1 //===-- AVRTargetMachine.cpp - Define TargetMachine for AVR ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the AVR specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AVRTargetMachine.h"
15 
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/CodeGen/TargetPassConfig.h"
18 #include "llvm/IR/LegacyPassManager.h"
19 #include "llvm/IR/Module.h"
20 #include "llvm/Support/TargetRegistry.h"
21 
22 #include "AVR.h"
23 #include "AVRTargetObjectFile.h"
24 #include "MCTargetDesc/AVRMCTargetDesc.h"
25 
26 namespace llvm {
27 
28 static const char *AVRDataLayout = "e-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8";
29 
30 /// Processes a CPU name.
31 static StringRef getCPU(StringRef CPU) {
32   if (CPU.empty() || CPU == "generic") {
33     return "avr2";
34   }
35 
36   return CPU;
37 }
38 
39 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
40   return RM.hasValue() ? *RM : Reloc::Static;
41 }
42 
43 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
44   if (CM)
45     return *CM;
46   return CodeModel::Small;
47 }
48 
49 AVRTargetMachine::AVRTargetMachine(const Target &T, const Triple &TT,
50                                    StringRef CPU, StringRef FS,
51                                    const TargetOptions &Options,
52                                    Optional<Reloc::Model> RM,
53                                    Optional<CodeModel::Model> CM,
54                                    CodeGenOpt::Level OL, bool JIT)
55     : TargetMachine(T, AVRDataLayout, TT, getCPU(CPU), FS, Options,
56                     getEffectiveRelocModel(RM), getEffectiveCodeModel(CM), OL),
57       SubTarget(TT, getCPU(CPU), FS, *this) {
58   this->TLOF = make_unique<AVRTargetObjectFile>();
59   initAsmInfo();
60 }
61 
62 namespace {
63 /// AVR Code Generator Pass Configuration Options.
64 class AVRPassConfig : public TargetPassConfig {
65 public:
66   AVRPassConfig(AVRTargetMachine &TM, PassManagerBase &PM)
67       : TargetPassConfig(TM, PM) {}
68 
69   AVRTargetMachine &getAVRTargetMachine() const {
70     return getTM<AVRTargetMachine>();
71   }
72 
73   bool addInstSelector() override;
74   void addPreSched2() override;
75   void addPreEmitPass() override;
76   void addPreRegAlloc() override;
77 };
78 } // namespace
79 
80 TargetPassConfig *AVRTargetMachine::createPassConfig(PassManagerBase &PM) {
81   return new AVRPassConfig(*this, PM);
82 }
83 
84 extern "C" void LLVMInitializeAVRTarget() {
85   // Register the target.
86   RegisterTargetMachine<AVRTargetMachine> X(getTheAVRTarget());
87 
88   auto &PR = *PassRegistry::getPassRegistry();
89   initializeAVRExpandPseudoPass(PR);
90   initializeAVRRelaxMemPass(PR);
91 }
92 
93 const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const {
94   return &SubTarget;
95 }
96 
97 const AVRSubtarget *AVRTargetMachine::getSubtargetImpl(const Function &) const {
98   return &SubTarget;
99 }
100 
101 //===----------------------------------------------------------------------===//
102 // Pass Pipeline Configuration
103 //===----------------------------------------------------------------------===//
104 
105 bool AVRPassConfig::addInstSelector() {
106   // Install an instruction selector.
107   addPass(createAVRISelDag(getAVRTargetMachine(), getOptLevel()));
108   // Create the frame analyzer pass used by the PEI pass.
109   addPass(createAVRFrameAnalyzerPass());
110 
111   return false;
112 }
113 
114 void AVRPassConfig::addPreRegAlloc() {
115   // Create the dynalloc SP save/restore pass to handle variable sized allocas.
116   addPass(createAVRDynAllocaSRPass());
117 }
118 
119 void AVRPassConfig::addPreSched2() {
120   addPass(createAVRRelaxMemPass());
121   addPass(createAVRExpandPseudoPass());
122 }
123 
124 void AVRPassConfig::addPreEmitPass() {
125   // Must run branch selection immediately preceding the asm printer.
126   addPass(&BranchRelaxationPassID);
127 }
128 
129 } // end of namespace llvm
130