1 //===-- AVRTargetMachine.cpp - Define TargetMachine for AVR ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the AVR specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AVRTargetMachine.h"
15 
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/CodeGen/TargetPassConfig.h"
18 #include "llvm/IR/LegacyPassManager.h"
19 #include "llvm/IR/Module.h"
20 #include "llvm/Support/TargetRegistry.h"
21 
22 #include "AVR.h"
23 #include "AVRTargetObjectFile.h"
24 #include "MCTargetDesc/AVRMCTargetDesc.h"
25 
26 namespace llvm {
27 
28 static const char *AVRDataLayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-n8";
29 
30 /// Processes a CPU name.
31 static StringRef getCPU(StringRef CPU) {
32   if (CPU.empty() || CPU == "generic") {
33     return "avr2";
34   }
35 
36   return CPU;
37 }
38 
39 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
40   return RM.hasValue() ? *RM : Reloc::Static;
41 }
42 
43 AVRTargetMachine::AVRTargetMachine(const Target &T, const Triple &TT,
44                                    StringRef CPU, StringRef FS,
45                                    const TargetOptions &Options,
46                                    Optional<Reloc::Model> RM,
47                                    Optional<CodeModel::Model> CM,
48                                    CodeGenOpt::Level OL,
49                                    bool JIT)
50     : LLVMTargetMachine(
51           T, AVRDataLayout, TT,
52           getCPU(CPU), FS, Options, getEffectiveRelocModel(RM),
53           CM, OL),
54       SubTarget(TT, getCPU(CPU), FS, *this) {
55   this->TLOF = make_unique<AVRTargetObjectFile>();
56   initAsmInfo();
57 }
58 
59 namespace {
60 /// AVR Code Generator Pass Configuration Options.
61 class AVRPassConfig : public TargetPassConfig {
62 public:
63   AVRPassConfig(AVRTargetMachine &TM, PassManagerBase &PM)
64       : TargetPassConfig(TM, PM) {}
65 
66   AVRTargetMachine &getAVRTargetMachine() const {
67     return getTM<AVRTargetMachine>();
68   }
69 
70   bool addInstSelector() override;
71   void addPreSched2() override;
72   void addPreEmitPass() override;
73   void addPreRegAlloc() override;
74 };
75 } // namespace
76 
77 TargetPassConfig *AVRTargetMachine::createPassConfig(PassManagerBase &PM) {
78   return new AVRPassConfig(*this, PM);
79 }
80 
81 extern "C" void LLVMInitializeAVRTarget() {
82   // Register the target.
83   RegisterTargetMachine<AVRTargetMachine> X(getTheAVRTarget());
84 
85   auto &PR = *PassRegistry::getPassRegistry();
86   initializeAVRExpandPseudoPass(PR);
87   initializeAVRRelaxMemPass(PR);
88 }
89 
90 const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const {
91   return &SubTarget;
92 }
93 
94 const AVRSubtarget *AVRTargetMachine::getSubtargetImpl(const Function &) const {
95   return &SubTarget;
96 }
97 
98 //===----------------------------------------------------------------------===//
99 // Pass Pipeline Configuration
100 //===----------------------------------------------------------------------===//
101 
102 bool AVRPassConfig::addInstSelector() {
103   // Install an instruction selector.
104   addPass(createAVRISelDag(getAVRTargetMachine(), getOptLevel()));
105   // Create the frame analyzer pass used by the PEI pass.
106   addPass(createAVRFrameAnalyzerPass());
107 
108   return false;
109 }
110 
111 void AVRPassConfig::addPreRegAlloc() {
112   // Create the dynalloc SP save/restore pass to handle variable sized allocas.
113   addPass(createAVRDynAllocaSRPass());
114 }
115 
116 void AVRPassConfig::addPreSched2() {
117   addPass(createAVRRelaxMemPass());
118   addPass(createAVRExpandPseudoPass());
119 }
120 
121 void AVRPassConfig::addPreEmitPass() {
122   // Must run branch selection immediately preceding the asm printer.
123   addPass(&BranchRelaxationPassID);
124 }
125 
126 } // end of namespace llvm
127