1 //===-- AVRRegisterInfo.cpp - AVR Register Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the AVR implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AVRRegisterInfo.h"
14 
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/CodeGen/TargetFrameLowering.h"
22 
23 #include "AVR.h"
24 #include "AVRInstrInfo.h"
25 #include "AVRTargetMachine.h"
26 #include "MCTargetDesc/AVRMCTargetDesc.h"
27 
28 #define GET_REGINFO_TARGET_DESC
29 #include "AVRGenRegisterInfo.inc"
30 
31 namespace llvm {
32 
33 AVRRegisterInfo::AVRRegisterInfo() : AVRGenRegisterInfo(0) {}
34 
35 const uint16_t *
36 AVRRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
37   CallingConv::ID CC = MF->getFunction().getCallingConv();
38 
39   return ((CC == CallingConv::AVR_INTR || CC == CallingConv::AVR_SIGNAL)
40               ? CSR_Interrupts_SaveList
41               : CSR_Normal_SaveList);
42 }
43 
44 const uint32_t *
45 AVRRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
46                                       CallingConv::ID CC) const {
47   return ((CC == CallingConv::AVR_INTR || CC == CallingConv::AVR_SIGNAL)
48               ? CSR_Interrupts_RegMask
49               : CSR_Normal_RegMask);
50 }
51 
52 BitVector AVRRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
53   BitVector Reserved(getNumRegs());
54 
55   // Reserve the intermediate result registers r1 and r2
56   // The result of instructions like 'mul' is always stored here.
57   Reserved.set(AVR::R0);
58   Reserved.set(AVR::R1);
59   Reserved.set(AVR::R1R0);
60 
61   //  Reserve the stack pointer.
62   Reserved.set(AVR::SPL);
63   Reserved.set(AVR::SPH);
64   Reserved.set(AVR::SP);
65 
66   // We tenatively reserve the frame pointer register r29:r28 because the
67   // function may require one, but we cannot tell until register allocation
68   // is complete, which can be too late.
69   //
70   // Instead we just unconditionally reserve the Y register.
71   //
72   // TODO: Write a pass to enumerate functions which reserved the Y register
73   //       but didn't end up needing a frame pointer. In these, we can
74   //       convert one or two of the spills inside to use the Y register.
75   Reserved.set(AVR::R28);
76   Reserved.set(AVR::R29);
77   Reserved.set(AVR::R29R28);
78 
79   return Reserved;
80 }
81 
82 const TargetRegisterClass *
83 AVRRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
84                                            const MachineFunction &MF) const {
85   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
86   if (TRI->isTypeLegalForClass(*RC, MVT::i16)) {
87     return &AVR::DREGSRegClass;
88   }
89 
90   if (TRI->isTypeLegalForClass(*RC, MVT::i8)) {
91     return &AVR::GPR8RegClass;
92   }
93 
94   llvm_unreachable("Invalid register size");
95 }
96 
97 /// Fold a frame offset shared between two add instructions into a single one.
98 static void foldFrameOffset(MachineBasicBlock::iterator &II, int &Offset,
99                             Register DstReg) {
100   MachineInstr &MI = *II;
101   int Opcode = MI.getOpcode();
102 
103   // Don't bother trying if the next instruction is not an add or a sub.
104   if ((Opcode != AVR::SUBIWRdK) && (Opcode != AVR::ADIWRdK)) {
105     return;
106   }
107 
108   // Check that DstReg matches with next instruction, otherwise the instruction
109   // is not related to stack address manipulation.
110   if (DstReg != MI.getOperand(0).getReg()) {
111     return;
112   }
113 
114   // Add the offset in the next instruction to our offset.
115   switch (Opcode) {
116   case AVR::SUBIWRdK:
117     Offset += -MI.getOperand(2).getImm();
118     break;
119   case AVR::ADIWRdK:
120     Offset += MI.getOperand(2).getImm();
121     break;
122   }
123 
124   // Finally remove the instruction.
125   II++;
126   MI.eraseFromParent();
127 }
128 
129 void AVRRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
130                                           int SPAdj, unsigned FIOperandNum,
131                                           RegScavenger *RS) const {
132   assert(SPAdj == 0 && "Unexpected SPAdj value");
133 
134   MachineInstr &MI = *II;
135   DebugLoc dl = MI.getDebugLoc();
136   MachineBasicBlock &MBB = *MI.getParent();
137   const MachineFunction &MF = *MBB.getParent();
138   const AVRTargetMachine &TM = (const AVRTargetMachine &)MF.getTarget();
139   const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
140   const MachineFrameInfo &MFI = MF.getFrameInfo();
141   const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();
142   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
143   int Offset = MFI.getObjectOffset(FrameIndex);
144 
145   // Add one to the offset because SP points to an empty slot.
146   Offset += MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;
147   // Fold incoming offset.
148   Offset += MI.getOperand(FIOperandNum + 1).getImm();
149 
150   // This is actually "load effective address" of the stack slot
151   // instruction. We have only two-address instructions, thus we need to
152   // expand it into move + add.
153   if (MI.getOpcode() == AVR::FRMIDX) {
154     MI.setDesc(TII.get(AVR::MOVWRdRr));
155     MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
156     MI.RemoveOperand(2);
157 
158     assert(Offset > 0 && "Invalid offset");
159 
160     // We need to materialize the offset via an add instruction.
161     unsigned Opcode;
162     Register DstReg = MI.getOperand(0).getReg();
163     assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer");
164 
165     II++; // Skip over the FRMIDX (and now MOVW) instruction.
166 
167     // Generally, to load a frame address two add instructions are emitted that
168     // could get folded into a single one:
169     //  movw    r31:r30, r29:r28
170     //  adiw    r31:r30, 29
171     //  adiw    r31:r30, 16
172     // to:
173     //  movw    r31:r30, r29:r28
174     //  adiw    r31:r30, 45
175     if (II != MBB.end())
176       foldFrameOffset(II, Offset, DstReg);
177 
178     // Select the best opcode based on DstReg and the offset size.
179     switch (DstReg) {
180     case AVR::R25R24:
181     case AVR::R27R26:
182     case AVR::R31R30: {
183       if (isUInt<6>(Offset)) {
184         Opcode = AVR::ADIWRdK;
185         break;
186       }
187       LLVM_FALLTHROUGH;
188     }
189     default: {
190       // This opcode will get expanded into a pair of subi/sbci.
191       Opcode = AVR::SUBIWRdK;
192       Offset = -Offset;
193       break;
194     }
195     }
196 
197     MachineInstr *New = BuildMI(MBB, II, dl, TII.get(Opcode), DstReg)
198                             .addReg(DstReg, RegState::Kill)
199                             .addImm(Offset);
200     New->getOperand(3).setIsDead();
201 
202     return;
203   }
204 
205   // If the offset is too big we have to adjust and restore the frame pointer
206   // to materialize a valid load/store with displacement.
207   //:TODO: consider using only one adiw/sbiw chain for more than one frame index
208   if (Offset > 62) {
209     unsigned AddOpc = AVR::ADIWRdK, SubOpc = AVR::SBIWRdK;
210     int AddOffset = Offset - 63 + 1;
211 
212     // For huge offsets where adiw/sbiw cannot be used use a pair of subi/sbci.
213     if ((Offset - 63 + 1) > 63) {
214       AddOpc = AVR::SUBIWRdK;
215       SubOpc = AVR::SUBIWRdK;
216       AddOffset = -AddOffset;
217     }
218 
219     // It is possible that the spiller places this frame instruction in between
220     // a compare and branch, invalidating the contents of SREG set by the
221     // compare instruction because of the add/sub pairs. Conservatively save and
222     // restore SREG before and after each add/sub pair.
223     BuildMI(MBB, II, dl, TII.get(AVR::INRdA), AVR::R0).addImm(0x3f);
224 
225     MachineInstr *New = BuildMI(MBB, II, dl, TII.get(AddOpc), AVR::R29R28)
226                             .addReg(AVR::R29R28, RegState::Kill)
227                             .addImm(AddOffset);
228     New->getOperand(3).setIsDead();
229 
230     // Restore SREG.
231     BuildMI(MBB, std::next(II), dl, TII.get(AVR::OUTARr))
232         .addImm(0x3f)
233         .addReg(AVR::R0, RegState::Kill);
234 
235     // No need to set SREG as dead here otherwise if the next instruction is a
236     // cond branch it will be using a dead register.
237     BuildMI(MBB, std::next(II), dl, TII.get(SubOpc), AVR::R29R28)
238         .addReg(AVR::R29R28, RegState::Kill)
239         .addImm(Offset - 63 + 1);
240 
241     Offset = 62;
242   }
243 
244   MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
245   assert(isUInt<6>(Offset) && "Offset is out of range");
246   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
247 }
248 
249 Register AVRRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
250   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
251   if (TFI->hasFP(MF)) {
252     // The Y pointer register
253     return AVR::R28;
254   }
255 
256   return AVR::SP;
257 }
258 
259 const TargetRegisterClass *
260 AVRRegisterInfo::getPointerRegClass(const MachineFunction &MF,
261                                     unsigned Kind) const {
262   // FIXME: Currently we're using avr-gcc as reference, so we restrict
263   // ptrs to Y and Z regs. Though avr-gcc has buggy implementation
264   // of memory constraint, so we can fix it and bit avr-gcc here ;-)
265   return &AVR::PTRDISPREGSRegClass;
266 }
267 
268 void AVRRegisterInfo::splitReg(Register Reg, Register &LoReg,
269                                Register &HiReg) const {
270   assert(AVR::DREGSRegClass.contains(Reg) && "can only split 16-bit registers");
271 
272   LoReg = getSubReg(Reg, AVR::sub_lo);
273   HiReg = getSubReg(Reg, AVR::sub_hi);
274 }
275 
276 bool AVRRegisterInfo::shouldCoalesce(MachineInstr *MI,
277                                      const TargetRegisterClass *SrcRC,
278                                      unsigned SubReg,
279                                      const TargetRegisterClass *DstRC,
280                                      unsigned DstSubReg,
281                                      const TargetRegisterClass *NewRC,
282                                      LiveIntervals &LIS) const {
283   if(this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) {
284     return false;
285   }
286 
287   return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, NewRC, LIS);
288 }
289 
290 } // end of namespace llvm
291