1 //===-- AVRRegisterInfo.cpp - AVR Register Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AVR implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AVRRegisterInfo.h"
15 
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/Target/TargetFrameLowering.h"
22 
23 #include "AVR.h"
24 #include "AVRInstrInfo.h"
25 #include "AVRTargetMachine.h"
26 #include "MCTargetDesc/AVRMCTargetDesc.h"
27 
28 #define GET_REGINFO_TARGET_DESC
29 #include "AVRGenRegisterInfo.inc"
30 
31 namespace llvm {
32 
33 AVRRegisterInfo::AVRRegisterInfo() : AVRGenRegisterInfo(0) {}
34 
35 const uint16_t *
36 AVRRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
37   CallingConv::ID CC = MF->getFunction()->getCallingConv();
38 
39   return ((CC == CallingConv::AVR_INTR || CC == CallingConv::AVR_SIGNAL)
40               ? CSR_Interrupts_SaveList
41               : CSR_Normal_SaveList);
42 }
43 
44 const uint32_t *
45 AVRRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
46                                       CallingConv::ID CC) const {
47   return ((CC == CallingConv::AVR_INTR || CC == CallingConv::AVR_SIGNAL)
48               ? CSR_Interrupts_RegMask
49               : CSR_Normal_RegMask);
50 }
51 
52 BitVector AVRRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
53   BitVector Reserved(getNumRegs());
54   const AVRTargetMachine &TM = static_cast<const AVRTargetMachine&>(MF.getTarget());
55   const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();
56 
57   // Reserve the intermediate result registers r1 and r2
58   // The result of instructions like 'mul' is always stored here.
59   Reserved.set(AVR::R0);
60   Reserved.set(AVR::R1);
61   Reserved.set(AVR::R1R0);
62 
63   //  Reserve the stack pointer.
64   Reserved.set(AVR::SPL);
65   Reserved.set(AVR::SPH);
66   Reserved.set(AVR::SP);
67 
68   // We tenatively reserve the frame pointer register r29:r28 because the
69   // function may require one, but we cannot tell until register allocation
70   // is complete, which can be too late.
71   //
72   // Instead we just unconditionally reserve the Y register.
73   //
74   // TODO: Write a pass to enumerate functions which reserved the Y register
75   //       but didn't end up needing a frame pointer. In these, we can
76   //       convert one or two of the spills inside to use the Y register.
77   Reserved.set(AVR::R28);
78   Reserved.set(AVR::R29);
79   Reserved.set(AVR::R29R28);
80 
81   return Reserved;
82 }
83 
84 const TargetRegisterClass *
85 AVRRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
86                                            const MachineFunction &MF) const {
87   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
88   if (TRI->isTypeLegalForClass(*RC, MVT::i16)) {
89     return &AVR::DREGSRegClass;
90   }
91 
92   if (TRI->isTypeLegalForClass(*RC, MVT::i8)) {
93     return &AVR::GPR8RegClass;
94   }
95 
96   llvm_unreachable("Invalid register size");
97 }
98 
99 /// Fold a frame offset shared between two add instructions into a single one.
100 static void foldFrameOffset(MachineInstr &MI, int &Offset, unsigned DstReg) {
101   int Opcode = MI.getOpcode();
102 
103   // Don't bother trying if the next instruction is not an add or a sub.
104   if ((Opcode != AVR::SUBIWRdK) && (Opcode != AVR::ADIWRdK)) {
105     return;
106   }
107 
108   // Check that DstReg matches with next instruction, otherwise the instruction
109   // is not related to stack address manipulation.
110   if (DstReg != MI.getOperand(0).getReg()) {
111     return;
112   }
113 
114   // Add the offset in the next instruction to our offset.
115   switch (Opcode) {
116   case AVR::SUBIWRdK:
117     Offset += -MI.getOperand(2).getImm();
118     break;
119   case AVR::ADIWRdK:
120     Offset += MI.getOperand(2).getImm();
121     break;
122   }
123 
124   // Finally remove the instruction.
125   MI.eraseFromParent();
126 }
127 
128 void AVRRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
129                                           int SPAdj, unsigned FIOperandNum,
130                                           RegScavenger *RS) const {
131   assert(SPAdj == 0 && "Unexpected SPAdj value");
132 
133   MachineInstr &MI = *II;
134   DebugLoc dl = MI.getDebugLoc();
135   MachineBasicBlock &MBB = *MI.getParent();
136   const MachineFunction &MF = *MBB.getParent();
137   const AVRTargetMachine &TM = (const AVRTargetMachine &)MF.getTarget();
138   const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
139   const MachineFrameInfo &MFI = MF.getFrameInfo();
140   const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();
141   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
142   int Offset = MFI.getObjectOffset(FrameIndex);
143 
144   // Add one to the offset because SP points to an empty slot.
145   Offset += MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;
146   // Fold incoming offset.
147   Offset += MI.getOperand(FIOperandNum + 1).getImm();
148 
149   // This is actually "load effective address" of the stack slot
150   // instruction. We have only two-address instructions, thus we need to
151   // expand it into move + add.
152   if (MI.getOpcode() == AVR::FRMIDX) {
153     MI.setDesc(TII.get(AVR::MOVWRdRr));
154     MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
155 
156     assert(Offset > 0 && "Invalid offset");
157 
158     // We need to materialize the offset via an add instruction.
159     unsigned Opcode;
160     unsigned DstReg = MI.getOperand(0).getReg();
161     assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer");
162 
163     // Generally, to load a frame address two add instructions are emitted that
164     // could get folded into a single one:
165     //  movw    r31:r30, r29:r28
166     //  adiw    r31:r30, 29
167     //  adiw    r31:r30, 16
168     // to:
169     //  movw    r31:r30, r29:r28
170     //  adiw    r31:r30, 45
171     foldFrameOffset(*std::next(II), Offset, DstReg);
172 
173     // Select the best opcode based on DstReg and the offset size.
174     switch (DstReg) {
175     case AVR::R25R24:
176     case AVR::R27R26:
177     case AVR::R31R30: {
178       if (isUInt<6>(Offset)) {
179         Opcode = AVR::ADIWRdK;
180         break;
181       }
182       LLVM_FALLTHROUGH;
183     }
184     default: {
185       // This opcode will get expanded into a pair of subi/sbci.
186       Opcode = AVR::SUBIWRdK;
187       Offset = -Offset;
188       break;
189     }
190     }
191 
192     MachineInstr *New = BuildMI(MBB, std::next(II), dl, TII.get(Opcode), DstReg)
193                             .addReg(DstReg, RegState::Kill)
194                             .addImm(Offset);
195     New->getOperand(3).setIsDead();
196 
197     return;
198   }
199 
200   // If the offset is too big we have to adjust and restore the frame pointer
201   // to materialize a valid load/store with displacement.
202   //:TODO: consider using only one adiw/sbiw chain for more than one frame index
203   if (Offset > 63) {
204     unsigned AddOpc = AVR::ADIWRdK, SubOpc = AVR::SBIWRdK;
205     int AddOffset = Offset - 63 + 1;
206 
207     // For huge offsets where adiw/sbiw cannot be used use a pair of subi/sbci.
208     if ((Offset - 63 + 1) > 63) {
209       AddOpc = AVR::SUBIWRdK;
210       SubOpc = AVR::SUBIWRdK;
211       AddOffset = -AddOffset;
212     }
213 
214     // It is possible that the spiller places this frame instruction in between
215     // a compare and branch, invalidating the contents of SREG set by the
216     // compare instruction because of the add/sub pairs. Conservatively save and
217     // restore SREG before and after each add/sub pair.
218     BuildMI(MBB, II, dl, TII.get(AVR::INRdA), AVR::R0).addImm(0x3f);
219 
220     MachineInstr *New = BuildMI(MBB, II, dl, TII.get(AddOpc), AVR::R29R28)
221                             .addReg(AVR::R29R28, RegState::Kill)
222                             .addImm(AddOffset);
223     New->getOperand(3).setIsDead();
224 
225     // Restore SREG.
226     BuildMI(MBB, std::next(II), dl, TII.get(AVR::OUTARr))
227         .addImm(0x3f)
228         .addReg(AVR::R0, RegState::Kill);
229 
230     // No need to set SREG as dead here otherwise if the next instruction is a
231     // cond branch it will be using a dead register.
232     New = BuildMI(MBB, std::next(II), dl, TII.get(SubOpc), AVR::R29R28)
233               .addReg(AVR::R29R28, RegState::Kill)
234               .addImm(Offset - 63 + 1);
235 
236     Offset = 62;
237   }
238 
239   MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
240   assert(isUInt<6>(Offset) && "Offset is out of range");
241   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
242 }
243 
244 unsigned AVRRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
245   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
246   if (TFI->hasFP(MF)) {
247     // The Y pointer register
248     return AVR::R28;
249   }
250 
251   return AVR::SP;
252 }
253 
254 const TargetRegisterClass *
255 AVRRegisterInfo::getPointerRegClass(const MachineFunction &MF,
256                                     unsigned Kind) const {
257   // FIXME: Currently we're using avr-gcc as reference, so we restrict
258   // ptrs to Y and Z regs. Though avr-gcc has buggy implementation
259   // of memory constraint, so we can fix it and bit avr-gcc here ;-)
260   return &AVR::PTRDISPREGSRegClass;
261 }
262 
263 void AVRRegisterInfo::splitReg(unsigned Reg,
264                                unsigned &LoReg,
265                                unsigned &HiReg) const {
266     assert(AVR::DREGSRegClass.contains(Reg) && "can only split 16-bit registers");
267 
268     LoReg = getSubReg(Reg, AVR::sub_lo);
269     HiReg = getSubReg(Reg, AVR::sub_hi);
270 }
271 
272 } // end of namespace llvm
273 
274