1 //===-- AVRRegisterInfo.cpp - AVR Register Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AVR implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AVRRegisterInfo.h"
15 
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/Target/TargetFrameLowering.h"
22 
23 #include "AVR.h"
24 #include "AVRInstrInfo.h"
25 #include "AVRTargetMachine.h"
26 #include "MCTargetDesc/AVRMCTargetDesc.h"
27 
28 #define GET_REGINFO_TARGET_DESC
29 #include "AVRGenRegisterInfo.inc"
30 
31 namespace llvm {
32 
33 AVRRegisterInfo::AVRRegisterInfo() : AVRGenRegisterInfo(0) {}
34 
35 const uint16_t *
36 AVRRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
37   CallingConv::ID CC = MF->getFunction()->getCallingConv();
38 
39   return ((CC == CallingConv::AVR_INTR || CC == CallingConv::AVR_SIGNAL)
40               ? CSR_Interrupts_SaveList
41               : CSR_Normal_SaveList);
42 }
43 
44 const uint32_t *
45 AVRRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
46                                       CallingConv::ID CC) const {
47   return ((CC == CallingConv::AVR_INTR || CC == CallingConv::AVR_SIGNAL)
48               ? CSR_Interrupts_RegMask
49               : CSR_Normal_RegMask);
50 }
51 
52 BitVector AVRRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
53   BitVector Reserved(getNumRegs());
54 
55   // Reserve the intermediate result registers r1 and r2
56   // The result of instructions like 'mul' is always stored here.
57   Reserved.set(AVR::R0);
58   Reserved.set(AVR::R1);
59   Reserved.set(AVR::R1R0);
60 
61   //  Reserve the stack pointer.
62   Reserved.set(AVR::SPL);
63   Reserved.set(AVR::SPH);
64   Reserved.set(AVR::SP);
65 
66   // We tenatively reserve the frame pointer register r29:r28 because the
67   // function may require one, but we cannot tell until register allocation
68   // is complete, which can be too late.
69   //
70   // Instead we just unconditionally reserve the Y register.
71   //
72   // TODO: Write a pass to enumerate functions which reserved the Y register
73   //       but didn't end up needing a frame pointer. In these, we can
74   //       convert one or two of the spills inside to use the Y register.
75   Reserved.set(AVR::R28);
76   Reserved.set(AVR::R29);
77   Reserved.set(AVR::R29R28);
78 
79   return Reserved;
80 }
81 
82 const TargetRegisterClass *
83 AVRRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
84                                            const MachineFunction &MF) const {
85   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
86   if (TRI->isTypeLegalForClass(*RC, MVT::i16)) {
87     return &AVR::DREGSRegClass;
88   }
89 
90   if (TRI->isTypeLegalForClass(*RC, MVT::i8)) {
91     return &AVR::GPR8RegClass;
92   }
93 
94   llvm_unreachable("Invalid register size");
95 }
96 
97 /// Fold a frame offset shared between two add instructions into a single one.
98 static void foldFrameOffset(MachineInstr &MI, int &Offset, unsigned DstReg) {
99   int Opcode = MI.getOpcode();
100 
101   // Don't bother trying if the next instruction is not an add or a sub.
102   if ((Opcode != AVR::SUBIWRdK) && (Opcode != AVR::ADIWRdK)) {
103     return;
104   }
105 
106   // Check that DstReg matches with next instruction, otherwise the instruction
107   // is not related to stack address manipulation.
108   if (DstReg != MI.getOperand(0).getReg()) {
109     return;
110   }
111 
112   // Add the offset in the next instruction to our offset.
113   switch (Opcode) {
114   case AVR::SUBIWRdK:
115     Offset += -MI.getOperand(2).getImm();
116     break;
117   case AVR::ADIWRdK:
118     Offset += MI.getOperand(2).getImm();
119     break;
120   }
121 
122   // Finally remove the instruction.
123   MI.eraseFromParent();
124 }
125 
126 void AVRRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
127                                           int SPAdj, unsigned FIOperandNum,
128                                           RegScavenger *RS) const {
129   assert(SPAdj == 0 && "Unexpected SPAdj value");
130 
131   MachineInstr &MI = *II;
132   DebugLoc dl = MI.getDebugLoc();
133   MachineBasicBlock &MBB = *MI.getParent();
134   const MachineFunction &MF = *MBB.getParent();
135   const AVRTargetMachine &TM = (const AVRTargetMachine &)MF.getTarget();
136   const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
137   const MachineFrameInfo &MFI = MF.getFrameInfo();
138   const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();
139   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
140   int Offset = MFI.getObjectOffset(FrameIndex);
141 
142   // Add one to the offset because SP points to an empty slot.
143   Offset += MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;
144   // Fold incoming offset.
145   Offset += MI.getOperand(FIOperandNum + 1).getImm();
146 
147   // This is actually "load effective address" of the stack slot
148   // instruction. We have only two-address instructions, thus we need to
149   // expand it into move + add.
150   if (MI.getOpcode() == AVR::FRMIDX) {
151     MI.setDesc(TII.get(AVR::MOVWRdRr));
152     MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
153 
154     assert(Offset > 0 && "Invalid offset");
155 
156     // We need to materialize the offset via an add instruction.
157     unsigned Opcode;
158     unsigned DstReg = MI.getOperand(0).getReg();
159     assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer");
160 
161     // Generally, to load a frame address two add instructions are emitted that
162     // could get folded into a single one:
163     //  movw    r31:r30, r29:r28
164     //  adiw    r31:r30, 29
165     //  adiw    r31:r30, 16
166     // to:
167     //  movw    r31:r30, r29:r28
168     //  adiw    r31:r30, 45
169     foldFrameOffset(*std::next(II), Offset, DstReg);
170 
171     // Select the best opcode based on DstReg and the offset size.
172     switch (DstReg) {
173     case AVR::R25R24:
174     case AVR::R27R26:
175     case AVR::R31R30: {
176       if (isUInt<6>(Offset)) {
177         Opcode = AVR::ADIWRdK;
178         break;
179       }
180       LLVM_FALLTHROUGH;
181     }
182     default: {
183       // This opcode will get expanded into a pair of subi/sbci.
184       Opcode = AVR::SUBIWRdK;
185       Offset = -Offset;
186       break;
187     }
188     }
189 
190     MachineInstr *New = BuildMI(MBB, std::next(II), dl, TII.get(Opcode), DstReg)
191                             .addReg(DstReg, RegState::Kill)
192                             .addImm(Offset);
193     New->getOperand(3).setIsDead();
194 
195     return;
196   }
197 
198   // If the offset is too big we have to adjust and restore the frame pointer
199   // to materialize a valid load/store with displacement.
200   //:TODO: consider using only one adiw/sbiw chain for more than one frame index
201   if (Offset > 63) {
202     unsigned AddOpc = AVR::ADIWRdK, SubOpc = AVR::SBIWRdK;
203     int AddOffset = Offset - 63 + 1;
204 
205     // For huge offsets where adiw/sbiw cannot be used use a pair of subi/sbci.
206     if ((Offset - 63 + 1) > 63) {
207       AddOpc = AVR::SUBIWRdK;
208       SubOpc = AVR::SUBIWRdK;
209       AddOffset = -AddOffset;
210     }
211 
212     // It is possible that the spiller places this frame instruction in between
213     // a compare and branch, invalidating the contents of SREG set by the
214     // compare instruction because of the add/sub pairs. Conservatively save and
215     // restore SREG before and after each add/sub pair.
216     BuildMI(MBB, II, dl, TII.get(AVR::INRdA), AVR::R0).addImm(0x3f);
217 
218     MachineInstr *New = BuildMI(MBB, II, dl, TII.get(AddOpc), AVR::R29R28)
219                             .addReg(AVR::R29R28, RegState::Kill)
220                             .addImm(AddOffset);
221     New->getOperand(3).setIsDead();
222 
223     // Restore SREG.
224     BuildMI(MBB, std::next(II), dl, TII.get(AVR::OUTARr))
225         .addImm(0x3f)
226         .addReg(AVR::R0, RegState::Kill);
227 
228     // No need to set SREG as dead here otherwise if the next instruction is a
229     // cond branch it will be using a dead register.
230     New = BuildMI(MBB, std::next(II), dl, TII.get(SubOpc), AVR::R29R28)
231               .addReg(AVR::R29R28, RegState::Kill)
232               .addImm(Offset - 63 + 1);
233 
234     Offset = 62;
235   }
236 
237   MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
238   assert(isUInt<6>(Offset) && "Offset is out of range");
239   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
240 }
241 
242 unsigned AVRRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
243   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
244   if (TFI->hasFP(MF)) {
245     // The Y pointer register
246     return AVR::R28;
247   }
248 
249   return AVR::SP;
250 }
251 
252 const TargetRegisterClass *
253 AVRRegisterInfo::getPointerRegClass(const MachineFunction &MF,
254                                     unsigned Kind) const {
255   // FIXME: Currently we're using avr-gcc as reference, so we restrict
256   // ptrs to Y and Z regs. Though avr-gcc has buggy implementation
257   // of memory constraint, so we can fix it and bit avr-gcc here ;-)
258   return &AVR::PTRDISPREGSRegClass;
259 }
260 
261 void AVRRegisterInfo::splitReg(unsigned Reg,
262                                unsigned &LoReg,
263                                unsigned &HiReg) const {
264     assert(AVR::DREGSRegClass.contains(Reg) && "can only split 16-bit registers");
265 
266     LoReg = getSubReg(Reg, AVR::sub_lo);
267     HiReg = getSubReg(Reg, AVR::sub_hi);
268 }
269 
270 } // end of namespace llvm
271