1 //===-- AVRRegisterInfo.cpp - AVR Register Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the AVR implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AVRRegisterInfo.h"
14 
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetFrameLowering.h"
21 #include "llvm/IR/Function.h"
22 
23 #include "AVR.h"
24 #include "AVRInstrInfo.h"
25 #include "AVRMachineFunctionInfo.h"
26 #include "AVRTargetMachine.h"
27 #include "MCTargetDesc/AVRMCTargetDesc.h"
28 
29 #define GET_REGINFO_TARGET_DESC
30 #include "AVRGenRegisterInfo.inc"
31 
32 namespace llvm {
33 
34 AVRRegisterInfo::AVRRegisterInfo() : AVRGenRegisterInfo(0) {}
35 
36 const uint16_t *
37 AVRRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
38   const AVRMachineFunctionInfo *AFI = MF->getInfo<AVRMachineFunctionInfo>();
39 
40   return AFI->isInterruptOrSignalHandler() ? CSR_Interrupts_SaveList
41                                            : CSR_Normal_SaveList;
42 }
43 
44 const uint32_t *
45 AVRRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
46                                       CallingConv::ID CC) const {
47   return CSR_Normal_RegMask;
48 }
49 
50 BitVector AVRRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
51   BitVector Reserved(getNumRegs());
52 
53   // Reserve the intermediate result registers r1 and r2
54   // The result of instructions like 'mul' is always stored here.
55   Reserved.set(AVR::R0);
56   Reserved.set(AVR::R1);
57   Reserved.set(AVR::R1R0);
58 
59   //  Reserve the stack pointer.
60   Reserved.set(AVR::SPL);
61   Reserved.set(AVR::SPH);
62   Reserved.set(AVR::SP);
63 
64   // We tenatively reserve the frame pointer register r29:r28 because the
65   // function may require one, but we cannot tell until register allocation
66   // is complete, which can be too late.
67   //
68   // Instead we just unconditionally reserve the Y register.
69   //
70   // TODO: Write a pass to enumerate functions which reserved the Y register
71   //       but didn't end up needing a frame pointer. In these, we can
72   //       convert one or two of the spills inside to use the Y register.
73   Reserved.set(AVR::R28);
74   Reserved.set(AVR::R29);
75   Reserved.set(AVR::R29R28);
76 
77   return Reserved;
78 }
79 
80 const TargetRegisterClass *
81 AVRRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
82                                            const MachineFunction &MF) const {
83   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
84   if (TRI->isTypeLegalForClass(*RC, MVT::i16)) {
85     return &AVR::DREGSRegClass;
86   }
87 
88   if (TRI->isTypeLegalForClass(*RC, MVT::i8)) {
89     return &AVR::GPR8RegClass;
90   }
91 
92   llvm_unreachable("Invalid register size");
93 }
94 
95 /// Fold a frame offset shared between two add instructions into a single one.
96 static void foldFrameOffset(MachineBasicBlock::iterator &II, int &Offset,
97                             Register DstReg) {
98   MachineInstr &MI = *II;
99   int Opcode = MI.getOpcode();
100 
101   // Don't bother trying if the next instruction is not an add or a sub.
102   if ((Opcode != AVR::SUBIWRdK) && (Opcode != AVR::ADIWRdK)) {
103     return;
104   }
105 
106   // Check that DstReg matches with next instruction, otherwise the instruction
107   // is not related to stack address manipulation.
108   if (DstReg != MI.getOperand(0).getReg()) {
109     return;
110   }
111 
112   // Add the offset in the next instruction to our offset.
113   switch (Opcode) {
114   case AVR::SUBIWRdK:
115     Offset += -MI.getOperand(2).getImm();
116     break;
117   case AVR::ADIWRdK:
118     Offset += MI.getOperand(2).getImm();
119     break;
120   }
121 
122   // Finally remove the instruction.
123   II++;
124   MI.eraseFromParent();
125 }
126 
127 void AVRRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
128                                           int SPAdj, unsigned FIOperandNum,
129                                           RegScavenger *RS) const {
130   assert(SPAdj == 0 && "Unexpected SPAdj value");
131 
132   MachineInstr &MI = *II;
133   DebugLoc dl = MI.getDebugLoc();
134   MachineBasicBlock &MBB = *MI.getParent();
135   const MachineFunction &MF = *MBB.getParent();
136   const AVRTargetMachine &TM = (const AVRTargetMachine &)MF.getTarget();
137   const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
138   const MachineFrameInfo &MFI = MF.getFrameInfo();
139   const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();
140   const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
141   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
142   int Offset = MFI.getObjectOffset(FrameIndex);
143 
144   // Add one to the offset because SP points to an empty slot.
145   Offset += MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;
146   // Fold incoming offset.
147   Offset += MI.getOperand(FIOperandNum + 1).getImm();
148 
149   // This is actually "load effective address" of the stack slot
150   // instruction. We have only two-address instructions, thus we need to
151   // expand it into move + add.
152   if (MI.getOpcode() == AVR::FRMIDX) {
153     MI.setDesc(TII.get(AVR::MOVWRdRr));
154     MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
155     MI.removeOperand(2);
156 
157     assert(Offset > 0 && "Invalid offset");
158 
159     // We need to materialize the offset via an add instruction.
160     unsigned Opcode;
161     Register DstReg = MI.getOperand(0).getReg();
162     assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer");
163 
164     II++; // Skip over the FRMIDX (and now MOVW) instruction.
165 
166     // Generally, to load a frame address two add instructions are emitted that
167     // could get folded into a single one:
168     //  movw    r31:r30, r29:r28
169     //  adiw    r31:r30, 29
170     //  adiw    r31:r30, 16
171     // to:
172     //  movw    r31:r30, r29:r28
173     //  adiw    r31:r30, 45
174     if (II != MBB.end())
175       foldFrameOffset(II, Offset, DstReg);
176 
177     // Select the best opcode based on DstReg and the offset size.
178     switch (DstReg) {
179     case AVR::R25R24:
180     case AVR::R27R26:
181     case AVR::R31R30: {
182       if (isUInt<6>(Offset)) {
183         Opcode = AVR::ADIWRdK;
184         break;
185       }
186       LLVM_FALLTHROUGH;
187     }
188     default: {
189       // This opcode will get expanded into a pair of subi/sbci.
190       Opcode = AVR::SUBIWRdK;
191       Offset = -Offset;
192       break;
193     }
194     }
195 
196     MachineInstr *New = BuildMI(MBB, II, dl, TII.get(Opcode), DstReg)
197                             .addReg(DstReg, RegState::Kill)
198                             .addImm(Offset);
199     New->getOperand(3).setIsDead();
200 
201     return;
202   }
203 
204   // If the offset is too big we have to adjust and restore the frame pointer
205   // to materialize a valid load/store with displacement.
206   //: TODO: consider using only one adiw/sbiw chain for more than one frame
207   //: index
208   if (Offset > 62) {
209     unsigned AddOpc = AVR::ADIWRdK, SubOpc = AVR::SBIWRdK;
210     int AddOffset = Offset - 63 + 1;
211 
212     // For huge offsets where adiw/sbiw cannot be used use a pair of subi/sbci.
213     if ((Offset - 63 + 1) > 63) {
214       AddOpc = AVR::SUBIWRdK;
215       SubOpc = AVR::SUBIWRdK;
216       AddOffset = -AddOffset;
217     }
218 
219     // It is possible that the spiller places this frame instruction in between
220     // a compare and branch, invalidating the contents of SREG set by the
221     // compare instruction because of the add/sub pairs. Conservatively save and
222     // restore SREG before and after each add/sub pair.
223     BuildMI(MBB, II, dl, TII.get(AVR::INRdA), AVR::R0)
224         .addImm(STI.getIORegSREG());
225 
226     MachineInstr *New = BuildMI(MBB, II, dl, TII.get(AddOpc), AVR::R29R28)
227                             .addReg(AVR::R29R28, RegState::Kill)
228                             .addImm(AddOffset);
229     New->getOperand(3).setIsDead();
230 
231     // Restore SREG.
232     BuildMI(MBB, std::next(II), dl, TII.get(AVR::OUTARr))
233         .addImm(STI.getIORegSREG())
234         .addReg(AVR::R0, RegState::Kill);
235 
236     // No need to set SREG as dead here otherwise if the next instruction is a
237     // cond branch it will be using a dead register.
238     BuildMI(MBB, std::next(II), dl, TII.get(SubOpc), AVR::R29R28)
239         .addReg(AVR::R29R28, RegState::Kill)
240         .addImm(Offset - 63 + 1);
241 
242     Offset = 62;
243   }
244 
245   MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
246   assert(isUInt<6>(Offset) && "Offset is out of range");
247   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
248 }
249 
250 Register AVRRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
251   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
252   if (TFI->hasFP(MF)) {
253     // The Y pointer register
254     return AVR::R28;
255   }
256 
257   return AVR::SP;
258 }
259 
260 const TargetRegisterClass *
261 AVRRegisterInfo::getPointerRegClass(const MachineFunction &MF,
262                                     unsigned Kind) const {
263   // FIXME: Currently we're using avr-gcc as reference, so we restrict
264   // ptrs to Y and Z regs. Though avr-gcc has buggy implementation
265   // of memory constraint, so we can fix it and bit avr-gcc here ;-)
266   return &AVR::PTRDISPREGSRegClass;
267 }
268 
269 void AVRRegisterInfo::splitReg(Register Reg, Register &LoReg,
270                                Register &HiReg) const {
271   assert(AVR::DREGSRegClass.contains(Reg) && "can only split 16-bit registers");
272 
273   LoReg = getSubReg(Reg, AVR::sub_lo);
274   HiReg = getSubReg(Reg, AVR::sub_hi);
275 }
276 
277 bool AVRRegisterInfo::shouldCoalesce(
278     MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg,
279     const TargetRegisterClass *DstRC, unsigned DstSubReg,
280     const TargetRegisterClass *NewRC, LiveIntervals &LIS) const {
281   if (this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) {
282     return false;
283   }
284 
285   return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg,
286                                             NewRC, LIS);
287 }
288 
289 } // end of namespace llvm
290