1 //===-- AVRRegisterInfo.cpp - AVR Register Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AVR implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AVRRegisterInfo.h"
15 
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/Target/TargetFrameLowering.h"
22 
23 #include "AVR.h"
24 #include "AVRInstrInfo.h"
25 #include "AVRTargetMachine.h"
26 #include "MCTargetDesc/AVRMCTargetDesc.h"
27 
28 #define GET_REGINFO_TARGET_DESC
29 #include "AVRGenRegisterInfo.inc"
30 
31 namespace llvm {
32 
33 AVRRegisterInfo::AVRRegisterInfo() : AVRGenRegisterInfo(0) {}
34 
35 const uint16_t *
36 AVRRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
37   CallingConv::ID CC = MF->getFunction()->getCallingConv();
38 
39   return ((CC == CallingConv::AVR_INTR || CC == CallingConv::AVR_SIGNAL)
40               ? CSR_Interrupts_SaveList
41               : CSR_Normal_SaveList);
42 }
43 
44 const uint32_t *
45 AVRRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
46                                       CallingConv::ID CC) const {
47   return ((CC == CallingConv::AVR_INTR || CC == CallingConv::AVR_SIGNAL)
48               ? CSR_Interrupts_RegMask
49               : CSR_Normal_RegMask);
50 }
51 
52 BitVector AVRRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
53   BitVector Reserved(getNumRegs());
54   const AVRTargetMachine &TM = static_cast<const AVRTargetMachine&>(MF.getTarget());
55 
56   // Reserve the intermediate result registers r1 and r2
57   // The result of instructions like 'mul' is always stored here.
58   Reserved.set(AVR::R0);
59   Reserved.set(AVR::R1);
60   Reserved.set(AVR::R1R0);
61 
62   //  Reserve the stack pointer.
63   Reserved.set(AVR::SPL);
64   Reserved.set(AVR::SPH);
65   Reserved.set(AVR::SP);
66 
67   // We tenatively reserve the frame pointer register r29:r28 because the
68   // function may require one, but we cannot tell until register allocation
69   // is complete, which can be too late.
70   //
71   // Instead we just unconditionally reserve the Y register.
72   //
73   // TODO: Write a pass to enumerate functions which reserved the Y register
74   //       but didn't end up needing a frame pointer. In these, we can
75   //       convert one or two of the spills inside to use the Y register.
76   Reserved.set(AVR::R28);
77   Reserved.set(AVR::R29);
78   Reserved.set(AVR::R29R28);
79 
80   return Reserved;
81 }
82 
83 const TargetRegisterClass *
84 AVRRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
85                                            const MachineFunction &MF) const {
86   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
87   if (TRI->isTypeLegalForClass(*RC, MVT::i16)) {
88     return &AVR::DREGSRegClass;
89   }
90 
91   if (TRI->isTypeLegalForClass(*RC, MVT::i8)) {
92     return &AVR::GPR8RegClass;
93   }
94 
95   llvm_unreachable("Invalid register size");
96 }
97 
98 /// Fold a frame offset shared between two add instructions into a single one.
99 static void foldFrameOffset(MachineInstr &MI, int &Offset, unsigned DstReg) {
100   int Opcode = MI.getOpcode();
101 
102   // Don't bother trying if the next instruction is not an add or a sub.
103   if ((Opcode != AVR::SUBIWRdK) && (Opcode != AVR::ADIWRdK)) {
104     return;
105   }
106 
107   // Check that DstReg matches with next instruction, otherwise the instruction
108   // is not related to stack address manipulation.
109   if (DstReg != MI.getOperand(0).getReg()) {
110     return;
111   }
112 
113   // Add the offset in the next instruction to our offset.
114   switch (Opcode) {
115   case AVR::SUBIWRdK:
116     Offset += -MI.getOperand(2).getImm();
117     break;
118   case AVR::ADIWRdK:
119     Offset += MI.getOperand(2).getImm();
120     break;
121   }
122 
123   // Finally remove the instruction.
124   MI.eraseFromParent();
125 }
126 
127 void AVRRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
128                                           int SPAdj, unsigned FIOperandNum,
129                                           RegScavenger *RS) const {
130   assert(SPAdj == 0 && "Unexpected SPAdj value");
131 
132   MachineInstr &MI = *II;
133   DebugLoc dl = MI.getDebugLoc();
134   MachineBasicBlock &MBB = *MI.getParent();
135   const MachineFunction &MF = *MBB.getParent();
136   const AVRTargetMachine &TM = (const AVRTargetMachine &)MF.getTarget();
137   const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
138   const MachineFrameInfo &MFI = MF.getFrameInfo();
139   const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();
140   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
141   int Offset = MFI.getObjectOffset(FrameIndex);
142 
143   // Add one to the offset because SP points to an empty slot.
144   Offset += MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;
145   // Fold incoming offset.
146   Offset += MI.getOperand(FIOperandNum + 1).getImm();
147 
148   // This is actually "load effective address" of the stack slot
149   // instruction. We have only two-address instructions, thus we need to
150   // expand it into move + add.
151   if (MI.getOpcode() == AVR::FRMIDX) {
152     MI.setDesc(TII.get(AVR::MOVWRdRr));
153     MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
154 
155     assert(Offset > 0 && "Invalid offset");
156 
157     // We need to materialize the offset via an add instruction.
158     unsigned Opcode;
159     unsigned DstReg = MI.getOperand(0).getReg();
160     assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer");
161 
162     // Generally, to load a frame address two add instructions are emitted that
163     // could get folded into a single one:
164     //  movw    r31:r30, r29:r28
165     //  adiw    r31:r30, 29
166     //  adiw    r31:r30, 16
167     // to:
168     //  movw    r31:r30, r29:r28
169     //  adiw    r31:r30, 45
170     foldFrameOffset(*std::next(II), Offset, DstReg);
171 
172     // Select the best opcode based on DstReg and the offset size.
173     switch (DstReg) {
174     case AVR::R25R24:
175     case AVR::R27R26:
176     case AVR::R31R30: {
177       if (isUInt<6>(Offset)) {
178         Opcode = AVR::ADIWRdK;
179         break;
180       }
181       LLVM_FALLTHROUGH;
182     }
183     default: {
184       // This opcode will get expanded into a pair of subi/sbci.
185       Opcode = AVR::SUBIWRdK;
186       Offset = -Offset;
187       break;
188     }
189     }
190 
191     MachineInstr *New = BuildMI(MBB, std::next(II), dl, TII.get(Opcode), DstReg)
192                             .addReg(DstReg, RegState::Kill)
193                             .addImm(Offset);
194     New->getOperand(3).setIsDead();
195 
196     return;
197   }
198 
199   // If the offset is too big we have to adjust and restore the frame pointer
200   // to materialize a valid load/store with displacement.
201   //:TODO: consider using only one adiw/sbiw chain for more than one frame index
202   if (Offset > 63) {
203     unsigned AddOpc = AVR::ADIWRdK, SubOpc = AVR::SBIWRdK;
204     int AddOffset = Offset - 63 + 1;
205 
206     // For huge offsets where adiw/sbiw cannot be used use a pair of subi/sbci.
207     if ((Offset - 63 + 1) > 63) {
208       AddOpc = AVR::SUBIWRdK;
209       SubOpc = AVR::SUBIWRdK;
210       AddOffset = -AddOffset;
211     }
212 
213     // It is possible that the spiller places this frame instruction in between
214     // a compare and branch, invalidating the contents of SREG set by the
215     // compare instruction because of the add/sub pairs. Conservatively save and
216     // restore SREG before and after each add/sub pair.
217     BuildMI(MBB, II, dl, TII.get(AVR::INRdA), AVR::R0).addImm(0x3f);
218 
219     MachineInstr *New = BuildMI(MBB, II, dl, TII.get(AddOpc), AVR::R29R28)
220                             .addReg(AVR::R29R28, RegState::Kill)
221                             .addImm(AddOffset);
222     New->getOperand(3).setIsDead();
223 
224     // Restore SREG.
225     BuildMI(MBB, std::next(II), dl, TII.get(AVR::OUTARr))
226         .addImm(0x3f)
227         .addReg(AVR::R0, RegState::Kill);
228 
229     // No need to set SREG as dead here otherwise if the next instruction is a
230     // cond branch it will be using a dead register.
231     New = BuildMI(MBB, std::next(II), dl, TII.get(SubOpc), AVR::R29R28)
232               .addReg(AVR::R29R28, RegState::Kill)
233               .addImm(Offset - 63 + 1);
234 
235     Offset = 62;
236   }
237 
238   MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
239   assert(isUInt<6>(Offset) && "Offset is out of range");
240   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
241 }
242 
243 unsigned AVRRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
244   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
245   if (TFI->hasFP(MF)) {
246     // The Y pointer register
247     return AVR::R28;
248   }
249 
250   return AVR::SP;
251 }
252 
253 const TargetRegisterClass *
254 AVRRegisterInfo::getPointerRegClass(const MachineFunction &MF,
255                                     unsigned Kind) const {
256   // FIXME: Currently we're using avr-gcc as reference, so we restrict
257   // ptrs to Y and Z regs. Though avr-gcc has buggy implementation
258   // of memory constraint, so we can fix it and bit avr-gcc here ;-)
259   return &AVR::PTRDISPREGSRegClass;
260 }
261 
262 void AVRRegisterInfo::splitReg(unsigned Reg,
263                                unsigned &LoReg,
264                                unsigned &HiReg) const {
265     assert(AVR::DREGSRegClass.contains(Reg) && "can only split 16-bit registers");
266 
267     LoReg = getSubReg(Reg, AVR::sub_lo);
268     HiReg = getSubReg(Reg, AVR::sub_hi);
269 }
270 
271 } // end of namespace llvm
272 
273