1 //===-- AVRExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a pass that expands pseudo instructions into target
10 // instructions. This pass should be run after register allocation but before
11 // the post-regalloc scheduling pass.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AVR.h"
16 #include "AVRInstrInfo.h"
17 #include "AVRTargetMachine.h"
18 #include "MCTargetDesc/AVRMCTargetDesc.h"
19 
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/CodeGen/TargetRegisterInfo.h"
25 
26 using namespace llvm;
27 
28 #define AVR_EXPAND_PSEUDO_NAME "AVR pseudo instruction expansion pass"
29 
30 namespace {
31 
32 /// Expands "placeholder" instructions marked as pseudo into
33 /// actual AVR instructions.
34 class AVRExpandPseudo : public MachineFunctionPass {
35 public:
36   static char ID;
37 
38   AVRExpandPseudo() : MachineFunctionPass(ID) {
39     initializeAVRExpandPseudoPass(*PassRegistry::getPassRegistry());
40   }
41 
42   bool runOnMachineFunction(MachineFunction &MF) override;
43 
44   StringRef getPassName() const override { return AVR_EXPAND_PSEUDO_NAME; }
45 
46 private:
47   typedef MachineBasicBlock Block;
48   typedef Block::iterator BlockIt;
49 
50   const AVRRegisterInfo *TRI;
51   const TargetInstrInfo *TII;
52 
53   /// The register to be used for temporary storage.
54   const Register SCRATCH_REGISTER = AVR::R0;
55   /// The register that will always contain zero.
56   const Register ZERO_REGISTER = AVR::R1;
57   /// The IO address of the status register.
58   const unsigned SREG_ADDR = 0x3f;
59 
60   bool expandMBB(Block &MBB);
61   bool expandMI(Block &MBB, BlockIt MBBI);
62   template <unsigned OP> bool expand(Block &MBB, BlockIt MBBI);
63 
64   MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode) {
65     return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode));
66   }
67 
68   MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode,
69                               Register DstReg) {
70     return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg);
71   }
72 
73   MachineRegisterInfo &getRegInfo(Block &MBB) { return MBB.getParent()->getRegInfo(); }
74 
75   bool expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI);
76   bool expandLogic(unsigned Op, Block &MBB, BlockIt MBBI);
77   bool expandLogicImm(unsigned Op, Block &MBB, BlockIt MBBI);
78   bool isLogicImmOpRedundant(unsigned Op, unsigned ImmVal) const;
79 
80   template<typename Func>
81   bool expandAtomic(Block &MBB, BlockIt MBBI, Func f);
82 
83   template<typename Func>
84   bool expandAtomicBinaryOp(unsigned Opcode, Block &MBB, BlockIt MBBI, Func f);
85 
86   bool expandAtomicBinaryOp(unsigned Opcode, Block &MBB, BlockIt MBBI);
87 
88   bool expandAtomicArithmeticOp(unsigned MemOpcode,
89                                 unsigned ArithOpcode,
90                                 Block &MBB,
91                                 BlockIt MBBI);
92 
93   /// Specific shift implementation.
94   bool expandLSLB7Rd(Block &MBB, BlockIt MBBI);
95   bool expandLSRB7Rd(Block &MBB, BlockIt MBBI);
96   bool expandASRB7Rd(Block &MBB, BlockIt MBBI);
97   bool expandLSLW4Rd(Block &MBB, BlockIt MBBI);
98   bool expandLSRW4Rd(Block &MBB, BlockIt MBBI);
99   bool expandLSLW8Rd(Block &MBB, BlockIt MBBI);
100   bool expandLSRW8Rd(Block &MBB, BlockIt MBBI);
101   bool expandASRW8Rd(Block &MBB, BlockIt MBBI);
102   bool expandLSLW12Rd(Block &MBB, BlockIt MBBI);
103   bool expandLSRW12Rd(Block &MBB, BlockIt MBBI);
104 
105   /// Scavenges a free GPR8 register for use.
106   Register scavengeGPR8(MachineInstr &MI);
107 };
108 
109 char AVRExpandPseudo::ID = 0;
110 
111 bool AVRExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
112   bool Modified = false;
113 
114   BlockIt MBBI = MBB.begin(), E = MBB.end();
115   while (MBBI != E) {
116     BlockIt NMBBI = std::next(MBBI);
117     Modified |= expandMI(MBB, MBBI);
118     MBBI = NMBBI;
119   }
120 
121   return Modified;
122 }
123 
124 bool AVRExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
125   bool Modified = false;
126 
127   const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
128   TRI = STI.getRegisterInfo();
129   TII = STI.getInstrInfo();
130 
131   // We need to track liveness in order to use register scavenging.
132   MF.getProperties().set(MachineFunctionProperties::Property::TracksLiveness);
133 
134   for (Block &MBB : MF) {
135     bool ContinueExpanding = true;
136     unsigned ExpandCount = 0;
137 
138     // Continue expanding the block until all pseudos are expanded.
139     do {
140       assert(ExpandCount < 10 && "pseudo expand limit reached");
141 
142       bool BlockModified = expandMBB(MBB);
143       Modified |= BlockModified;
144       ExpandCount++;
145 
146       ContinueExpanding = BlockModified;
147     } while (ContinueExpanding);
148   }
149 
150   return Modified;
151 }
152 
153 bool AVRExpandPseudo::
154 expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI) {
155   MachineInstr &MI = *MBBI;
156   Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
157   Register DstReg = MI.getOperand(0).getReg();
158   Register SrcReg = MI.getOperand(2).getReg();
159   bool DstIsDead = MI.getOperand(0).isDead();
160   bool DstIsKill = MI.getOperand(1).isKill();
161   bool SrcIsKill = MI.getOperand(2).isKill();
162   bool ImpIsDead = MI.getOperand(3).isDead();
163   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
164   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
165 
166   buildMI(MBB, MBBI, OpLo)
167     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
168     .addReg(DstLoReg, getKillRegState(DstIsKill))
169     .addReg(SrcLoReg, getKillRegState(SrcIsKill));
170 
171   auto MIBHI = buildMI(MBB, MBBI, OpHi)
172     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
173     .addReg(DstHiReg, getKillRegState(DstIsKill))
174     .addReg(SrcHiReg, getKillRegState(SrcIsKill));
175 
176   if (ImpIsDead)
177     MIBHI->getOperand(3).setIsDead();
178 
179   // SREG is always implicitly killed
180   MIBHI->getOperand(4).setIsKill();
181 
182   MI.eraseFromParent();
183   return true;
184 }
185 
186 bool AVRExpandPseudo::
187 expandLogic(unsigned Op, Block &MBB, BlockIt MBBI) {
188   MachineInstr &MI = *MBBI;
189   Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
190   Register DstReg = MI.getOperand(0).getReg();
191   Register SrcReg = MI.getOperand(2).getReg();
192   bool DstIsDead = MI.getOperand(0).isDead();
193   bool DstIsKill = MI.getOperand(1).isKill();
194   bool SrcIsKill = MI.getOperand(2).isKill();
195   bool ImpIsDead = MI.getOperand(3).isDead();
196   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
197   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
198 
199   auto MIBLO = buildMI(MBB, MBBI, Op)
200     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
201     .addReg(DstLoReg, getKillRegState(DstIsKill))
202     .addReg(SrcLoReg, getKillRegState(SrcIsKill));
203 
204   // SREG is always implicitly dead
205   MIBLO->getOperand(3).setIsDead();
206 
207   auto MIBHI = buildMI(MBB, MBBI, Op)
208     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
209     .addReg(DstHiReg, getKillRegState(DstIsKill))
210     .addReg(SrcHiReg, getKillRegState(SrcIsKill));
211 
212   if (ImpIsDead)
213     MIBHI->getOperand(3).setIsDead();
214 
215   MI.eraseFromParent();
216   return true;
217 }
218 
219 bool AVRExpandPseudo::
220   isLogicImmOpRedundant(unsigned Op, unsigned ImmVal) const {
221 
222   // ANDI Rd, 0xff is redundant.
223   if (Op == AVR::ANDIRdK && ImmVal == 0xff)
224     return true;
225 
226   // ORI Rd, 0x0 is redundant.
227   if (Op == AVR::ORIRdK && ImmVal == 0x0)
228     return true;
229 
230   return false;
231 }
232 
233 bool AVRExpandPseudo::
234 expandLogicImm(unsigned Op, Block &MBB, BlockIt MBBI) {
235   MachineInstr &MI = *MBBI;
236   Register DstLoReg, DstHiReg;
237   Register DstReg = MI.getOperand(0).getReg();
238   bool DstIsDead = MI.getOperand(0).isDead();
239   bool SrcIsKill = MI.getOperand(1).isKill();
240   bool ImpIsDead = MI.getOperand(3).isDead();
241   unsigned Imm = MI.getOperand(2).getImm();
242   unsigned Lo8 = Imm & 0xff;
243   unsigned Hi8 = (Imm >> 8) & 0xff;
244   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
245 
246   if (!isLogicImmOpRedundant(Op, Lo8)) {
247     auto MIBLO = buildMI(MBB, MBBI, Op)
248       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
249       .addReg(DstLoReg, getKillRegState(SrcIsKill))
250       .addImm(Lo8);
251 
252     // SREG is always implicitly dead
253     MIBLO->getOperand(3).setIsDead();
254   }
255 
256   if (!isLogicImmOpRedundant(Op, Hi8)) {
257     auto MIBHI = buildMI(MBB, MBBI, Op)
258       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
259       .addReg(DstHiReg, getKillRegState(SrcIsKill))
260       .addImm(Hi8);
261 
262     if (ImpIsDead)
263       MIBHI->getOperand(3).setIsDead();
264   }
265 
266   MI.eraseFromParent();
267   return true;
268 }
269 
270 template <>
271 bool AVRExpandPseudo::expand<AVR::ADDWRdRr>(Block &MBB, BlockIt MBBI) {
272   return expandArith(AVR::ADDRdRr, AVR::ADCRdRr, MBB, MBBI);
273 }
274 
275 template <>
276 bool AVRExpandPseudo::expand<AVR::ADCWRdRr>(Block &MBB, BlockIt MBBI) {
277   return expandArith(AVR::ADCRdRr, AVR::ADCRdRr, MBB, MBBI);
278 }
279 
280 template <>
281 bool AVRExpandPseudo::expand<AVR::SUBWRdRr>(Block &MBB, BlockIt MBBI) {
282   return expandArith(AVR::SUBRdRr, AVR::SBCRdRr, MBB, MBBI);
283 }
284 
285 template <>
286 bool AVRExpandPseudo::expand<AVR::SUBIWRdK>(Block &MBB, BlockIt MBBI) {
287   MachineInstr &MI = *MBBI;
288   Register DstLoReg, DstHiReg;
289   Register DstReg = MI.getOperand(0).getReg();
290   bool DstIsDead = MI.getOperand(0).isDead();
291   bool SrcIsKill = MI.getOperand(1).isKill();
292   bool ImpIsDead = MI.getOperand(3).isDead();
293   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
294 
295   auto MIBLO = buildMI(MBB, MBBI, AVR::SUBIRdK)
296     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
297     .addReg(DstLoReg, getKillRegState(SrcIsKill));
298 
299   auto MIBHI = buildMI(MBB, MBBI, AVR::SBCIRdK)
300     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
301     .addReg(DstHiReg, getKillRegState(SrcIsKill));
302 
303   switch (MI.getOperand(2).getType()) {
304   case MachineOperand::MO_GlobalAddress: {
305     const GlobalValue *GV = MI.getOperand(2).getGlobal();
306     int64_t Offs = MI.getOperand(2).getOffset();
307     unsigned TF = MI.getOperand(2).getTargetFlags();
308     MIBLO.addGlobalAddress(GV, Offs, TF | AVRII::MO_NEG | AVRII::MO_LO);
309     MIBHI.addGlobalAddress(GV, Offs, TF | AVRII::MO_NEG | AVRII::MO_HI);
310     break;
311   }
312   case MachineOperand::MO_Immediate: {
313     unsigned Imm = MI.getOperand(2).getImm();
314     MIBLO.addImm(Imm & 0xff);
315     MIBHI.addImm((Imm >> 8) & 0xff);
316     break;
317   }
318   default:
319     llvm_unreachable("Unknown operand type!");
320   }
321 
322   if (ImpIsDead)
323     MIBHI->getOperand(3).setIsDead();
324 
325   // SREG is always implicitly killed
326   MIBHI->getOperand(4).setIsKill();
327 
328   MI.eraseFromParent();
329   return true;
330 }
331 
332 template <>
333 bool AVRExpandPseudo::expand<AVR::SBCWRdRr>(Block &MBB, BlockIt MBBI) {
334   return expandArith(AVR::SBCRdRr, AVR::SBCRdRr, MBB, MBBI);
335 }
336 
337 template <>
338 bool AVRExpandPseudo::expand<AVR::SBCIWRdK>(Block &MBB, BlockIt MBBI) {
339   MachineInstr &MI = *MBBI;
340   Register DstLoReg, DstHiReg;
341   Register DstReg = MI.getOperand(0).getReg();
342   bool DstIsDead = MI.getOperand(0).isDead();
343   bool SrcIsKill = MI.getOperand(1).isKill();
344   bool ImpIsDead = MI.getOperand(3).isDead();
345   unsigned Imm = MI.getOperand(2).getImm();
346   unsigned Lo8 = Imm & 0xff;
347   unsigned Hi8 = (Imm >> 8) & 0xff;
348   unsigned OpLo = AVR::SBCIRdK;
349   unsigned OpHi = AVR::SBCIRdK;
350   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
351 
352   auto MIBLO = buildMI(MBB, MBBI, OpLo)
353     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
354     .addReg(DstLoReg, getKillRegState(SrcIsKill))
355     .addImm(Lo8);
356 
357   // SREG is always implicitly killed
358   MIBLO->getOperand(4).setIsKill();
359 
360   auto MIBHI = buildMI(MBB, MBBI, OpHi)
361     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
362     .addReg(DstHiReg, getKillRegState(SrcIsKill))
363     .addImm(Hi8);
364 
365   if (ImpIsDead)
366     MIBHI->getOperand(3).setIsDead();
367 
368   // SREG is always implicitly killed
369   MIBHI->getOperand(4).setIsKill();
370 
371   MI.eraseFromParent();
372   return true;
373 }
374 
375 template <>
376 bool AVRExpandPseudo::expand<AVR::ANDWRdRr>(Block &MBB, BlockIt MBBI) {
377   return expandLogic(AVR::ANDRdRr, MBB, MBBI);
378 }
379 
380 template <>
381 bool AVRExpandPseudo::expand<AVR::ANDIWRdK>(Block &MBB, BlockIt MBBI) {
382   return expandLogicImm(AVR::ANDIRdK, MBB, MBBI);
383 }
384 
385 template <>
386 bool AVRExpandPseudo::expand<AVR::ORWRdRr>(Block &MBB, BlockIt MBBI) {
387   return expandLogic(AVR::ORRdRr, MBB, MBBI);
388 }
389 
390 template <>
391 bool AVRExpandPseudo::expand<AVR::ORIWRdK>(Block &MBB, BlockIt MBBI) {
392   return expandLogicImm(AVR::ORIRdK, MBB, MBBI);
393 }
394 
395 template <>
396 bool AVRExpandPseudo::expand<AVR::EORWRdRr>(Block &MBB, BlockIt MBBI) {
397   return expandLogic(AVR::EORRdRr, MBB, MBBI);
398 }
399 
400 template <>
401 bool AVRExpandPseudo::expand<AVR::COMWRd>(Block &MBB, BlockIt MBBI) {
402   MachineInstr &MI = *MBBI;
403   Register DstLoReg, DstHiReg;
404   Register DstReg = MI.getOperand(0).getReg();
405   bool DstIsDead = MI.getOperand(0).isDead();
406   bool DstIsKill = MI.getOperand(1).isKill();
407   bool ImpIsDead = MI.getOperand(2).isDead();
408   unsigned OpLo = AVR::COMRd;
409   unsigned OpHi = AVR::COMRd;
410   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
411 
412   auto MIBLO = buildMI(MBB, MBBI, OpLo)
413     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
414     .addReg(DstLoReg, getKillRegState(DstIsKill));
415 
416   // SREG is always implicitly dead
417   MIBLO->getOperand(2).setIsDead();
418 
419   auto MIBHI = buildMI(MBB, MBBI, OpHi)
420     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
421     .addReg(DstHiReg, getKillRegState(DstIsKill));
422 
423   if (ImpIsDead)
424     MIBHI->getOperand(2).setIsDead();
425 
426   MI.eraseFromParent();
427   return true;
428 }
429 
430 template <>
431 bool AVRExpandPseudo::expand<AVR::NEGWRd>(Block &MBB, BlockIt MBBI) {
432   MachineInstr &MI = *MBBI;
433   Register DstLoReg, DstHiReg;
434   Register DstReg = MI.getOperand(0).getReg();
435   bool DstIsDead = MI.getOperand(0).isDead();
436   bool DstIsKill = MI.getOperand(1).isKill();
437   bool ImpIsDead = MI.getOperand(2).isDead();
438   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
439 
440   // Do NEG on the upper byte.
441   auto MIBHI =
442       buildMI(MBB, MBBI, AVR::NEGRd)
443           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
444           .addReg(DstHiReg, getKillRegState(DstIsKill));
445   // SREG is always implicitly dead
446   MIBHI->getOperand(2).setIsDead();
447 
448   // Do NEG on the lower byte.
449   buildMI(MBB, MBBI, AVR::NEGRd)
450       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
451       .addReg(DstLoReg, getKillRegState(DstIsKill));
452 
453   // Do an extra SBC.
454   auto MISBCI =
455       buildMI(MBB, MBBI, AVR::SBCRdRr)
456           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
457           .addReg(DstHiReg, getKillRegState(DstIsKill))
458           .addReg(ZERO_REGISTER);
459   if (ImpIsDead)
460     MISBCI->getOperand(3).setIsDead();
461   // SREG is always implicitly killed
462   MISBCI->getOperand(4).setIsKill();
463 
464   MI.eraseFromParent();
465   return true;
466 }
467 
468 template <>
469 bool AVRExpandPseudo::expand<AVR::CPWRdRr>(Block &MBB, BlockIt MBBI) {
470   MachineInstr &MI = *MBBI;
471   Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
472   Register DstReg = MI.getOperand(0).getReg();
473   Register SrcReg = MI.getOperand(1).getReg();
474   bool DstIsKill = MI.getOperand(0).isKill();
475   bool SrcIsKill = MI.getOperand(1).isKill();
476   bool ImpIsDead = MI.getOperand(2).isDead();
477   unsigned OpLo = AVR::CPRdRr;
478   unsigned OpHi = AVR::CPCRdRr;
479   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
480   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
481 
482   // Low part
483   buildMI(MBB, MBBI, OpLo)
484     .addReg(DstLoReg, getKillRegState(DstIsKill))
485     .addReg(SrcLoReg, getKillRegState(SrcIsKill));
486 
487   auto MIBHI = buildMI(MBB, MBBI, OpHi)
488     .addReg(DstHiReg, getKillRegState(DstIsKill))
489     .addReg(SrcHiReg, getKillRegState(SrcIsKill));
490 
491   if (ImpIsDead)
492     MIBHI->getOperand(2).setIsDead();
493 
494   // SREG is always implicitly killed
495   MIBHI->getOperand(3).setIsKill();
496 
497   MI.eraseFromParent();
498   return true;
499 }
500 
501 template <>
502 bool AVRExpandPseudo::expand<AVR::CPCWRdRr>(Block &MBB, BlockIt MBBI) {
503   MachineInstr &MI = *MBBI;
504   Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
505   Register DstReg = MI.getOperand(0).getReg();
506   Register SrcReg = MI.getOperand(1).getReg();
507   bool DstIsKill = MI.getOperand(0).isKill();
508   bool SrcIsKill = MI.getOperand(1).isKill();
509   bool ImpIsDead = MI.getOperand(2).isDead();
510   unsigned OpLo = AVR::CPCRdRr;
511   unsigned OpHi = AVR::CPCRdRr;
512   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
513   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
514 
515   auto MIBLO = buildMI(MBB, MBBI, OpLo)
516     .addReg(DstLoReg, getKillRegState(DstIsKill))
517     .addReg(SrcLoReg, getKillRegState(SrcIsKill));
518 
519   // SREG is always implicitly killed
520   MIBLO->getOperand(3).setIsKill();
521 
522   auto MIBHI = buildMI(MBB, MBBI, OpHi)
523     .addReg(DstHiReg, getKillRegState(DstIsKill))
524     .addReg(SrcHiReg, getKillRegState(SrcIsKill));
525 
526   if (ImpIsDead)
527     MIBHI->getOperand(2).setIsDead();
528 
529   // SREG is always implicitly killed
530   MIBHI->getOperand(3).setIsKill();
531 
532   MI.eraseFromParent();
533   return true;
534 }
535 
536 template <>
537 bool AVRExpandPseudo::expand<AVR::LDIWRdK>(Block &MBB, BlockIt MBBI) {
538   MachineInstr &MI = *MBBI;
539   Register DstLoReg, DstHiReg;
540   Register DstReg = MI.getOperand(0).getReg();
541   bool DstIsDead = MI.getOperand(0).isDead();
542   unsigned OpLo = AVR::LDIRdK;
543   unsigned OpHi = AVR::LDIRdK;
544   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
545 
546   auto MIBLO = buildMI(MBB, MBBI, OpLo)
547     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
548 
549   auto MIBHI = buildMI(MBB, MBBI, OpHi)
550     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
551 
552   switch (MI.getOperand(1).getType()) {
553   case MachineOperand::MO_GlobalAddress: {
554     const GlobalValue *GV = MI.getOperand(1).getGlobal();
555     int64_t Offs = MI.getOperand(1).getOffset();
556     unsigned TF = MI.getOperand(1).getTargetFlags();
557 
558     MIBLO.addGlobalAddress(GV, Offs, TF | AVRII::MO_LO);
559     MIBHI.addGlobalAddress(GV, Offs, TF | AVRII::MO_HI);
560     break;
561   }
562   case MachineOperand::MO_BlockAddress: {
563     const BlockAddress *BA = MI.getOperand(1).getBlockAddress();
564     unsigned TF = MI.getOperand(1).getTargetFlags();
565 
566     MIBLO.add(MachineOperand::CreateBA(BA, TF | AVRII::MO_LO));
567     MIBHI.add(MachineOperand::CreateBA(BA, TF | AVRII::MO_HI));
568     break;
569   }
570   case MachineOperand::MO_Immediate: {
571     unsigned Imm = MI.getOperand(1).getImm();
572 
573     MIBLO.addImm(Imm & 0xff);
574     MIBHI.addImm((Imm >> 8) & 0xff);
575     break;
576   }
577   default:
578     llvm_unreachable("Unknown operand type!");
579   }
580 
581   MI.eraseFromParent();
582   return true;
583 }
584 
585 template <>
586 bool AVRExpandPseudo::expand<AVR::LDSWRdK>(Block &MBB, BlockIt MBBI) {
587   MachineInstr &MI = *MBBI;
588   Register DstLoReg, DstHiReg;
589   Register DstReg = MI.getOperand(0).getReg();
590   bool DstIsDead = MI.getOperand(0).isDead();
591   unsigned OpLo = AVR::LDSRdK;
592   unsigned OpHi = AVR::LDSRdK;
593   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
594 
595   auto MIBLO = buildMI(MBB, MBBI, OpLo)
596     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
597 
598   auto MIBHI = buildMI(MBB, MBBI, OpHi)
599     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
600 
601   switch (MI.getOperand(1).getType()) {
602   case MachineOperand::MO_GlobalAddress: {
603     const GlobalValue *GV = MI.getOperand(1).getGlobal();
604     int64_t Offs = MI.getOperand(1).getOffset();
605     unsigned TF = MI.getOperand(1).getTargetFlags();
606 
607     MIBLO.addGlobalAddress(GV, Offs, TF);
608     MIBHI.addGlobalAddress(GV, Offs + 1, TF);
609     break;
610   }
611   case MachineOperand::MO_Immediate: {
612     unsigned Imm = MI.getOperand(1).getImm();
613 
614     MIBLO.addImm(Imm);
615     MIBHI.addImm(Imm + 1);
616     break;
617   }
618   default:
619     llvm_unreachable("Unknown operand type!");
620   }
621 
622   MIBLO.setMemRefs(MI.memoperands());
623   MIBHI.setMemRefs(MI.memoperands());
624 
625   MI.eraseFromParent();
626   return true;
627 }
628 
629 template <>
630 bool AVRExpandPseudo::expand<AVR::LDWRdPtr>(Block &MBB, BlockIt MBBI) {
631   MachineInstr &MI = *MBBI;
632   Register DstLoReg, DstHiReg;
633   Register DstReg = MI.getOperand(0).getReg();
634   Register TmpReg = 0; // 0 for no temporary register
635   Register SrcReg = MI.getOperand(1).getReg();
636   bool SrcIsKill = MI.getOperand(1).isKill();
637   unsigned OpLo = AVR::LDRdPtr;
638   unsigned OpHi = AVR::LDDRdPtrQ;
639   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
640 
641   // Use a temporary register if src and dst registers are the same.
642   if (DstReg == SrcReg)
643     TmpReg = scavengeGPR8(MI);
644 
645   Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;
646   Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;
647 
648   // Load low byte.
649   auto MIBLO = buildMI(MBB, MBBI, OpLo)
650                    .addReg(CurDstLoReg, RegState::Define)
651                    .addReg(SrcReg);
652 
653   // Push low byte onto stack if necessary.
654   if (TmpReg)
655     buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
656 
657   // Load high byte.
658   auto MIBHI = buildMI(MBB, MBBI, OpHi)
659     .addReg(CurDstHiReg, RegState::Define)
660     .addReg(SrcReg, getKillRegState(SrcIsKill))
661     .addImm(1);
662 
663   if (TmpReg) {
664     // Move the high byte into the final destination.
665     buildMI(MBB, MBBI, AVR::MOVRdRr, DstHiReg).addReg(TmpReg);
666 
667     // Move the low byte from the scratch space into the final destination.
668     buildMI(MBB, MBBI, AVR::POPRd, DstLoReg);
669   }
670 
671   MIBLO.setMemRefs(MI.memoperands());
672   MIBHI.setMemRefs(MI.memoperands());
673 
674   MI.eraseFromParent();
675   return true;
676 }
677 
678 template <>
679 bool AVRExpandPseudo::expand<AVR::LDWRdPtrPi>(Block &MBB, BlockIt MBBI) {
680   MachineInstr &MI = *MBBI;
681   Register DstLoReg, DstHiReg;
682   Register DstReg = MI.getOperand(0).getReg();
683   Register SrcReg = MI.getOperand(1).getReg();
684   bool DstIsDead = MI.getOperand(0).isDead();
685   bool SrcIsDead = MI.getOperand(1).isKill();
686   unsigned OpLo = AVR::LDRdPtrPi;
687   unsigned OpHi = AVR::LDRdPtrPi;
688   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
689 
690   assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
691 
692   auto MIBLO = buildMI(MBB, MBBI, OpLo)
693     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
694     .addReg(SrcReg, RegState::Define)
695     .addReg(SrcReg, RegState::Kill);
696 
697   auto MIBHI = buildMI(MBB, MBBI, OpHi)
698     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
699     .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
700     .addReg(SrcReg, RegState::Kill);
701 
702   MIBLO.setMemRefs(MI.memoperands());
703   MIBHI.setMemRefs(MI.memoperands());
704 
705   MI.eraseFromParent();
706   return true;
707 }
708 
709 template <>
710 bool AVRExpandPseudo::expand<AVR::LDWRdPtrPd>(Block &MBB, BlockIt MBBI) {
711   MachineInstr &MI = *MBBI;
712   Register DstLoReg, DstHiReg;
713   Register DstReg = MI.getOperand(0).getReg();
714   Register SrcReg = MI.getOperand(1).getReg();
715   bool DstIsDead = MI.getOperand(0).isDead();
716   bool SrcIsDead = MI.getOperand(1).isKill();
717   unsigned OpLo = AVR::LDRdPtrPd;
718   unsigned OpHi = AVR::LDRdPtrPd;
719   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
720 
721   assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
722 
723   auto MIBHI = buildMI(MBB, MBBI, OpHi)
724     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
725     .addReg(SrcReg, RegState::Define)
726     .addReg(SrcReg, RegState::Kill);
727 
728   auto MIBLO = buildMI(MBB, MBBI, OpLo)
729     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
730     .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
731     .addReg(SrcReg, RegState::Kill);
732 
733   MIBLO.setMemRefs(MI.memoperands());
734   MIBHI.setMemRefs(MI.memoperands());
735 
736   MI.eraseFromParent();
737   return true;
738 }
739 
740 template <>
741 bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) {
742   MachineInstr &MI = *MBBI;
743   Register DstLoReg, DstHiReg;
744   Register DstReg = MI.getOperand(0).getReg();
745   Register TmpReg = 0; // 0 for no temporary register
746   Register SrcReg = MI.getOperand(1).getReg();
747   unsigned Imm = MI.getOperand(2).getImm();
748   bool SrcIsKill = MI.getOperand(1).isKill();
749   unsigned OpLo = AVR::LDDRdPtrQ;
750   unsigned OpHi = AVR::LDDRdPtrQ;
751   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
752 
753   // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
754   // allowed for the instruction, 62 is the limit here.
755   assert(Imm <= 62 && "Offset is out of range");
756 
757   // Use a temporary register if src and dst registers are the same.
758   if (DstReg == SrcReg)
759     TmpReg = scavengeGPR8(MI);
760 
761   Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;
762   Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;
763 
764   // Load low byte.
765   auto MIBLO = buildMI(MBB, MBBI, OpLo)
766     .addReg(CurDstLoReg, RegState::Define)
767     .addReg(SrcReg)
768     .addImm(Imm);
769 
770   // Push low byte onto stack if necessary.
771   if (TmpReg)
772     buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
773 
774   // Load high byte.
775   auto MIBHI = buildMI(MBB, MBBI, OpHi)
776     .addReg(CurDstHiReg, RegState::Define)
777     .addReg(SrcReg, getKillRegState(SrcIsKill))
778     .addImm(Imm + 1);
779 
780   if (TmpReg) {
781     // Move the high byte into the final destination.
782     buildMI(MBB, MBBI, AVR::MOVRdRr, DstHiReg).addReg(TmpReg);
783 
784     // Move the low byte from the scratch space into the final destination.
785     buildMI(MBB, MBBI, AVR::POPRd, DstLoReg);
786   }
787 
788   MIBLO.setMemRefs(MI.memoperands());
789   MIBHI.setMemRefs(MI.memoperands());
790 
791   MI.eraseFromParent();
792   return true;
793 }
794 
795 template <>
796 bool AVRExpandPseudo::expand<AVR::LPMWRdZ>(Block &MBB, BlockIt MBBI) {
797   MachineInstr &MI = *MBBI;
798   Register DstLoReg, DstHiReg;
799   Register DstReg = MI.getOperand(0).getReg();
800   Register TmpReg = 0; // 0 for no temporary register
801   Register SrcReg = MI.getOperand(1).getReg();
802   bool SrcIsKill = MI.getOperand(1).isKill();
803   unsigned OpLo = AVR::LPMRdZPi;
804   unsigned OpHi = AVR::LPMRdZ;
805   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
806 
807   // Use a temporary register if src and dst registers are the same.
808   if (DstReg == SrcReg)
809     TmpReg = scavengeGPR8(MI);
810 
811   Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;
812   Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;
813 
814   // Load low byte.
815   auto MIBLO = buildMI(MBB, MBBI, OpLo)
816       .addReg(CurDstLoReg, RegState::Define)
817       .addReg(SrcReg);
818 
819   // Push low byte onto stack if necessary.
820   if (TmpReg)
821     buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
822 
823   // Load high byte.
824   auto MIBHI = buildMI(MBB, MBBI, OpHi)
825       .addReg(CurDstHiReg, RegState::Define)
826       .addReg(SrcReg, getKillRegState(SrcIsKill));
827 
828   if (TmpReg) {
829     // Move the high byte into the final destination.
830     buildMI(MBB, MBBI, AVR::MOVRdRr, DstHiReg).addReg(TmpReg);
831 
832     // Move the low byte from the scratch space into the final destination.
833     buildMI(MBB, MBBI, AVR::POPRd, DstLoReg);
834   }
835 
836   MIBLO.setMemRefs(MI.memoperands());
837   MIBHI.setMemRefs(MI.memoperands());
838 
839   MI.eraseFromParent();
840   return true;
841 }
842 
843 template <>
844 bool AVRExpandPseudo::expand<AVR::LPMWRdZPi>(Block &MBB, BlockIt MBBI) {
845   llvm_unreachable("wide LPMPi is unimplemented");
846 }
847 
848 template<typename Func>
849 bool AVRExpandPseudo::expandAtomic(Block &MBB, BlockIt MBBI, Func f) {
850   // Remove the pseudo instruction.
851   MachineInstr &MI = *MBBI;
852 
853   // Store the SREG.
854   buildMI(MBB, MBBI, AVR::INRdA)
855     .addReg(SCRATCH_REGISTER, RegState::Define)
856     .addImm(SREG_ADDR);
857 
858   // Disable exceptions.
859   buildMI(MBB, MBBI, AVR::BCLRs).addImm(7); // CLI
860 
861   f(MI);
862 
863   // Restore the status reg.
864   buildMI(MBB, MBBI, AVR::OUTARr)
865     .addImm(SREG_ADDR)
866     .addReg(SCRATCH_REGISTER);
867 
868   MI.eraseFromParent();
869   return true;
870 }
871 
872 template<typename Func>
873 bool AVRExpandPseudo::expandAtomicBinaryOp(unsigned Opcode,
874                                            Block &MBB,
875                                            BlockIt MBBI,
876                                            Func f) {
877   return expandAtomic(MBB, MBBI, [&](MachineInstr &MI) {
878       auto Op1 = MI.getOperand(0);
879       auto Op2 = MI.getOperand(1);
880 
881       MachineInstr &NewInst =
882           *buildMI(MBB, MBBI, Opcode).add(Op1).add(Op2).getInstr();
883       f(NewInst);
884   });
885 }
886 
887 bool AVRExpandPseudo::expandAtomicBinaryOp(unsigned Opcode,
888                                            Block &MBB,
889                                            BlockIt MBBI) {
890   return expandAtomicBinaryOp(Opcode, MBB, MBBI, [](MachineInstr &MI) {});
891 }
892 
893 bool AVRExpandPseudo::expandAtomicArithmeticOp(unsigned Width,
894                                                unsigned ArithOpcode,
895                                                Block &MBB,
896                                                BlockIt MBBI) {
897   return expandAtomic(MBB, MBBI, [&](MachineInstr &MI) {
898       auto Op1 = MI.getOperand(0);
899       auto Op2 = MI.getOperand(1);
900 
901       unsigned LoadOpcode = (Width == 8) ? AVR::LDRdPtr : AVR::LDWRdPtr;
902       unsigned StoreOpcode = (Width == 8) ? AVR::STPtrRr : AVR::STWPtrRr;
903 
904       // Create the load
905       buildMI(MBB, MBBI, LoadOpcode).add(Op1).add(Op2);
906 
907       // Create the arithmetic op
908       buildMI(MBB, MBBI, ArithOpcode).add(Op1).add(Op1).add(Op2);
909 
910       // Create the store
911       buildMI(MBB, MBBI, StoreOpcode).add(Op2).add(Op1);
912   });
913 }
914 
915 Register AVRExpandPseudo::scavengeGPR8(MachineInstr &MI) {
916   MachineBasicBlock &MBB = *MI.getParent();
917   RegScavenger RS;
918 
919   RS.enterBasicBlock(MBB);
920   RS.forward(MI);
921 
922   BitVector Candidates =
923       TRI->getAllocatableSet
924       (*MBB.getParent(), &AVR::GPR8RegClass);
925 
926   // Exclude all the registers being used by the instruction.
927   for (MachineOperand &MO : MI.operands()) {
928     if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
929         !Register::isVirtualRegister(MO.getReg()))
930       Candidates.reset(MO.getReg());
931   }
932 
933   BitVector Available = RS.getRegsAvailable(&AVR::GPR8RegClass);
934   Available &= Candidates;
935 
936   signed Reg = Available.find_first();
937   assert(Reg != -1 && "ran out of registers");
938   return Reg;
939 }
940 
941 template<>
942 bool AVRExpandPseudo::expand<AVR::AtomicLoad8>(Block &MBB, BlockIt MBBI) {
943   return expandAtomicBinaryOp(AVR::LDRdPtr, MBB, MBBI);
944 }
945 
946 template<>
947 bool AVRExpandPseudo::expand<AVR::AtomicLoad16>(Block &MBB, BlockIt MBBI) {
948   return expandAtomicBinaryOp(AVR::LDWRdPtr, MBB, MBBI);
949 }
950 
951 template<>
952 bool AVRExpandPseudo::expand<AVR::AtomicStore8>(Block &MBB, BlockIt MBBI) {
953   return expandAtomicBinaryOp(AVR::STPtrRr, MBB, MBBI);
954 }
955 
956 template<>
957 bool AVRExpandPseudo::expand<AVR::AtomicStore16>(Block &MBB, BlockIt MBBI) {
958   return expandAtomicBinaryOp(AVR::STWPtrRr, MBB, MBBI);
959 }
960 
961 template<>
962 bool AVRExpandPseudo::expand<AVR::AtomicLoadAdd8>(Block &MBB, BlockIt MBBI) {
963   return expandAtomicArithmeticOp(8, AVR::ADDRdRr, MBB, MBBI);
964 }
965 
966 template<>
967 bool AVRExpandPseudo::expand<AVR::AtomicLoadAdd16>(Block &MBB, BlockIt MBBI) {
968   return expandAtomicArithmeticOp(16, AVR::ADDWRdRr, MBB, MBBI);
969 }
970 
971 template<>
972 bool AVRExpandPseudo::expand<AVR::AtomicLoadSub8>(Block &MBB, BlockIt MBBI) {
973   return expandAtomicArithmeticOp(8, AVR::SUBRdRr, MBB, MBBI);
974 }
975 
976 template<>
977 bool AVRExpandPseudo::expand<AVR::AtomicLoadSub16>(Block &MBB, BlockIt MBBI) {
978   return expandAtomicArithmeticOp(16, AVR::SUBWRdRr, MBB, MBBI);
979 }
980 
981 template<>
982 bool AVRExpandPseudo::expand<AVR::AtomicLoadAnd8>(Block &MBB, BlockIt MBBI) {
983   return expandAtomicArithmeticOp(8, AVR::ANDRdRr, MBB, MBBI);
984 }
985 
986 template<>
987 bool AVRExpandPseudo::expand<AVR::AtomicLoadAnd16>(Block &MBB, BlockIt MBBI) {
988   return expandAtomicArithmeticOp(16, AVR::ANDWRdRr, MBB, MBBI);
989 }
990 
991 template<>
992 bool AVRExpandPseudo::expand<AVR::AtomicLoadOr8>(Block &MBB, BlockIt MBBI) {
993   return expandAtomicArithmeticOp(8, AVR::ORRdRr, MBB, MBBI);
994 }
995 
996 template<>
997 bool AVRExpandPseudo::expand<AVR::AtomicLoadOr16>(Block &MBB, BlockIt MBBI) {
998   return expandAtomicArithmeticOp(16, AVR::ORWRdRr, MBB, MBBI);
999 }
1000 
1001 template<>
1002 bool AVRExpandPseudo::expand<AVR::AtomicLoadXor8>(Block &MBB, BlockIt MBBI) {
1003   return expandAtomicArithmeticOp(8, AVR::EORRdRr, MBB, MBBI);
1004 }
1005 
1006 template<>
1007 bool AVRExpandPseudo::expand<AVR::AtomicLoadXor16>(Block &MBB, BlockIt MBBI) {
1008   return expandAtomicArithmeticOp(16, AVR::EORWRdRr, MBB, MBBI);
1009 }
1010 
1011 template<>
1012 bool AVRExpandPseudo::expand<AVR::AtomicFence>(Block &MBB, BlockIt MBBI) {
1013   // On AVR, there is only one core and so atomic fences do nothing.
1014   MBBI->eraseFromParent();
1015   return true;
1016 }
1017 
1018 template <>
1019 bool AVRExpandPseudo::expand<AVR::STSWKRr>(Block &MBB, BlockIt MBBI) {
1020   MachineInstr &MI = *MBBI;
1021   Register SrcLoReg, SrcHiReg;
1022   Register SrcReg = MI.getOperand(1).getReg();
1023   bool SrcIsKill = MI.getOperand(1).isKill();
1024   unsigned OpLo = AVR::STSKRr;
1025   unsigned OpHi = AVR::STSKRr;
1026   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1027 
1028   // Write the high byte first in case this address belongs to a special
1029   // I/O address with a special temporary register.
1030   auto MIBHI = buildMI(MBB, MBBI, OpHi);
1031   auto MIBLO = buildMI(MBB, MBBI, OpLo);
1032 
1033   switch (MI.getOperand(0).getType()) {
1034   case MachineOperand::MO_GlobalAddress: {
1035     const GlobalValue *GV = MI.getOperand(0).getGlobal();
1036     int64_t Offs = MI.getOperand(0).getOffset();
1037     unsigned TF = MI.getOperand(0).getTargetFlags();
1038 
1039     MIBLO.addGlobalAddress(GV, Offs, TF);
1040     MIBHI.addGlobalAddress(GV, Offs + 1, TF);
1041     break;
1042   }
1043   case MachineOperand::MO_Immediate: {
1044     unsigned Imm = MI.getOperand(0).getImm();
1045 
1046     MIBLO.addImm(Imm);
1047     MIBHI.addImm(Imm + 1);
1048     break;
1049   }
1050   default:
1051     llvm_unreachable("Unknown operand type!");
1052   }
1053 
1054   MIBLO.addReg(SrcLoReg, getKillRegState(SrcIsKill));
1055   MIBHI.addReg(SrcHiReg, getKillRegState(SrcIsKill));
1056 
1057   MIBLO.setMemRefs(MI.memoperands());
1058   MIBHI.setMemRefs(MI.memoperands());
1059 
1060   MI.eraseFromParent();
1061   return true;
1062 }
1063 
1064 template <>
1065 bool AVRExpandPseudo::expand<AVR::STWPtrRr>(Block &MBB, BlockIt MBBI) {
1066   MachineInstr &MI = *MBBI;
1067   Register SrcLoReg, SrcHiReg;
1068   Register DstReg = MI.getOperand(0).getReg();
1069   Register SrcReg = MI.getOperand(1).getReg();
1070   bool DstIsUndef = MI.getOperand(0).isUndef();
1071   bool SrcIsKill = MI.getOperand(1).isKill();
1072   unsigned OpLo = AVR::STPtrRr;
1073   unsigned OpHi = AVR::STDPtrQRr;
1074   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1075 
1076   //:TODO: need to reverse this order like inw and stsw?
1077   auto MIBLO = buildMI(MBB, MBBI, OpLo)
1078     .addReg(DstReg, getUndefRegState(DstIsUndef))
1079     .addReg(SrcLoReg, getKillRegState(SrcIsKill));
1080 
1081   auto MIBHI = buildMI(MBB, MBBI, OpHi)
1082     .addReg(DstReg, getUndefRegState(DstIsUndef))
1083     .addImm(1)
1084     .addReg(SrcHiReg, getKillRegState(SrcIsKill));
1085 
1086   MIBLO.setMemRefs(MI.memoperands());
1087   MIBHI.setMemRefs(MI.memoperands());
1088 
1089   MI.eraseFromParent();
1090   return true;
1091 }
1092 
1093 template <>
1094 bool AVRExpandPseudo::expand<AVR::STWPtrPiRr>(Block &MBB, BlockIt MBBI) {
1095   MachineInstr &MI = *MBBI;
1096   Register SrcLoReg, SrcHiReg;
1097   Register DstReg = MI.getOperand(0).getReg();
1098   Register SrcReg = MI.getOperand(2).getReg();
1099   unsigned Imm = MI.getOperand(3).getImm();
1100   bool DstIsDead = MI.getOperand(0).isDead();
1101   bool SrcIsKill = MI.getOperand(2).isKill();
1102   unsigned OpLo = AVR::STPtrPiRr;
1103   unsigned OpHi = AVR::STPtrPiRr;
1104   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1105 
1106   assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
1107 
1108   auto MIBLO = buildMI(MBB, MBBI, OpLo)
1109     .addReg(DstReg, RegState::Define)
1110     .addReg(DstReg, RegState::Kill)
1111     .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1112     .addImm(Imm);
1113 
1114   auto MIBHI = buildMI(MBB, MBBI, OpHi)
1115     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1116     .addReg(DstReg, RegState::Kill)
1117     .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1118     .addImm(Imm);
1119 
1120   MIBLO.setMemRefs(MI.memoperands());
1121   MIBHI.setMemRefs(MI.memoperands());
1122 
1123   MI.eraseFromParent();
1124   return true;
1125 }
1126 
1127 template <>
1128 bool AVRExpandPseudo::expand<AVR::STWPtrPdRr>(Block &MBB, BlockIt MBBI) {
1129   MachineInstr &MI = *MBBI;
1130   Register SrcLoReg, SrcHiReg;
1131   Register DstReg = MI.getOperand(0).getReg();
1132   Register SrcReg = MI.getOperand(2).getReg();
1133   unsigned Imm = MI.getOperand(3).getImm();
1134   bool DstIsDead = MI.getOperand(0).isDead();
1135   bool SrcIsKill = MI.getOperand(2).isKill();
1136   unsigned OpLo = AVR::STPtrPdRr;
1137   unsigned OpHi = AVR::STPtrPdRr;
1138   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1139 
1140   assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
1141 
1142   auto MIBHI = buildMI(MBB, MBBI, OpHi)
1143     .addReg(DstReg, RegState::Define)
1144     .addReg(DstReg, RegState::Kill)
1145     .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1146     .addImm(Imm);
1147 
1148   auto MIBLO = buildMI(MBB, MBBI, OpLo)
1149     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1150     .addReg(DstReg, RegState::Kill)
1151     .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1152     .addImm(Imm);
1153 
1154   MIBLO.setMemRefs(MI.memoperands());
1155   MIBHI.setMemRefs(MI.memoperands());
1156 
1157   MI.eraseFromParent();
1158   return true;
1159 }
1160 
1161 template <>
1162 bool AVRExpandPseudo::expand<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {
1163   MachineInstr &MI = *MBBI;
1164   Register SrcLoReg, SrcHiReg;
1165   Register DstReg = MI.getOperand(0).getReg();
1166   Register SrcReg = MI.getOperand(2).getReg();
1167   unsigned Imm = MI.getOperand(1).getImm();
1168   bool DstIsKill = MI.getOperand(0).isKill();
1169   bool SrcIsKill = MI.getOperand(2).isKill();
1170   unsigned OpLo = AVR::STDPtrQRr;
1171   unsigned OpHi = AVR::STDPtrQRr;
1172   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1173 
1174   // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
1175   // allowed for the instruction, 62 is the limit here.
1176   assert(Imm <= 62 && "Offset is out of range");
1177 
1178   auto MIBLO = buildMI(MBB, MBBI, OpLo)
1179     .addReg(DstReg)
1180     .addImm(Imm)
1181     .addReg(SrcLoReg, getKillRegState(SrcIsKill));
1182 
1183   auto MIBHI = buildMI(MBB, MBBI, OpHi)
1184     .addReg(DstReg, getKillRegState(DstIsKill))
1185     .addImm(Imm + 1)
1186     .addReg(SrcHiReg, getKillRegState(SrcIsKill));
1187 
1188   MIBLO.setMemRefs(MI.memoperands());
1189   MIBHI.setMemRefs(MI.memoperands());
1190 
1191   MI.eraseFromParent();
1192   return true;
1193 }
1194 
1195 template <>
1196 bool AVRExpandPseudo::expand<AVR::INWRdA>(Block &MBB, BlockIt MBBI) {
1197   MachineInstr &MI = *MBBI;
1198   Register DstLoReg, DstHiReg;
1199   unsigned Imm = MI.getOperand(1).getImm();
1200   Register DstReg = MI.getOperand(0).getReg();
1201   bool DstIsDead = MI.getOperand(0).isDead();
1202   unsigned OpLo = AVR::INRdA;
1203   unsigned OpHi = AVR::INRdA;
1204   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1205 
1206   // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
1207   // allowed for the instruction, 62 is the limit here.
1208   assert(Imm <= 62 && "Address is out of range");
1209 
1210   auto MIBLO = buildMI(MBB, MBBI, OpLo)
1211     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1212     .addImm(Imm);
1213 
1214   auto MIBHI = buildMI(MBB, MBBI, OpHi)
1215     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1216     .addImm(Imm + 1);
1217 
1218   MIBLO.setMemRefs(MI.memoperands());
1219   MIBHI.setMemRefs(MI.memoperands());
1220 
1221   MI.eraseFromParent();
1222   return true;
1223 }
1224 
1225 template <>
1226 bool AVRExpandPseudo::expand<AVR::OUTWARr>(Block &MBB, BlockIt MBBI) {
1227   MachineInstr &MI = *MBBI;
1228   Register SrcLoReg, SrcHiReg;
1229   unsigned Imm = MI.getOperand(0).getImm();
1230   Register SrcReg = MI.getOperand(1).getReg();
1231   bool SrcIsKill = MI.getOperand(1).isKill();
1232   unsigned OpLo = AVR::OUTARr;
1233   unsigned OpHi = AVR::OUTARr;
1234   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1235 
1236   // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
1237   // allowed for the instruction, 62 is the limit here.
1238   assert(Imm <= 62 && "Address is out of range");
1239 
1240   // 16 bit I/O writes need the high byte first
1241   auto MIBHI = buildMI(MBB, MBBI, OpHi)
1242     .addImm(Imm + 1)
1243     .addReg(SrcHiReg, getKillRegState(SrcIsKill));
1244 
1245   auto MIBLO = buildMI(MBB, MBBI, OpLo)
1246     .addImm(Imm)
1247     .addReg(SrcLoReg, getKillRegState(SrcIsKill));
1248 
1249   MIBLO.setMemRefs(MI.memoperands());
1250   MIBHI.setMemRefs(MI.memoperands());
1251 
1252   MI.eraseFromParent();
1253   return true;
1254 }
1255 
1256 template <>
1257 bool AVRExpandPseudo::expand<AVR::PUSHWRr>(Block &MBB, BlockIt MBBI) {
1258   MachineInstr &MI = *MBBI;
1259   Register SrcLoReg, SrcHiReg;
1260   Register SrcReg = MI.getOperand(0).getReg();
1261   bool SrcIsKill = MI.getOperand(0).isKill();
1262   unsigned Flags = MI.getFlags();
1263   unsigned OpLo = AVR::PUSHRr;
1264   unsigned OpHi = AVR::PUSHRr;
1265   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1266 
1267   // Low part
1268   buildMI(MBB, MBBI, OpLo)
1269     .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1270     .setMIFlags(Flags);
1271 
1272   // High part
1273   buildMI(MBB, MBBI, OpHi)
1274     .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1275     .setMIFlags(Flags);
1276 
1277   MI.eraseFromParent();
1278   return true;
1279 }
1280 
1281 template <>
1282 bool AVRExpandPseudo::expand<AVR::POPWRd>(Block &MBB, BlockIt MBBI) {
1283   MachineInstr &MI = *MBBI;
1284   Register DstLoReg, DstHiReg;
1285   Register DstReg = MI.getOperand(0).getReg();
1286   unsigned Flags = MI.getFlags();
1287   unsigned OpLo = AVR::POPRd;
1288   unsigned OpHi = AVR::POPRd;
1289   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1290 
1291   buildMI(MBB, MBBI, OpHi, DstHiReg).setMIFlags(Flags); // High
1292   buildMI(MBB, MBBI, OpLo, DstLoReg).setMIFlags(Flags); // Low
1293 
1294   MI.eraseFromParent();
1295   return true;
1296 }
1297 
1298 template <>
1299 bool AVRExpandPseudo::expand<AVR::ROLBRd>(Block &MBB, BlockIt MBBI) {
1300   // In AVR, the rotate instructions behave quite unintuitively. They rotate
1301   // bits through the carry bit in SREG, effectively rotating over 9 bits,
1302   // instead of 8. This is useful when we are dealing with numbers over
1303   // multiple registers, but when we actually need to rotate stuff, we have
1304   // to explicitly add the carry bit.
1305 
1306   MachineInstr &MI = *MBBI;
1307   unsigned OpShift, OpCarry;
1308   Register DstReg = MI.getOperand(0).getReg();
1309   bool DstIsDead = MI.getOperand(0).isDead();
1310   OpShift = AVR::ADDRdRr;
1311   OpCarry = AVR::ADCRdRr;
1312 
1313   // add r16, r16
1314   // adc r16, r1
1315 
1316   // Shift part
1317   buildMI(MBB, MBBI, OpShift)
1318     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1319     .addReg(DstReg)
1320     .addReg(DstReg);
1321 
1322   // Add the carry bit
1323   auto MIB = buildMI(MBB, MBBI, OpCarry)
1324     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1325     .addReg(DstReg)
1326     .addReg(ZERO_REGISTER);
1327 
1328   // SREG is always implicitly killed
1329   MIB->getOperand(2).setIsKill();
1330 
1331   MI.eraseFromParent();
1332   return true;
1333 }
1334 
1335 template <>
1336 bool AVRExpandPseudo::expand<AVR::RORBRd>(Block &MBB, BlockIt MBBI) {
1337   // In AVR, the rotate instructions behave quite unintuitively. They rotate
1338   // bits through the carry bit in SREG, effectively rotating over 9 bits,
1339   // instead of 8. This is useful when we are dealing with numbers over
1340   // multiple registers, but when we actually need to rotate stuff, we have
1341   // to explicitly add the carry bit.
1342 
1343   MachineInstr &MI = *MBBI;
1344   unsigned OpShiftOut, OpLoad, OpShiftIn, OpAdd;
1345   Register DstReg = MI.getOperand(0).getReg();
1346   bool DstIsDead = MI.getOperand(0).isDead();
1347   OpShiftOut = AVR::LSRRd;
1348   OpLoad = AVR::LDIRdK;
1349   OpShiftIn = AVR::RORRd;
1350   OpAdd = AVR::ORRdRr;
1351 
1352   // lsr r16
1353   // ldi r0, 0
1354   // ror r0
1355   // or r16, r17
1356 
1357   // Shift out
1358   buildMI(MBB, MBBI, OpShiftOut)
1359     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1360     .addReg(DstReg);
1361 
1362   // Put 0 in temporary register
1363   buildMI(MBB, MBBI, OpLoad)
1364     .addReg(SCRATCH_REGISTER, RegState::Define | getDeadRegState(true))
1365     .addImm(0x00);
1366 
1367   // Shift in
1368   buildMI(MBB, MBBI, OpShiftIn)
1369     .addReg(SCRATCH_REGISTER, RegState::Define | getDeadRegState(true))
1370     .addReg(SCRATCH_REGISTER);
1371 
1372   // Add the results together using an or-instruction
1373   auto MIB = buildMI(MBB, MBBI, OpAdd)
1374     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1375     .addReg(DstReg)
1376     .addReg(SCRATCH_REGISTER);
1377 
1378   // SREG is always implicitly killed
1379   MIB->getOperand(2).setIsKill();
1380 
1381   MI.eraseFromParent();
1382   return true;
1383 }
1384 
1385 template <>
1386 bool AVRExpandPseudo::expand<AVR::LSLWRd>(Block &MBB, BlockIt MBBI) {
1387   MachineInstr &MI = *MBBI;
1388   Register DstLoReg, DstHiReg;
1389   Register DstReg = MI.getOperand(0).getReg();
1390   bool DstIsDead = MI.getOperand(0).isDead();
1391   bool DstIsKill = MI.getOperand(1).isKill();
1392   bool ImpIsDead = MI.getOperand(2).isDead();
1393   unsigned OpLo = AVR::ADDRdRr; // ADD Rd, Rd <==> LSL Rd
1394   unsigned OpHi = AVR::ADCRdRr; // ADC Rd, Rd <==> ROL Rd
1395   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1396 
1397   // Low part
1398   buildMI(MBB, MBBI, OpLo)
1399     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1400     .addReg(DstLoReg)
1401     .addReg(DstLoReg, getKillRegState(DstIsKill));
1402 
1403   auto MIBHI = buildMI(MBB, MBBI, OpHi)
1404     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1405     .addReg(DstHiReg)
1406     .addReg(DstHiReg, getKillRegState(DstIsKill));
1407 
1408   if (ImpIsDead)
1409     MIBHI->getOperand(3).setIsDead();
1410 
1411   // SREG is always implicitly killed
1412   MIBHI->getOperand(4).setIsKill();
1413 
1414   MI.eraseFromParent();
1415   return true;
1416 }
1417 
1418 bool AVRExpandPseudo::expandLSLW4Rd(Block &MBB, BlockIt MBBI) {
1419   MachineInstr &MI = *MBBI;
1420   Register DstLoReg, DstHiReg;
1421   Register DstReg = MI.getOperand(0).getReg();
1422   bool DstIsDead = MI.getOperand(0).isDead();
1423   bool DstIsKill = MI.getOperand(1).isKill();
1424   bool ImpIsDead = MI.getOperand(3).isDead();
1425   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1426 
1427   // swap Rh
1428   // swap Rl
1429   buildMI(MBB, MBBI, AVR::SWAPRd)
1430       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1431       .addReg(DstHiReg, getKillRegState(DstIsKill));
1432   buildMI(MBB, MBBI, AVR::SWAPRd)
1433       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1434       .addReg(DstLoReg, getKillRegState(DstIsKill));
1435 
1436   // andi Rh, 0xf0
1437   auto MI0 =
1438       buildMI(MBB, MBBI, AVR::ANDIRdK)
1439           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1440           .addReg(DstHiReg, getKillRegState(DstIsKill))
1441           .addImm(0xf0);
1442   // SREG is implicitly dead.
1443   MI0->getOperand(3).setIsDead();
1444 
1445   // eor Rh, Rl
1446   auto MI1 =
1447       buildMI(MBB, MBBI, AVR::EORRdRr)
1448           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1449           .addReg(DstHiReg, getKillRegState(DstIsKill))
1450           .addReg(DstLoReg);
1451   // SREG is implicitly dead.
1452   MI1->getOperand(3).setIsDead();
1453 
1454   // andi Rl, 0xf0
1455   auto MI2 =
1456       buildMI(MBB, MBBI, AVR::ANDIRdK)
1457           .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1458           .addReg(DstLoReg, getKillRegState(DstIsKill))
1459           .addImm(0xf0);
1460   // SREG is implicitly dead.
1461   MI2->getOperand(3).setIsDead();
1462 
1463   // eor Rh, Rl
1464   auto MI3 =
1465       buildMI(MBB, MBBI, AVR::EORRdRr)
1466           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1467           .addReg(DstHiReg, getKillRegState(DstIsKill))
1468           .addReg(DstLoReg);
1469   if (ImpIsDead)
1470     MI3->getOperand(3).setIsDead();
1471 
1472   MI.eraseFromParent();
1473   return true;
1474 }
1475 
1476 bool AVRExpandPseudo::expandLSLW8Rd(Block &MBB, BlockIt MBBI) {
1477   MachineInstr &MI = *MBBI;
1478   Register DstLoReg, DstHiReg;
1479   Register DstReg = MI.getOperand(0).getReg();
1480   bool DstIsDead = MI.getOperand(0).isDead();
1481   bool DstIsKill = MI.getOperand(1).isKill();
1482   bool ImpIsDead = MI.getOperand(3).isDead();
1483   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1484 
1485   // mov Rh, Rl
1486   buildMI(MBB, MBBI, AVR::MOVRdRr)
1487       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1488       .addReg(DstLoReg);
1489 
1490   // clr Rl
1491   auto MIBLO =
1492       buildMI(MBB, MBBI, AVR::EORRdRr)
1493           .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1494           .addReg(DstLoReg, getKillRegState(DstIsKill))
1495           .addReg(DstLoReg, getKillRegState(DstIsKill));
1496   if (ImpIsDead)
1497     MIBLO->getOperand(3).setIsDead();
1498 
1499   MI.eraseFromParent();
1500   return true;
1501 }
1502 
1503 bool AVRExpandPseudo::expandLSLW12Rd(Block &MBB, BlockIt MBBI) {
1504   MachineInstr &MI = *MBBI;
1505   Register DstLoReg, DstHiReg;
1506   Register DstReg = MI.getOperand(0).getReg();
1507   bool DstIsDead = MI.getOperand(0).isDead();
1508   bool DstIsKill = MI.getOperand(1).isKill();
1509   bool ImpIsDead = MI.getOperand(3).isDead();
1510   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1511 
1512   // mov Rh, Rl
1513   buildMI(MBB, MBBI, AVR::MOVRdRr)
1514       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1515       .addReg(DstLoReg);
1516 
1517   // swap Rh
1518   buildMI(MBB, MBBI, AVR::SWAPRd)
1519       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1520       .addReg(DstHiReg, getKillRegState(DstIsKill));
1521 
1522   // andi Rh, 0xf0
1523   auto MI0 =
1524       buildMI(MBB, MBBI, AVR::ANDIRdK)
1525           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1526           .addReg(DstHiReg, getKillRegState(DstIsKill))
1527           .addImm(0xf0);
1528   // SREG is implicitly dead.
1529   MI0->getOperand(3).setIsDead();
1530 
1531   // clr Rl
1532   auto MI1 =
1533       buildMI(MBB, MBBI, AVR::EORRdRr)
1534           .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1535           .addReg(DstLoReg, getKillRegState(DstIsKill))
1536           .addReg(DstLoReg, getKillRegState(DstIsKill));
1537   if (ImpIsDead)
1538     MI1->getOperand(3).setIsDead();
1539 
1540   MI.eraseFromParent();
1541   return true;
1542 }
1543 
1544 template <>
1545 bool AVRExpandPseudo::expand<AVR::LSLWNRd>(Block &MBB, BlockIt MBBI) {
1546   MachineInstr &MI = *MBBI;
1547   unsigned Imm = MI.getOperand(2).getImm();
1548   switch (Imm) {
1549   case 4:
1550     return expandLSLW4Rd(MBB, MBBI);
1551   case 8:
1552     return expandLSLW8Rd(MBB, MBBI);
1553   case 12:
1554     return expandLSLW12Rd(MBB, MBBI);
1555   default:
1556     llvm_unreachable("unimplemented lslwn");
1557     return false;
1558   }
1559 }
1560 
1561 template <>
1562 bool AVRExpandPseudo::expand<AVR::LSRWRd>(Block &MBB, BlockIt MBBI) {
1563   MachineInstr &MI = *MBBI;
1564   Register DstLoReg, DstHiReg;
1565   Register DstReg = MI.getOperand(0).getReg();
1566   bool DstIsDead = MI.getOperand(0).isDead();
1567   bool DstIsKill = MI.getOperand(1).isKill();
1568   bool ImpIsDead = MI.getOperand(2).isDead();
1569   unsigned OpLo = AVR::RORRd;
1570   unsigned OpHi = AVR::LSRRd;
1571   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1572 
1573   // High part
1574   buildMI(MBB, MBBI, OpHi)
1575     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1576     .addReg(DstHiReg, getKillRegState(DstIsKill));
1577 
1578   auto MIBLO = buildMI(MBB, MBBI, OpLo)
1579     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1580     .addReg(DstLoReg, getKillRegState(DstIsKill));
1581 
1582   if (ImpIsDead)
1583     MIBLO->getOperand(2).setIsDead();
1584 
1585   // SREG is always implicitly killed
1586   MIBLO->getOperand(3).setIsKill();
1587 
1588   MI.eraseFromParent();
1589   return true;
1590 }
1591 
1592 bool AVRExpandPseudo::expandLSRW4Rd(Block &MBB, BlockIt MBBI) {
1593   MachineInstr &MI = *MBBI;
1594   Register DstLoReg, DstHiReg;
1595   Register DstReg = MI.getOperand(0).getReg();
1596   bool DstIsDead = MI.getOperand(0).isDead();
1597   bool DstIsKill = MI.getOperand(1).isKill();
1598   bool ImpIsDead = MI.getOperand(3).isDead();
1599   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1600 
1601   // swap Rh
1602   // swap Rl
1603   buildMI(MBB, MBBI, AVR::SWAPRd)
1604       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1605       .addReg(DstHiReg, getKillRegState(DstIsKill));
1606   buildMI(MBB, MBBI, AVR::SWAPRd)
1607       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1608       .addReg(DstLoReg, getKillRegState(DstIsKill));
1609 
1610   // andi Rl, 0xf
1611   auto MI0 =
1612       buildMI(MBB, MBBI, AVR::ANDIRdK)
1613           .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1614           .addReg(DstLoReg, getKillRegState(DstIsKill))
1615           .addImm(0xf);
1616   // SREG is implicitly dead.
1617   MI0->getOperand(3).setIsDead();
1618 
1619   // eor Rl, Rh
1620   auto MI1 =
1621       buildMI(MBB, MBBI, AVR::EORRdRr)
1622           .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1623           .addReg(DstLoReg, getKillRegState(DstIsKill))
1624           .addReg(DstHiReg);
1625   // SREG is implicitly dead.
1626   MI1->getOperand(3).setIsDead();
1627 
1628   // andi Rh, 0xf
1629   auto MI2 =
1630       buildMI(MBB, MBBI, AVR::ANDIRdK)
1631           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1632           .addReg(DstHiReg, getKillRegState(DstIsKill))
1633           .addImm(0xf);
1634   // SREG is implicitly dead.
1635   MI2->getOperand(3).setIsDead();
1636 
1637   // eor Rl, Rh
1638   auto MI3 =
1639       buildMI(MBB, MBBI, AVR::EORRdRr)
1640           .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1641           .addReg(DstLoReg, getKillRegState(DstIsKill))
1642           .addReg(DstHiReg);
1643   if (ImpIsDead)
1644     MI3->getOperand(3).setIsDead();
1645 
1646   MI.eraseFromParent();
1647   return true;
1648 }
1649 
1650 bool AVRExpandPseudo::expandLSRW8Rd(Block &MBB, BlockIt MBBI) {
1651   MachineInstr &MI = *MBBI;
1652   Register DstLoReg, DstHiReg;
1653   Register DstReg = MI.getOperand(0).getReg();
1654   bool DstIsDead = MI.getOperand(0).isDead();
1655   bool DstIsKill = MI.getOperand(1).isKill();
1656   bool ImpIsDead = MI.getOperand(3).isDead();
1657   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1658 
1659   // Move upper byte to lower byte.
1660   buildMI(MBB, MBBI, AVR::MOVRdRr)
1661       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1662       .addReg(DstHiReg);
1663 
1664   // Clear upper byte.
1665   auto MIBHI =
1666       buildMI(MBB, MBBI, AVR::EORRdRr)
1667           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1668           .addReg(DstHiReg, getKillRegState(DstIsKill))
1669           .addReg(DstHiReg, getKillRegState(DstIsKill));
1670   if (ImpIsDead)
1671     MIBHI->getOperand(3).setIsDead();
1672 
1673   MI.eraseFromParent();
1674   return true;
1675 }
1676 
1677 bool AVRExpandPseudo::expandLSRW12Rd(Block &MBB, BlockIt MBBI) {
1678   MachineInstr &MI = *MBBI;
1679   Register DstLoReg, DstHiReg;
1680   Register DstReg = MI.getOperand(0).getReg();
1681   bool DstIsDead = MI.getOperand(0).isDead();
1682   bool DstIsKill = MI.getOperand(1).isKill();
1683   bool ImpIsDead = MI.getOperand(3).isDead();
1684   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1685 
1686   // Move upper byte to lower byte.
1687   buildMI(MBB, MBBI, AVR::MOVRdRr)
1688       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1689       .addReg(DstHiReg);
1690 
1691   // swap Rl
1692   buildMI(MBB, MBBI, AVR::SWAPRd)
1693       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1694       .addReg(DstLoReg, getKillRegState(DstIsKill));
1695 
1696   // andi Rl, 0xf
1697   auto MI0 =
1698       buildMI(MBB, MBBI, AVR::ANDIRdK)
1699           .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1700           .addReg(DstLoReg, getKillRegState(DstIsKill))
1701           .addImm(0xf);
1702   // SREG is implicitly dead.
1703   MI0->getOperand(3).setIsDead();
1704 
1705   // Clear upper byte.
1706   auto MIBHI =
1707       buildMI(MBB, MBBI, AVR::EORRdRr)
1708           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1709           .addReg(DstHiReg, getKillRegState(DstIsKill))
1710           .addReg(DstHiReg, getKillRegState(DstIsKill));
1711   if (ImpIsDead)
1712     MIBHI->getOperand(3).setIsDead();
1713 
1714   MI.eraseFromParent();
1715   return true;
1716 }
1717 
1718 template <>
1719 bool AVRExpandPseudo::expand<AVR::LSRWNRd>(Block &MBB, BlockIt MBBI) {
1720   MachineInstr &MI = *MBBI;
1721   unsigned Imm = MI.getOperand(2).getImm();
1722   switch (Imm) {
1723   case 4:
1724     return expandLSRW4Rd(MBB, MBBI);
1725   case 8:
1726     return expandLSRW8Rd(MBB, MBBI);
1727   case 12:
1728     return expandLSRW12Rd(MBB, MBBI);
1729   default:
1730     llvm_unreachable("unimplemented lsrwn");
1731     return false;
1732   }
1733 }
1734 
1735 template <>
1736 bool AVRExpandPseudo::expand<AVR::RORWRd>(Block &MBB, BlockIt MBBI) {
1737   llvm_unreachable("RORW unimplemented");
1738   return false;
1739 }
1740 
1741 template <>
1742 bool AVRExpandPseudo::expand<AVR::ROLWRd>(Block &MBB, BlockIt MBBI) {
1743   llvm_unreachable("ROLW unimplemented");
1744   return false;
1745 }
1746 
1747 template <>
1748 bool AVRExpandPseudo::expand<AVR::ASRWRd>(Block &MBB, BlockIt MBBI) {
1749   MachineInstr &MI = *MBBI;
1750   Register DstLoReg, DstHiReg;
1751   Register DstReg = MI.getOperand(0).getReg();
1752   bool DstIsDead = MI.getOperand(0).isDead();
1753   bool DstIsKill = MI.getOperand(1).isKill();
1754   bool ImpIsDead = MI.getOperand(2).isDead();
1755   unsigned OpLo = AVR::RORRd;
1756   unsigned OpHi = AVR::ASRRd;
1757   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1758 
1759   // High part
1760   buildMI(MBB, MBBI, OpHi)
1761     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1762     .addReg(DstHiReg, getKillRegState(DstIsKill));
1763 
1764   auto MIBLO = buildMI(MBB, MBBI, OpLo)
1765     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1766     .addReg(DstLoReg, getKillRegState(DstIsKill));
1767 
1768   if (ImpIsDead)
1769     MIBLO->getOperand(2).setIsDead();
1770 
1771   // SREG is always implicitly killed
1772   MIBLO->getOperand(3).setIsKill();
1773 
1774   MI.eraseFromParent();
1775   return true;
1776 }
1777 
1778 bool AVRExpandPseudo::expandASRW8Rd(Block &MBB, BlockIt MBBI) {
1779   MachineInstr &MI = *MBBI;
1780   Register DstLoReg, DstHiReg;
1781   Register DstReg = MI.getOperand(0).getReg();
1782   bool DstIsDead = MI.getOperand(0).isDead();
1783   bool DstIsKill = MI.getOperand(1).isKill();
1784   bool ImpIsDead = MI.getOperand(3).isDead();
1785   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1786 
1787   // Move upper byte to lower byte.
1788   buildMI(MBB, MBBI, AVR::MOVRdRr)
1789       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1790       .addReg(DstHiReg);
1791 
1792   // Move the sign bit to the C flag.
1793   buildMI(MBB, MBBI, AVR::ADDRdRr)
1794       .addReg(DstHiReg, RegState::Define, getDeadRegState(DstIsDead))
1795       .addReg(DstHiReg, getKillRegState(DstIsKill) | getDeadRegState(DstIsDead))
1796       .addReg(DstHiReg, getKillRegState(DstIsKill));
1797 
1798   // Set upper byte to 0 or -1.
1799   auto MIBHI =
1800       buildMI(MBB, MBBI, AVR::SBCRdRr)
1801           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1802           .addReg(DstHiReg, getKillRegState(DstIsKill))
1803           .addReg(DstHiReg, getKillRegState(DstIsKill));
1804   if (ImpIsDead)
1805     MIBHI->getOperand(3).setIsDead();
1806 
1807   MI.eraseFromParent();
1808   return true;
1809 }
1810 
1811 template <>
1812 bool AVRExpandPseudo::expand<AVR::ASRWNRd>(Block &MBB, BlockIt MBBI) {
1813   MachineInstr &MI = *MBBI;
1814   unsigned Imm = MI.getOperand(2).getImm();
1815   switch (Imm) {
1816   case 8:
1817     return expandASRW8Rd(MBB, MBBI);
1818   default:
1819     llvm_unreachable("unimplemented asrwn");
1820     return false;
1821   }
1822 }
1823 
1824 bool AVRExpandPseudo::expandLSLB7Rd(Block &MBB, BlockIt MBBI) {
1825   MachineInstr &MI = *MBBI;
1826   Register DstReg = MI.getOperand(0).getReg();
1827   bool DstIsDead = MI.getOperand(0).isDead();
1828   bool DstIsKill = MI.getOperand(1).isKill();
1829   bool ImpIsDead = MI.getOperand(3).isDead();
1830 
1831   // ror r24
1832   // clr r24
1833   // ror r24
1834 
1835   buildMI(MBB, MBBI, AVR::RORRd)
1836       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1837       .addReg(DstReg, getKillRegState(DstIsKill))
1838       ->getOperand(3).setIsUndef(true);
1839 
1840   buildMI(MBB, MBBI, AVR::EORRdRr)
1841       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1842       .addReg(DstReg, getKillRegState(DstIsKill))
1843       .addReg(DstReg, getKillRegState(DstIsKill));
1844 
1845   auto MIRRC =
1846       buildMI(MBB, MBBI, AVR::RORRd)
1847           .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1848           .addReg(DstReg, getKillRegState(DstIsKill));
1849 
1850   if (ImpIsDead)
1851     MIRRC->getOperand(2).setIsDead();
1852 
1853   // SREG is always implicitly killed
1854   MIRRC->getOperand(3).setIsKill();
1855 
1856   MI.eraseFromParent();
1857   return true;
1858 }
1859 
1860 template <>
1861 bool AVRExpandPseudo::expand<AVR::LSLBNRd>(Block &MBB, BlockIt MBBI) {
1862   MachineInstr &MI = *MBBI;
1863   unsigned Imm = MI.getOperand(2).getImm();
1864   switch (Imm) {
1865   case 7:
1866     return expandLSLB7Rd(MBB, MBBI);
1867   default:
1868     llvm_unreachable("unimplemented lslbn");
1869     return false;
1870   }
1871 }
1872 
1873 bool AVRExpandPseudo::expandLSRB7Rd(Block &MBB, BlockIt MBBI) {
1874   MachineInstr &MI = *MBBI;
1875   Register DstReg = MI.getOperand(0).getReg();
1876   bool DstIsDead = MI.getOperand(0).isDead();
1877   bool DstIsKill = MI.getOperand(1).isKill();
1878   bool ImpIsDead = MI.getOperand(3).isDead();
1879 
1880   // rol r24
1881   // clr r24
1882   // rol r24
1883 
1884   buildMI(MBB, MBBI, AVR::ADCRdRr)
1885       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1886       .addReg(DstReg, getKillRegState(DstIsKill))
1887       .addReg(DstReg, getKillRegState(DstIsKill))
1888       ->getOperand(4).setIsUndef(true);
1889 
1890   buildMI(MBB, MBBI, AVR::EORRdRr)
1891       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1892       .addReg(DstReg, getKillRegState(DstIsKill))
1893       .addReg(DstReg, getKillRegState(DstIsKill));
1894 
1895   auto MIRRC =
1896       buildMI(MBB, MBBI, AVR::ADCRdRr)
1897           .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1898           .addReg(DstReg, getKillRegState(DstIsKill))
1899           .addReg(DstReg, getKillRegState(DstIsKill));
1900 
1901   if (ImpIsDead)
1902     MIRRC->getOperand(3).setIsDead();
1903 
1904   // SREG is always implicitly killed
1905   MIRRC->getOperand(4).setIsKill();
1906 
1907   MI.eraseFromParent();
1908   return true;
1909 }
1910 
1911 template <>
1912 bool AVRExpandPseudo::expand<AVR::LSRBNRd>(Block &MBB, BlockIt MBBI) {
1913   MachineInstr &MI = *MBBI;
1914   unsigned Imm = MI.getOperand(2).getImm();
1915   switch (Imm) {
1916   case 7:
1917     return expandLSRB7Rd(MBB, MBBI);
1918   default:
1919     llvm_unreachable("unimplemented lsrbn");
1920     return false;
1921   }
1922 }
1923 
1924 bool AVRExpandPseudo::expandASRB7Rd(Block &MBB, BlockIt MBBI) {
1925   MachineInstr &MI = *MBBI;
1926   Register DstReg = MI.getOperand(0).getReg();
1927   bool DstIsDead = MI.getOperand(0).isDead();
1928   bool DstIsKill = MI.getOperand(1).isKill();
1929   bool ImpIsDead = MI.getOperand(3).isDead();
1930 
1931   // lsl r24
1932   // sbc r24, r24
1933 
1934   buildMI(MBB, MBBI, AVR::ADDRdRr)
1935       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1936       .addReg(DstReg, getKillRegState(DstIsKill))
1937       .addReg(DstReg, getKillRegState(DstIsKill));
1938 
1939   auto MIRRC = buildMI(MBB, MBBI, AVR::SBCRdRr)
1940       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1941       .addReg(DstReg, getKillRegState(DstIsKill))
1942       .addReg(DstReg, getKillRegState(DstIsKill));
1943 
1944   if (ImpIsDead)
1945     MIRRC->getOperand(3).setIsDead();
1946 
1947   // SREG is always implicitly killed
1948   MIRRC->getOperand(4).setIsKill();
1949 
1950   MI.eraseFromParent();
1951   return true;
1952 }
1953 
1954 template <>
1955 bool AVRExpandPseudo::expand<AVR::ASRBNRd>(Block &MBB, BlockIt MBBI) {
1956   MachineInstr &MI = *MBBI;
1957   unsigned Imm = MI.getOperand(2).getImm();
1958   switch (Imm) {
1959   case 7:
1960     return expandASRB7Rd(MBB, MBBI);
1961   default:
1962     llvm_unreachable("unimplemented asrbn");
1963     return false;
1964   }
1965 }
1966 
1967 template <> bool AVRExpandPseudo::expand<AVR::SEXT>(Block &MBB, BlockIt MBBI) {
1968   MachineInstr &MI = *MBBI;
1969   Register DstLoReg, DstHiReg;
1970   // sext R17:R16, R17
1971   // mov     r16, r17
1972   // lsl     r17
1973   // sbc     r17, r17
1974   // sext R17:R16, R13
1975   // mov     r16, r13
1976   // mov     r17, r13
1977   // lsl     r17
1978   // sbc     r17, r17
1979   // sext R17:R16, R16
1980   // mov     r17, r16
1981   // lsl     r17
1982   // sbc     r17, r17
1983   Register DstReg = MI.getOperand(0).getReg();
1984   Register SrcReg = MI.getOperand(1).getReg();
1985   bool DstIsDead = MI.getOperand(0).isDead();
1986   bool SrcIsKill = MI.getOperand(1).isKill();
1987   bool ImpIsDead = MI.getOperand(2).isDead();
1988   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1989 
1990   if (SrcReg != DstLoReg) {
1991     auto MOV = buildMI(MBB, MBBI, AVR::MOVRdRr)
1992       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1993       .addReg(SrcReg);
1994 
1995     if (SrcReg == DstHiReg) {
1996       MOV->getOperand(1).setIsKill();
1997     }
1998   }
1999 
2000   if (SrcReg != DstHiReg) {
2001     buildMI(MBB, MBBI, AVR::MOVRdRr)
2002       .addReg(DstHiReg, RegState::Define)
2003       .addReg(SrcReg, getKillRegState(SrcIsKill));
2004   }
2005 
2006   buildMI(MBB, MBBI, AVR::ADDRdRr) // LSL Rd <==> ADD Rd, Rr
2007     .addReg(DstHiReg, RegState::Define)
2008     .addReg(DstHiReg)
2009     .addReg(DstHiReg, RegState::Kill);
2010 
2011   auto SBC = buildMI(MBB, MBBI, AVR::SBCRdRr)
2012     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2013     .addReg(DstHiReg, RegState::Kill)
2014     .addReg(DstHiReg, RegState::Kill);
2015 
2016   if (ImpIsDead)
2017     SBC->getOperand(3).setIsDead();
2018 
2019   // SREG is always implicitly killed
2020   SBC->getOperand(4).setIsKill();
2021 
2022   MI.eraseFromParent();
2023   return true;
2024 }
2025 
2026 template <> bool AVRExpandPseudo::expand<AVR::ZEXT>(Block &MBB, BlockIt MBBI) {
2027   MachineInstr &MI = *MBBI;
2028   Register DstLoReg, DstHiReg;
2029   // zext R25:R24, R20
2030   // mov      R24, R20
2031   // eor      R25, R25
2032   // zext R25:R24, R24
2033   // eor      R25, R25
2034   // zext R25:R24, R25
2035   // mov      R24, R25
2036   // eor      R25, R25
2037   Register DstReg = MI.getOperand(0).getReg();
2038   Register SrcReg = MI.getOperand(1).getReg();
2039   bool DstIsDead = MI.getOperand(0).isDead();
2040   bool SrcIsKill = MI.getOperand(1).isKill();
2041   bool ImpIsDead = MI.getOperand(2).isDead();
2042   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2043 
2044   if (SrcReg != DstLoReg) {
2045     buildMI(MBB, MBBI, AVR::MOVRdRr)
2046       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2047       .addReg(SrcReg, getKillRegState(SrcIsKill));
2048   }
2049 
2050   auto EOR = buildMI(MBB, MBBI, AVR::EORRdRr)
2051     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2052     .addReg(DstHiReg, RegState::Kill | RegState::Undef)
2053     .addReg(DstHiReg, RegState::Kill | RegState::Undef);
2054 
2055   if (ImpIsDead)
2056     EOR->getOperand(3).setIsDead();
2057 
2058   MI.eraseFromParent();
2059   return true;
2060 }
2061 
2062 template <>
2063 bool AVRExpandPseudo::expand<AVR::SPREAD>(Block &MBB, BlockIt MBBI) {
2064   MachineInstr &MI = *MBBI;
2065   Register DstLoReg, DstHiReg;
2066   Register DstReg = MI.getOperand(0).getReg();
2067   bool DstIsDead = MI.getOperand(0).isDead();
2068   unsigned Flags = MI.getFlags();
2069   unsigned OpLo = AVR::INRdA;
2070   unsigned OpHi = AVR::INRdA;
2071   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2072 
2073   // Low part
2074   buildMI(MBB, MBBI, OpLo)
2075     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2076     .addImm(0x3d)
2077     .setMIFlags(Flags);
2078 
2079   // High part
2080   buildMI(MBB, MBBI, OpHi)
2081     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2082     .addImm(0x3e)
2083     .setMIFlags(Flags);
2084 
2085   MI.eraseFromParent();
2086   return true;
2087 }
2088 
2089 template <>
2090 bool AVRExpandPseudo::expand<AVR::SPWRITE>(Block &MBB, BlockIt MBBI) {
2091   MachineInstr &MI = *MBBI;
2092   Register SrcLoReg, SrcHiReg;
2093   Register SrcReg = MI.getOperand(1).getReg();
2094   bool SrcIsKill = MI.getOperand(1).isKill();
2095   unsigned Flags = MI.getFlags();
2096   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
2097 
2098   buildMI(MBB, MBBI, AVR::INRdA)
2099     .addReg(AVR::R0, RegState::Define)
2100     .addImm(SREG_ADDR)
2101     .setMIFlags(Flags);
2102 
2103   buildMI(MBB, MBBI, AVR::BCLRs).addImm(0x07).setMIFlags(Flags);
2104 
2105   buildMI(MBB, MBBI, AVR::OUTARr)
2106     .addImm(0x3e)
2107     .addReg(SrcHiReg, getKillRegState(SrcIsKill))
2108     .setMIFlags(Flags);
2109 
2110   buildMI(MBB, MBBI, AVR::OUTARr)
2111     .addImm(SREG_ADDR)
2112     .addReg(AVR::R0, RegState::Kill)
2113     .setMIFlags(Flags);
2114 
2115   buildMI(MBB, MBBI, AVR::OUTARr)
2116     .addImm(0x3d)
2117     .addReg(SrcLoReg, getKillRegState(SrcIsKill))
2118     .setMIFlags(Flags);
2119 
2120   MI.eraseFromParent();
2121   return true;
2122 }
2123 
2124 bool AVRExpandPseudo::expandMI(Block &MBB, BlockIt MBBI) {
2125   MachineInstr &MI = *MBBI;
2126   int Opcode = MBBI->getOpcode();
2127 
2128 #define EXPAND(Op)               \
2129   case Op:                       \
2130     return expand<Op>(MBB, MI)
2131 
2132   switch (Opcode) {
2133     EXPAND(AVR::ADDWRdRr);
2134     EXPAND(AVR::ADCWRdRr);
2135     EXPAND(AVR::SUBWRdRr);
2136     EXPAND(AVR::SUBIWRdK);
2137     EXPAND(AVR::SBCWRdRr);
2138     EXPAND(AVR::SBCIWRdK);
2139     EXPAND(AVR::ANDWRdRr);
2140     EXPAND(AVR::ANDIWRdK);
2141     EXPAND(AVR::ORWRdRr);
2142     EXPAND(AVR::ORIWRdK);
2143     EXPAND(AVR::EORWRdRr);
2144     EXPAND(AVR::COMWRd);
2145     EXPAND(AVR::NEGWRd);
2146     EXPAND(AVR::CPWRdRr);
2147     EXPAND(AVR::CPCWRdRr);
2148     EXPAND(AVR::LDIWRdK);
2149     EXPAND(AVR::LDSWRdK);
2150     EXPAND(AVR::LDWRdPtr);
2151     EXPAND(AVR::LDWRdPtrPi);
2152     EXPAND(AVR::LDWRdPtrPd);
2153   case AVR::LDDWRdYQ: //:FIXME: remove this once PR13375 gets fixed
2154     EXPAND(AVR::LDDWRdPtrQ);
2155     EXPAND(AVR::LPMWRdZ);
2156     EXPAND(AVR::LPMWRdZPi);
2157     EXPAND(AVR::AtomicLoad8);
2158     EXPAND(AVR::AtomicLoad16);
2159     EXPAND(AVR::AtomicStore8);
2160     EXPAND(AVR::AtomicStore16);
2161     EXPAND(AVR::AtomicLoadAdd8);
2162     EXPAND(AVR::AtomicLoadAdd16);
2163     EXPAND(AVR::AtomicLoadSub8);
2164     EXPAND(AVR::AtomicLoadSub16);
2165     EXPAND(AVR::AtomicLoadAnd8);
2166     EXPAND(AVR::AtomicLoadAnd16);
2167     EXPAND(AVR::AtomicLoadOr8);
2168     EXPAND(AVR::AtomicLoadOr16);
2169     EXPAND(AVR::AtomicLoadXor8);
2170     EXPAND(AVR::AtomicLoadXor16);
2171     EXPAND(AVR::AtomicFence);
2172     EXPAND(AVR::STSWKRr);
2173     EXPAND(AVR::STWPtrRr);
2174     EXPAND(AVR::STWPtrPiRr);
2175     EXPAND(AVR::STWPtrPdRr);
2176     EXPAND(AVR::STDWPtrQRr);
2177     EXPAND(AVR::INWRdA);
2178     EXPAND(AVR::OUTWARr);
2179     EXPAND(AVR::PUSHWRr);
2180     EXPAND(AVR::POPWRd);
2181     EXPAND(AVR::ROLBRd);
2182     EXPAND(AVR::RORBRd);
2183     EXPAND(AVR::LSLWRd);
2184     EXPAND(AVR::LSRWRd);
2185     EXPAND(AVR::RORWRd);
2186     EXPAND(AVR::ROLWRd);
2187     EXPAND(AVR::ASRWRd);
2188     EXPAND(AVR::LSLWNRd);
2189     EXPAND(AVR::LSRWNRd);
2190     EXPAND(AVR::ASRWNRd);
2191     EXPAND(AVR::LSLBNRd);
2192     EXPAND(AVR::LSRBNRd);
2193     EXPAND(AVR::ASRBNRd);
2194     EXPAND(AVR::SEXT);
2195     EXPAND(AVR::ZEXT);
2196     EXPAND(AVR::SPREAD);
2197     EXPAND(AVR::SPWRITE);
2198   }
2199 #undef EXPAND
2200   return false;
2201 }
2202 
2203 } // end of anonymous namespace
2204 
2205 INITIALIZE_PASS(AVRExpandPseudo, "avr-expand-pseudo",
2206                 AVR_EXPAND_PSEUDO_NAME, false, false)
2207 namespace llvm {
2208 
2209 FunctionPass *createAVRExpandPseudoPass() { return new AVRExpandPseudo(); }
2210 
2211 } // end of namespace llvm
2212