1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information --------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "Thumb2InstrInfo.h"
14 #include "ARMMachineFunctionInfo.h"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "llvm/CodeGen/MachineBasicBlock.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/CodeGen/MachineOperand.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/TargetRegisterInfo.h"
25 #include "llvm/IR/DebugLoc.h"
26 #include "llvm/MC/MCInst.h"
27 #include "llvm/MC/MCInstrDesc.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include <cassert>
33 
34 using namespace llvm;
35 
36 static cl::opt<bool>
37 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
38            cl::desc("Use old-style Thumb2 if-conversion heuristics"),
39            cl::init(false));
40 
41 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
42     : ARMBaseInstrInfo(STI) {}
43 
44 /// Return the noop instruction to use for a noop.
45 void Thumb2InstrInfo::getNoop(MCInst &NopInst) const {
46   NopInst.setOpcode(ARM::tHINT);
47   NopInst.addOperand(MCOperand::createImm(0));
48   NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
49   NopInst.addOperand(MCOperand::createReg(0));
50 }
51 
52 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
53   // FIXME
54   return 0;
55 }
56 
57 void
58 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
59                                          MachineBasicBlock *NewDest) const {
60   MachineBasicBlock *MBB = Tail->getParent();
61   ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
62   if (!AFI->hasITBlocks() || Tail->isBranch()) {
63     TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
64     return;
65   }
66 
67   // If the first instruction of Tail is predicated, we may have to update
68   // the IT instruction.
69   unsigned PredReg = 0;
70   ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg);
71   MachineBasicBlock::iterator MBBI = Tail;
72   if (CC != ARMCC::AL)
73     // Expecting at least the t2IT instruction before it.
74     --MBBI;
75 
76   // Actually replace the tail.
77   TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
78 
79   // Fix up IT.
80   if (CC != ARMCC::AL) {
81     MachineBasicBlock::iterator E = MBB->begin();
82     unsigned Count = 4; // At most 4 instructions in an IT block.
83     while (Count && MBBI != E) {
84       if (MBBI->isDebugInstr()) {
85         --MBBI;
86         continue;
87       }
88       if (MBBI->getOpcode() == ARM::t2IT) {
89         unsigned Mask = MBBI->getOperand(1).getImm();
90         if (Count == 4)
91           MBBI->eraseFromParent();
92         else {
93           unsigned MaskOn = 1 << Count;
94           unsigned MaskOff = ~(MaskOn - 1);
95           MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
96         }
97         return;
98       }
99       --MBBI;
100       --Count;
101     }
102 
103     // Ctrl flow can reach here if branch folding is run before IT block
104     // formation pass.
105   }
106 }
107 
108 bool
109 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
110                                      MachineBasicBlock::iterator MBBI) const {
111   while (MBBI->isDebugInstr()) {
112     ++MBBI;
113     if (MBBI == MBB.end())
114       return false;
115   }
116 
117   unsigned PredReg = 0;
118   return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL;
119 }
120 
121 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
122                                   MachineBasicBlock::iterator I,
123                                   const DebugLoc &DL, MCRegister DestReg,
124                                   MCRegister SrcReg, bool KillSrc) const {
125   // Handle SPR, DPR, and QPR copies.
126   if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
127     return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
128 
129   BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
130       .addReg(SrcReg, getKillRegState(KillSrc))
131       .add(predOps(ARMCC::AL));
132 }
133 
134 void Thumb2InstrInfo::
135 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
136                     unsigned SrcReg, bool isKill, int FI,
137                     const TargetRegisterClass *RC,
138                     const TargetRegisterInfo *TRI) const {
139   DebugLoc DL;
140   if (I != MBB.end()) DL = I->getDebugLoc();
141 
142   MachineFunction &MF = *MBB.getParent();
143   MachineFrameInfo &MFI = MF.getFrameInfo();
144   MachineMemOperand *MMO = MF.getMachineMemOperand(
145       MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
146       MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
147 
148   if (ARM::GPRRegClass.hasSubClassEq(RC)) {
149     BuildMI(MBB, I, DL, get(ARM::t2STRi12))
150         .addReg(SrcReg, getKillRegState(isKill))
151         .addFrameIndex(FI)
152         .addImm(0)
153         .addMemOperand(MMO)
154         .add(predOps(ARMCC::AL));
155     return;
156   }
157 
158   if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
159     // Thumb2 STRD expects its dest-registers to be in rGPR. Not a problem for
160     // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
161     // otherwise).
162     if (Register::isVirtualRegister(SrcReg)) {
163       MachineRegisterInfo *MRI = &MF.getRegInfo();
164       MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass);
165     }
166 
167     MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
168     AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
169     AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
170     MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO).add(predOps(ARMCC::AL));
171     return;
172   }
173 
174   ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
175 }
176 
177 void Thumb2InstrInfo::
178 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
179                      unsigned DestReg, int FI,
180                      const TargetRegisterClass *RC,
181                      const TargetRegisterInfo *TRI) const {
182   MachineFunction &MF = *MBB.getParent();
183   MachineFrameInfo &MFI = MF.getFrameInfo();
184   MachineMemOperand *MMO = MF.getMachineMemOperand(
185       MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
186       MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
187   DebugLoc DL;
188   if (I != MBB.end()) DL = I->getDebugLoc();
189 
190   if (ARM::GPRRegClass.hasSubClassEq(RC)) {
191     BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
192         .addFrameIndex(FI)
193         .addImm(0)
194         .addMemOperand(MMO)
195         .add(predOps(ARMCC::AL));
196     return;
197   }
198 
199   if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
200     // Thumb2 LDRD expects its dest-registers to be in rGPR. Not a problem for
201     // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
202     // otherwise).
203     if (Register::isVirtualRegister(DestReg)) {
204       MachineRegisterInfo *MRI = &MF.getRegInfo();
205       MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass);
206     }
207 
208     MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
209     AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
210     AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
211     MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO).add(predOps(ARMCC::AL));
212 
213     if (Register::isPhysicalRegister(DestReg))
214       MIB.addReg(DestReg, RegState::ImplicitDefine);
215     return;
216   }
217 
218   ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
219 }
220 
221 void Thumb2InstrInfo::expandLoadStackGuard(
222     MachineBasicBlock::iterator MI) const {
223   MachineFunction &MF = *MI->getParent()->getParent();
224   if (MF.getTarget().isPositionIndependent())
225     expandLoadStackGuardBase(MI, ARM::t2MOV_ga_pcrel, ARM::t2LDRi12);
226   else
227     expandLoadStackGuardBase(MI, ARM::t2MOVi32imm, ARM::t2LDRi12);
228 }
229 
230 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
231                                   MachineBasicBlock::iterator &MBBI,
232                                   const DebugLoc &dl, unsigned DestReg,
233                                   unsigned BaseReg, int NumBytes,
234                                   ARMCC::CondCodes Pred, unsigned PredReg,
235                                   const ARMBaseInstrInfo &TII,
236                                   unsigned MIFlags) {
237   if (NumBytes == 0 && DestReg != BaseReg) {
238     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
239       .addReg(BaseReg, RegState::Kill)
240       .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
241     return;
242   }
243 
244   bool isSub = NumBytes < 0;
245   if (isSub) NumBytes = -NumBytes;
246 
247   // If profitable, use a movw or movt to materialize the offset.
248   // FIXME: Use the scavenger to grab a scratch register.
249   if (DestReg != ARM::SP && DestReg != BaseReg &&
250       NumBytes >= 4096 &&
251       ARM_AM::getT2SOImmVal(NumBytes) == -1) {
252     bool Fits = false;
253     if (NumBytes < 65536) {
254       // Use a movw to materialize the 16-bit constant.
255       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
256         .addImm(NumBytes)
257         .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
258       Fits = true;
259     } else if ((NumBytes & 0xffff) == 0) {
260       // Use a movt to materialize the 32-bit constant.
261       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
262         .addReg(DestReg)
263         .addImm(NumBytes >> 16)
264         .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
265       Fits = true;
266     }
267 
268     if (Fits) {
269       if (isSub) {
270         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
271             .addReg(BaseReg)
272             .addReg(DestReg, RegState::Kill)
273             .add(predOps(Pred, PredReg))
274             .add(condCodeOp())
275             .setMIFlags(MIFlags);
276       } else {
277         // Here we know that DestReg is not SP but we do not
278         // know anything about BaseReg. t2ADDrr is an invalid
279         // instruction is SP is used as the second argument, but
280         // is fine if SP is the first argument. To be sure we
281         // do not generate invalid encoding, put BaseReg first.
282         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
283             .addReg(BaseReg)
284             .addReg(DestReg, RegState::Kill)
285             .add(predOps(Pred, PredReg))
286             .add(condCodeOp())
287             .setMIFlags(MIFlags);
288       }
289       return;
290     }
291   }
292 
293   while (NumBytes) {
294     unsigned ThisVal = NumBytes;
295     unsigned Opc = 0;
296     if (DestReg == ARM::SP && BaseReg != ARM::SP) {
297       // mov sp, rn. Note t2MOVr cannot be used.
298       BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
299           .addReg(BaseReg)
300           .setMIFlags(MIFlags)
301           .add(predOps(ARMCC::AL));
302       BaseReg = ARM::SP;
303       continue;
304     }
305 
306     bool HasCCOut = true;
307     if (BaseReg == ARM::SP) {
308       // sub sp, sp, #imm7
309       if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
310         assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
311         Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
312         BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
313             .addReg(BaseReg)
314             .addImm(ThisVal / 4)
315             .setMIFlags(MIFlags)
316             .add(predOps(ARMCC::AL));
317         NumBytes = 0;
318         continue;
319       }
320 
321       // sub rd, sp, so_imm
322       Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
323       if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
324         NumBytes = 0;
325       } else {
326         // FIXME: Move this to ARMAddressingModes.h?
327         unsigned RotAmt = countLeadingZeros(ThisVal);
328         ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
329         NumBytes &= ~ThisVal;
330         assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
331                "Bit extraction didn't work?");
332       }
333     } else {
334       assert(DestReg != ARM::SP && BaseReg != ARM::SP);
335       Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
336       if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
337         NumBytes = 0;
338       } else if (ThisVal < 4096) {
339         Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
340         HasCCOut = false;
341         NumBytes = 0;
342       } else {
343         // FIXME: Move this to ARMAddressingModes.h?
344         unsigned RotAmt = countLeadingZeros(ThisVal);
345         ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
346         NumBytes &= ~ThisVal;
347         assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
348                "Bit extraction didn't work?");
349       }
350     }
351 
352     // Build the new ADD / SUB.
353     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
354                                   .addReg(BaseReg, RegState::Kill)
355                                   .addImm(ThisVal)
356                                   .add(predOps(ARMCC::AL))
357                                   .setMIFlags(MIFlags);
358     if (HasCCOut)
359       MIB.add(condCodeOp());
360 
361     BaseReg = DestReg;
362   }
363 }
364 
365 static unsigned
366 negativeOffsetOpcode(unsigned opcode)
367 {
368   switch (opcode) {
369   case ARM::t2LDRi12:   return ARM::t2LDRi8;
370   case ARM::t2LDRHi12:  return ARM::t2LDRHi8;
371   case ARM::t2LDRBi12:  return ARM::t2LDRBi8;
372   case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
373   case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
374   case ARM::t2STRi12:   return ARM::t2STRi8;
375   case ARM::t2STRBi12:  return ARM::t2STRBi8;
376   case ARM::t2STRHi12:  return ARM::t2STRHi8;
377   case ARM::t2PLDi12:   return ARM::t2PLDi8;
378   case ARM::t2PLDWi12:  return ARM::t2PLDWi8;
379   case ARM::t2PLIi12:   return ARM::t2PLIi8;
380 
381   case ARM::t2LDRi8:
382   case ARM::t2LDRHi8:
383   case ARM::t2LDRBi8:
384   case ARM::t2LDRSHi8:
385   case ARM::t2LDRSBi8:
386   case ARM::t2STRi8:
387   case ARM::t2STRBi8:
388   case ARM::t2STRHi8:
389   case ARM::t2PLDi8:
390   case ARM::t2PLDWi8:
391   case ARM::t2PLIi8:
392     return opcode;
393 
394   default:
395     llvm_unreachable("unknown thumb2 opcode.");
396   }
397 }
398 
399 static unsigned
400 positiveOffsetOpcode(unsigned opcode)
401 {
402   switch (opcode) {
403   case ARM::t2LDRi8:   return ARM::t2LDRi12;
404   case ARM::t2LDRHi8:  return ARM::t2LDRHi12;
405   case ARM::t2LDRBi8:  return ARM::t2LDRBi12;
406   case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
407   case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
408   case ARM::t2STRi8:   return ARM::t2STRi12;
409   case ARM::t2STRBi8:  return ARM::t2STRBi12;
410   case ARM::t2STRHi8:  return ARM::t2STRHi12;
411   case ARM::t2PLDi8:   return ARM::t2PLDi12;
412   case ARM::t2PLDWi8:  return ARM::t2PLDWi12;
413   case ARM::t2PLIi8:   return ARM::t2PLIi12;
414 
415   case ARM::t2LDRi12:
416   case ARM::t2LDRHi12:
417   case ARM::t2LDRBi12:
418   case ARM::t2LDRSHi12:
419   case ARM::t2LDRSBi12:
420   case ARM::t2STRi12:
421   case ARM::t2STRBi12:
422   case ARM::t2STRHi12:
423   case ARM::t2PLDi12:
424   case ARM::t2PLDWi12:
425   case ARM::t2PLIi12:
426     return opcode;
427 
428   default:
429     llvm_unreachable("unknown thumb2 opcode.");
430   }
431 }
432 
433 static unsigned
434 immediateOffsetOpcode(unsigned opcode)
435 {
436   switch (opcode) {
437   case ARM::t2LDRs:   return ARM::t2LDRi12;
438   case ARM::t2LDRHs:  return ARM::t2LDRHi12;
439   case ARM::t2LDRBs:  return ARM::t2LDRBi12;
440   case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
441   case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
442   case ARM::t2STRs:   return ARM::t2STRi12;
443   case ARM::t2STRBs:  return ARM::t2STRBi12;
444   case ARM::t2STRHs:  return ARM::t2STRHi12;
445   case ARM::t2PLDs:   return ARM::t2PLDi12;
446   case ARM::t2PLDWs:  return ARM::t2PLDWi12;
447   case ARM::t2PLIs:   return ARM::t2PLIi12;
448 
449   case ARM::t2LDRi12:
450   case ARM::t2LDRHi12:
451   case ARM::t2LDRBi12:
452   case ARM::t2LDRSHi12:
453   case ARM::t2LDRSBi12:
454   case ARM::t2STRi12:
455   case ARM::t2STRBi12:
456   case ARM::t2STRHi12:
457   case ARM::t2PLDi12:
458   case ARM::t2PLDWi12:
459   case ARM::t2PLIi12:
460   case ARM::t2LDRi8:
461   case ARM::t2LDRHi8:
462   case ARM::t2LDRBi8:
463   case ARM::t2LDRSHi8:
464   case ARM::t2LDRSBi8:
465   case ARM::t2STRi8:
466   case ARM::t2STRBi8:
467   case ARM::t2STRHi8:
468   case ARM::t2PLDi8:
469   case ARM::t2PLDWi8:
470   case ARM::t2PLIi8:
471     return opcode;
472 
473   default:
474     llvm_unreachable("unknown thumb2 opcode.");
475   }
476 }
477 
478 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
479                                unsigned FrameReg, int &Offset,
480                                const ARMBaseInstrInfo &TII,
481                                const TargetRegisterInfo *TRI) {
482   unsigned Opcode = MI.getOpcode();
483   const MCInstrDesc &Desc = MI.getDesc();
484   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
485   bool isSub = false;
486 
487   MachineFunction &MF = *MI.getParent()->getParent();
488   const TargetRegisterClass *RegClass =
489       TII.getRegClass(Desc, FrameRegIdx, TRI, MF);
490 
491   // Memory operands in inline assembly always use AddrModeT2_i12.
492   if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR)
493     AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
494 
495   if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
496     Offset += MI.getOperand(FrameRegIdx+1).getImm();
497 
498     unsigned PredReg;
499     if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL &&
500         !MI.definesRegister(ARM::CPSR)) {
501       // Turn it into a move.
502       MI.setDesc(TII.get(ARM::tMOVr));
503       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
504       // Remove offset and remaining explicit predicate operands.
505       do MI.RemoveOperand(FrameRegIdx+1);
506       while (MI.getNumOperands() > FrameRegIdx+1);
507       MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
508       MIB.add(predOps(ARMCC::AL));
509       return true;
510     }
511 
512     bool HasCCOut = Opcode != ARM::t2ADDri12;
513 
514     if (Offset < 0) {
515       Offset = -Offset;
516       isSub = true;
517       MI.setDesc(TII.get(ARM::t2SUBri));
518     } else {
519       MI.setDesc(TII.get(ARM::t2ADDri));
520     }
521 
522     // Common case: small offset, fits into instruction.
523     if (ARM_AM::getT2SOImmVal(Offset) != -1) {
524       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
525       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
526       // Add cc_out operand if the original instruction did not have one.
527       if (!HasCCOut)
528         MI.addOperand(MachineOperand::CreateReg(0, false));
529       Offset = 0;
530       return true;
531     }
532     // Another common case: imm12.
533     if (Offset < 4096 &&
534         (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
535       unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
536       MI.setDesc(TII.get(NewOpc));
537       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
538       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
539       // Remove the cc_out operand.
540       if (HasCCOut)
541         MI.RemoveOperand(MI.getNumOperands()-1);
542       Offset = 0;
543       return true;
544     }
545 
546     // Otherwise, extract 8 adjacent bits from the immediate into this
547     // t2ADDri/t2SUBri.
548     unsigned RotAmt = countLeadingZeros<unsigned>(Offset);
549     unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
550 
551     // We will handle these bits from offset, clear them.
552     Offset &= ~ThisImmVal;
553 
554     assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
555            "Bit extraction didn't work?");
556     MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
557     // Add cc_out operand if the original instruction did not have one.
558     if (!HasCCOut)
559       MI.addOperand(MachineOperand::CreateReg(0, false));
560   } else {
561     // AddrMode4 and AddrMode6 cannot handle any offset.
562     if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
563       return false;
564 
565     // AddrModeT2_so cannot handle any offset. If there is no offset
566     // register then we change to an immediate version.
567     unsigned NewOpc = Opcode;
568     if (AddrMode == ARMII::AddrModeT2_so) {
569       Register OffsetReg = MI.getOperand(FrameRegIdx + 1).getReg();
570       if (OffsetReg != 0) {
571         MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
572         return Offset == 0;
573       }
574 
575       MI.RemoveOperand(FrameRegIdx+1);
576       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
577       NewOpc = immediateOffsetOpcode(Opcode);
578       AddrMode = ARMII::AddrModeT2_i12;
579     }
580 
581     unsigned NumBits = 0;
582     unsigned Scale = 1;
583     if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
584       // i8 supports only negative, and i12 supports only positive, so
585       // based on Offset sign convert Opcode to the appropriate
586       // instruction
587       Offset += MI.getOperand(FrameRegIdx+1).getImm();
588       if (Offset < 0) {
589         NewOpc = negativeOffsetOpcode(Opcode);
590         NumBits = 8;
591         isSub = true;
592         Offset = -Offset;
593       } else {
594         NewOpc = positiveOffsetOpcode(Opcode);
595         NumBits = 12;
596       }
597     } else if (AddrMode == ARMII::AddrMode5) {
598       // VFP address mode.
599       const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
600       int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
601       if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
602         InstrOffs *= -1;
603       NumBits = 8;
604       Scale = 4;
605       Offset += InstrOffs * 4;
606       assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
607       if (Offset < 0) {
608         Offset = -Offset;
609         isSub = true;
610       }
611     } else if (AddrMode == ARMII::AddrMode5FP16) {
612       // VFP address mode.
613       const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
614       int InstrOffs = ARM_AM::getAM5FP16Offset(OffOp.getImm());
615       if (ARM_AM::getAM5FP16Op(OffOp.getImm()) == ARM_AM::sub)
616         InstrOffs *= -1;
617       NumBits = 8;
618       Scale = 2;
619       Offset += InstrOffs * 2;
620       assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
621       if (Offset < 0) {
622         Offset = -Offset;
623         isSub = true;
624       }
625     } else if (AddrMode == ARMII::AddrModeT2_i7s4 ||
626                AddrMode == ARMII::AddrModeT2_i7s2 ||
627                AddrMode == ARMII::AddrModeT2_i7) {
628       Offset += MI.getOperand(FrameRegIdx + 1).getImm();
629       unsigned OffsetMask;
630       switch (AddrMode) {
631       case ARMII::AddrModeT2_i7s4: NumBits = 9; OffsetMask = 0x3; break;
632       case ARMII::AddrModeT2_i7s2: NumBits = 8; OffsetMask = 0x1; break;
633       default:                     NumBits = 7; OffsetMask = 0x0; break;
634       }
635       // MCInst operand expects already scaled value.
636       Scale = 1;
637       assert((Offset & OffsetMask) == 0 && "Can't encode this offset!");
638       (void)OffsetMask; // squash unused-variable warning at -NDEBUG
639     } else if (AddrMode == ARMII::AddrModeT2_i8s4) {
640       Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
641       NumBits = 8 + 2;
642       // MCInst operand expects already scaled value.
643       Scale = 1;
644       assert((Offset & 3) == 0 && "Can't encode this offset!");
645     } else if (AddrMode == ARMII::AddrModeT2_ldrex) {
646       Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
647       NumBits = 8; // 8 bits scaled by 4
648       Scale = 4;
649       assert((Offset & 3) == 0 && "Can't encode this offset!");
650     } else {
651       llvm_unreachable("Unsupported addressing mode!");
652     }
653 
654     if (NewOpc != Opcode)
655       MI.setDesc(TII.get(NewOpc));
656 
657     MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
658 
659     // Attempt to fold address computation
660     // Common case: small offset, fits into instruction. We need to make sure
661     // the register class is correct too, for instructions like the MVE
662     // VLDRH.32, which only accepts low tGPR registers.
663     int ImmedOffset = Offset / Scale;
664     unsigned Mask = (1 << NumBits) - 1;
665     if ((unsigned)Offset <= Mask * Scale &&
666         (Register::isVirtualRegister(FrameReg) ||
667          RegClass->contains(FrameReg))) {
668       if (Register::isVirtualRegister(FrameReg)) {
669         // Make sure the register class for the virtual register is correct
670         MachineRegisterInfo *MRI = &MF.getRegInfo();
671         if (!MRI->constrainRegClass(FrameReg, RegClass))
672           llvm_unreachable("Unable to constrain virtual register class.");
673       }
674 
675       // Replace the FrameIndex with fp/sp
676       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
677       if (isSub) {
678         if (AddrMode == ARMII::AddrMode5 || AddrMode == ARMII::AddrMode5FP16)
679           // FIXME: Not consistent.
680           ImmedOffset |= 1 << NumBits;
681         else
682           ImmedOffset = -ImmedOffset;
683       }
684       ImmOp.ChangeToImmediate(ImmedOffset);
685       Offset = 0;
686       return true;
687     }
688 
689     // Otherwise, offset doesn't fit. Pull in what we can to simplify
690     ImmedOffset = ImmedOffset & Mask;
691     if (isSub) {
692       if (AddrMode == ARMII::AddrMode5 || AddrMode == ARMII::AddrMode5FP16)
693         // FIXME: Not consistent.
694         ImmedOffset |= 1 << NumBits;
695       else {
696         ImmedOffset = -ImmedOffset;
697         if (ImmedOffset == 0)
698           // Change the opcode back if the encoded offset is zero.
699           MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
700       }
701     }
702     ImmOp.ChangeToImmediate(ImmedOffset);
703     Offset &= ~(Mask*Scale);
704   }
705 
706   Offset = (isSub) ? -Offset : Offset;
707   return Offset == 0 && (Register::isVirtualRegister(FrameReg) ||
708                          RegClass->contains(FrameReg));
709 }
710 
711 ARMCC::CondCodes llvm::getITInstrPredicate(const MachineInstr &MI,
712                                            unsigned &PredReg) {
713   unsigned Opc = MI.getOpcode();
714   if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
715     return ARMCC::AL;
716   return getInstrPredicate(MI, PredReg);
717 }
718 
719 int llvm::findFirstVPTPredOperandIdx(const MachineInstr &MI) {
720   const MCInstrDesc &MCID = MI.getDesc();
721 
722   if (!MCID.OpInfo)
723     return -1;
724 
725   for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
726     if (ARM::isVpred(MCID.OpInfo[i].OperandType))
727       return i;
728 
729   return -1;
730 }
731 
732 ARMVCC::VPTCodes llvm::getVPTInstrPredicate(const MachineInstr &MI,
733                                             unsigned &PredReg) {
734   int PIdx = findFirstVPTPredOperandIdx(MI);
735   if (PIdx == -1) {
736     PredReg = 0;
737     return ARMVCC::None;
738   }
739 
740   PredReg = MI.getOperand(PIdx+1).getReg();
741   return (ARMVCC::VPTCodes)MI.getOperand(PIdx).getImm();
742 }
743