1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information --------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "Thumb2InstrInfo.h"
14 #include "ARMMachineFunctionInfo.h"
15 #include "ARMSubtarget.h"
16 #include "MCTargetDesc/ARMAddressingModes.h"
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/TargetRegisterInfo.h"
26 #include "llvm/IR/DebugLoc.h"
27 #include "llvm/MC/MCInst.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include <cassert>
34 
35 using namespace llvm;
36 
37 static cl::opt<bool>
38 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
39            cl::desc("Use old-style Thumb2 if-conversion heuristics"),
40            cl::init(false));
41 
42 static cl::opt<bool>
43 PreferNoCSEL("prefer-no-csel", cl::Hidden,
44              cl::desc("Prefer predicated Move to CSEL"),
45              cl::init(false));
46 
47 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
48     : ARMBaseInstrInfo(STI) {}
49 
50 /// Return the noop instruction to use for a noop.
51 void Thumb2InstrInfo::getNoop(MCInst &NopInst) const {
52   NopInst.setOpcode(ARM::tHINT);
53   NopInst.addOperand(MCOperand::createImm(0));
54   NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
55   NopInst.addOperand(MCOperand::createReg(0));
56 }
57 
58 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
59   // FIXME
60   return 0;
61 }
62 
63 void
64 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
65                                          MachineBasicBlock *NewDest) const {
66   MachineBasicBlock *MBB = Tail->getParent();
67   ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
68   if (!AFI->hasITBlocks() || Tail->isBranch()) {
69     TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
70     return;
71   }
72 
73   // If the first instruction of Tail is predicated, we may have to update
74   // the IT instruction.
75   Register PredReg;
76   ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg);
77   MachineBasicBlock::iterator MBBI = Tail;
78   if (CC != ARMCC::AL)
79     // Expecting at least the t2IT instruction before it.
80     --MBBI;
81 
82   // Actually replace the tail.
83   TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
84 
85   // Fix up IT.
86   if (CC != ARMCC::AL) {
87     MachineBasicBlock::iterator E = MBB->begin();
88     unsigned Count = 4; // At most 4 instructions in an IT block.
89     while (Count && MBBI != E) {
90       if (MBBI->isDebugInstr()) {
91         --MBBI;
92         continue;
93       }
94       if (MBBI->getOpcode() == ARM::t2IT) {
95         unsigned Mask = MBBI->getOperand(1).getImm();
96         if (Count == 4)
97           MBBI->eraseFromParent();
98         else {
99           unsigned MaskOn = 1 << Count;
100           unsigned MaskOff = ~(MaskOn - 1);
101           MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
102         }
103         return;
104       }
105       --MBBI;
106       --Count;
107     }
108 
109     // Ctrl flow can reach here if branch folding is run before IT block
110     // formation pass.
111   }
112 }
113 
114 bool
115 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
116                                      MachineBasicBlock::iterator MBBI) const {
117   while (MBBI->isDebugInstr()) {
118     ++MBBI;
119     if (MBBI == MBB.end())
120       return false;
121   }
122 
123   Register PredReg;
124   return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL;
125 }
126 
127 MachineInstr *
128 Thumb2InstrInfo::optimizeSelect(MachineInstr &MI,
129                                 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
130                                 bool PreferFalse) const {
131   // Try to use the base optimizeSelect, which uses canFoldIntoMOVCC to fold the
132   // MOVCC into another instruction. If that fails on 8.1-M fall back to using a
133   // CSEL.
134   MachineInstr *RV = ARMBaseInstrInfo::optimizeSelect(MI, SeenMIs, PreferFalse);
135   if (!RV && getSubtarget().hasV8_1MMainlineOps() && !PreferNoCSEL) {
136     Register DestReg = MI.getOperand(0).getReg();
137 
138     if (!DestReg.isVirtual())
139       return nullptr;
140 
141     MachineInstrBuilder NewMI = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
142                                         get(ARM::t2CSEL), DestReg)
143                                     .add(MI.getOperand(2))
144                                     .add(MI.getOperand(1))
145                                     .add(MI.getOperand(3));
146     SeenMIs.insert(NewMI);
147     return NewMI;
148   }
149   return RV;
150 }
151 
152 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
153                                   MachineBasicBlock::iterator I,
154                                   const DebugLoc &DL, MCRegister DestReg,
155                                   MCRegister SrcReg, bool KillSrc) const {
156   // Handle SPR, DPR, and QPR copies.
157   if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
158     return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
159 
160   BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
161       .addReg(SrcReg, getKillRegState(KillSrc))
162       .add(predOps(ARMCC::AL));
163 }
164 
165 void Thumb2InstrInfo::
166 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
167                     Register SrcReg, bool isKill, int FI,
168                     const TargetRegisterClass *RC,
169                     const TargetRegisterInfo *TRI) const {
170   DebugLoc DL;
171   if (I != MBB.end()) DL = I->getDebugLoc();
172 
173   MachineFunction &MF = *MBB.getParent();
174   MachineFrameInfo &MFI = MF.getFrameInfo();
175   MachineMemOperand *MMO = MF.getMachineMemOperand(
176       MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
177       MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
178 
179   if (ARM::GPRRegClass.hasSubClassEq(RC)) {
180     BuildMI(MBB, I, DL, get(ARM::t2STRi12))
181         .addReg(SrcReg, getKillRegState(isKill))
182         .addFrameIndex(FI)
183         .addImm(0)
184         .addMemOperand(MMO)
185         .add(predOps(ARMCC::AL));
186     return;
187   }
188 
189   if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
190     // Thumb2 STRD expects its dest-registers to be in rGPR. Not a problem for
191     // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
192     // otherwise).
193     if (Register::isVirtualRegister(SrcReg)) {
194       MachineRegisterInfo *MRI = &MF.getRegInfo();
195       MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass);
196     }
197 
198     MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
199     AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
200     AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
201     MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO).add(predOps(ARMCC::AL));
202     return;
203   }
204 
205   ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
206 }
207 
208 void Thumb2InstrInfo::
209 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
210                      Register DestReg, int FI,
211                      const TargetRegisterClass *RC,
212                      const TargetRegisterInfo *TRI) const {
213   MachineFunction &MF = *MBB.getParent();
214   MachineFrameInfo &MFI = MF.getFrameInfo();
215   MachineMemOperand *MMO = MF.getMachineMemOperand(
216       MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
217       MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
218   DebugLoc DL;
219   if (I != MBB.end()) DL = I->getDebugLoc();
220 
221   if (ARM::GPRRegClass.hasSubClassEq(RC)) {
222     BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
223         .addFrameIndex(FI)
224         .addImm(0)
225         .addMemOperand(MMO)
226         .add(predOps(ARMCC::AL));
227     return;
228   }
229 
230   if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
231     // Thumb2 LDRD expects its dest-registers to be in rGPR. Not a problem for
232     // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
233     // otherwise).
234     if (Register::isVirtualRegister(DestReg)) {
235       MachineRegisterInfo *MRI = &MF.getRegInfo();
236       MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass);
237     }
238 
239     MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
240     AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
241     AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
242     MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO).add(predOps(ARMCC::AL));
243 
244     if (Register::isPhysicalRegister(DestReg))
245       MIB.addReg(DestReg, RegState::ImplicitDefine);
246     return;
247   }
248 
249   ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
250 }
251 
252 void Thumb2InstrInfo::expandLoadStackGuard(
253     MachineBasicBlock::iterator MI) const {
254   MachineFunction &MF = *MI->getParent()->getParent();
255   if (MF.getTarget().isPositionIndependent())
256     expandLoadStackGuardBase(MI, ARM::t2MOV_ga_pcrel, ARM::t2LDRi12);
257   else
258     expandLoadStackGuardBase(MI, ARM::t2MOVi32imm, ARM::t2LDRi12);
259 }
260 
261 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
262                                   MachineBasicBlock::iterator &MBBI,
263                                   const DebugLoc &dl, Register DestReg,
264                                   Register BaseReg, int NumBytes,
265                                   ARMCC::CondCodes Pred, Register PredReg,
266                                   const ARMBaseInstrInfo &TII,
267                                   unsigned MIFlags) {
268   if (NumBytes == 0 && DestReg != BaseReg) {
269     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
270       .addReg(BaseReg, RegState::Kill)
271       .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
272     return;
273   }
274 
275   bool isSub = NumBytes < 0;
276   if (isSub) NumBytes = -NumBytes;
277 
278   // If profitable, use a movw or movt to materialize the offset.
279   // FIXME: Use the scavenger to grab a scratch register.
280   if (DestReg != ARM::SP && DestReg != BaseReg &&
281       NumBytes >= 4096 &&
282       ARM_AM::getT2SOImmVal(NumBytes) == -1) {
283     bool Fits = false;
284     if (NumBytes < 65536) {
285       // Use a movw to materialize the 16-bit constant.
286       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
287         .addImm(NumBytes)
288         .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
289       Fits = true;
290     } else if ((NumBytes & 0xffff) == 0) {
291       // Use a movt to materialize the 32-bit constant.
292       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
293         .addReg(DestReg)
294         .addImm(NumBytes >> 16)
295         .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
296       Fits = true;
297     }
298 
299     if (Fits) {
300       if (isSub) {
301         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
302             .addReg(BaseReg)
303             .addReg(DestReg, RegState::Kill)
304             .add(predOps(Pred, PredReg))
305             .add(condCodeOp())
306             .setMIFlags(MIFlags);
307       } else {
308         // Here we know that DestReg is not SP but we do not
309         // know anything about BaseReg. t2ADDrr is an invalid
310         // instruction is SP is used as the second argument, but
311         // is fine if SP is the first argument. To be sure we
312         // do not generate invalid encoding, put BaseReg first.
313         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
314             .addReg(BaseReg)
315             .addReg(DestReg, RegState::Kill)
316             .add(predOps(Pred, PredReg))
317             .add(condCodeOp())
318             .setMIFlags(MIFlags);
319       }
320       return;
321     }
322   }
323 
324   while (NumBytes) {
325     unsigned ThisVal = NumBytes;
326     unsigned Opc = 0;
327     if (DestReg == ARM::SP && BaseReg != ARM::SP) {
328       // mov sp, rn. Note t2MOVr cannot be used.
329       BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
330           .addReg(BaseReg)
331           .setMIFlags(MIFlags)
332           .add(predOps(ARMCC::AL));
333       BaseReg = ARM::SP;
334       continue;
335     }
336 
337     assert((DestReg != ARM::SP || BaseReg == ARM::SP) &&
338            "Writing to SP, from other register.");
339 
340     // Try to use T1, as it smaller
341     if ((DestReg == ARM::SP) && (ThisVal < ((1 << 7) - 1) * 4)) {
342       assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
343       Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
344       BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
345           .addReg(BaseReg)
346           .addImm(ThisVal / 4)
347           .setMIFlags(MIFlags)
348           .add(predOps(ARMCC::AL));
349       break;
350     }
351     bool HasCCOut = true;
352     int ImmIsT2SO = ARM_AM::getT2SOImmVal(ThisVal);
353     bool ToSP = DestReg == ARM::SP;
354     unsigned t2SUB = ToSP ? ARM::t2SUBspImm : ARM::t2SUBri;
355     unsigned t2ADD = ToSP ? ARM::t2ADDspImm : ARM::t2ADDri;
356     unsigned t2SUBi12 = ToSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12;
357     unsigned t2ADDi12 = ToSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12;
358     Opc = isSub ? t2SUB : t2ADD;
359     // Prefer T2: sub rd, rn, so_imm | sub sp, sp, so_imm
360     if (ImmIsT2SO != -1) {
361       NumBytes = 0;
362     } else if (ThisVal < 4096) {
363       // Prefer T3 if can make it in a single go: subw rd, rn, imm12 | subw sp,
364       // sp, imm12
365       Opc = isSub ? t2SUBi12 : t2ADDi12;
366       HasCCOut = false;
367       NumBytes = 0;
368     } else {
369       // Use one T2 instruction to reduce NumBytes
370       // FIXME: Move this to ARMAddressingModes.h?
371       unsigned RotAmt = countLeadingZeros(ThisVal);
372       ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
373       NumBytes &= ~ThisVal;
374       assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
375              "Bit extraction didn't work?");
376     }
377 
378     // Build the new ADD / SUB.
379     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
380                                   .addReg(BaseReg, RegState::Kill)
381                                   .addImm(ThisVal)
382                                   .add(predOps(ARMCC::AL))
383                                   .setMIFlags(MIFlags);
384     if (HasCCOut)
385       MIB.add(condCodeOp());
386 
387     BaseReg = DestReg;
388   }
389 }
390 
391 static unsigned
392 negativeOffsetOpcode(unsigned opcode)
393 {
394   switch (opcode) {
395   case ARM::t2LDRi12:   return ARM::t2LDRi8;
396   case ARM::t2LDRHi12:  return ARM::t2LDRHi8;
397   case ARM::t2LDRBi12:  return ARM::t2LDRBi8;
398   case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
399   case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
400   case ARM::t2STRi12:   return ARM::t2STRi8;
401   case ARM::t2STRBi12:  return ARM::t2STRBi8;
402   case ARM::t2STRHi12:  return ARM::t2STRHi8;
403   case ARM::t2PLDi12:   return ARM::t2PLDi8;
404   case ARM::t2PLDWi12:  return ARM::t2PLDWi8;
405   case ARM::t2PLIi12:   return ARM::t2PLIi8;
406 
407   case ARM::t2LDRi8:
408   case ARM::t2LDRHi8:
409   case ARM::t2LDRBi8:
410   case ARM::t2LDRSHi8:
411   case ARM::t2LDRSBi8:
412   case ARM::t2STRi8:
413   case ARM::t2STRBi8:
414   case ARM::t2STRHi8:
415   case ARM::t2PLDi8:
416   case ARM::t2PLDWi8:
417   case ARM::t2PLIi8:
418     return opcode;
419 
420   default:
421     llvm_unreachable("unknown thumb2 opcode.");
422   }
423 }
424 
425 static unsigned
426 positiveOffsetOpcode(unsigned opcode)
427 {
428   switch (opcode) {
429   case ARM::t2LDRi8:   return ARM::t2LDRi12;
430   case ARM::t2LDRHi8:  return ARM::t2LDRHi12;
431   case ARM::t2LDRBi8:  return ARM::t2LDRBi12;
432   case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
433   case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
434   case ARM::t2STRi8:   return ARM::t2STRi12;
435   case ARM::t2STRBi8:  return ARM::t2STRBi12;
436   case ARM::t2STRHi8:  return ARM::t2STRHi12;
437   case ARM::t2PLDi8:   return ARM::t2PLDi12;
438   case ARM::t2PLDWi8:  return ARM::t2PLDWi12;
439   case ARM::t2PLIi8:   return ARM::t2PLIi12;
440 
441   case ARM::t2LDRi12:
442   case ARM::t2LDRHi12:
443   case ARM::t2LDRBi12:
444   case ARM::t2LDRSHi12:
445   case ARM::t2LDRSBi12:
446   case ARM::t2STRi12:
447   case ARM::t2STRBi12:
448   case ARM::t2STRHi12:
449   case ARM::t2PLDi12:
450   case ARM::t2PLDWi12:
451   case ARM::t2PLIi12:
452     return opcode;
453 
454   default:
455     llvm_unreachable("unknown thumb2 opcode.");
456   }
457 }
458 
459 static unsigned
460 immediateOffsetOpcode(unsigned opcode)
461 {
462   switch (opcode) {
463   case ARM::t2LDRs:   return ARM::t2LDRi12;
464   case ARM::t2LDRHs:  return ARM::t2LDRHi12;
465   case ARM::t2LDRBs:  return ARM::t2LDRBi12;
466   case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
467   case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
468   case ARM::t2STRs:   return ARM::t2STRi12;
469   case ARM::t2STRBs:  return ARM::t2STRBi12;
470   case ARM::t2STRHs:  return ARM::t2STRHi12;
471   case ARM::t2PLDs:   return ARM::t2PLDi12;
472   case ARM::t2PLDWs:  return ARM::t2PLDWi12;
473   case ARM::t2PLIs:   return ARM::t2PLIi12;
474 
475   case ARM::t2LDRi12:
476   case ARM::t2LDRHi12:
477   case ARM::t2LDRBi12:
478   case ARM::t2LDRSHi12:
479   case ARM::t2LDRSBi12:
480   case ARM::t2STRi12:
481   case ARM::t2STRBi12:
482   case ARM::t2STRHi12:
483   case ARM::t2PLDi12:
484   case ARM::t2PLDWi12:
485   case ARM::t2PLIi12:
486   case ARM::t2LDRi8:
487   case ARM::t2LDRHi8:
488   case ARM::t2LDRBi8:
489   case ARM::t2LDRSHi8:
490   case ARM::t2LDRSBi8:
491   case ARM::t2STRi8:
492   case ARM::t2STRBi8:
493   case ARM::t2STRHi8:
494   case ARM::t2PLDi8:
495   case ARM::t2PLDWi8:
496   case ARM::t2PLIi8:
497     return opcode;
498 
499   default:
500     llvm_unreachable("unknown thumb2 opcode.");
501   }
502 }
503 
504 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
505                                Register FrameReg, int &Offset,
506                                const ARMBaseInstrInfo &TII,
507                                const TargetRegisterInfo *TRI) {
508   unsigned Opcode = MI.getOpcode();
509   const MCInstrDesc &Desc = MI.getDesc();
510   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
511   bool isSub = false;
512 
513   MachineFunction &MF = *MI.getParent()->getParent();
514   const TargetRegisterClass *RegClass =
515       TII.getRegClass(Desc, FrameRegIdx, TRI, MF);
516 
517   // Memory operands in inline assembly always use AddrModeT2_i12.
518   if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR)
519     AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
520 
521   const bool IsSP = Opcode == ARM::t2ADDspImm12 || Opcode == ARM::t2ADDspImm;
522   if (IsSP || Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
523     Offset += MI.getOperand(FrameRegIdx+1).getImm();
524 
525     Register PredReg;
526     if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL &&
527         !MI.definesRegister(ARM::CPSR)) {
528       // Turn it into a move.
529       MI.setDesc(TII.get(ARM::tMOVr));
530       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
531       // Remove offset and remaining explicit predicate operands.
532       do MI.RemoveOperand(FrameRegIdx+1);
533       while (MI.getNumOperands() > FrameRegIdx+1);
534       MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
535       MIB.add(predOps(ARMCC::AL));
536       return true;
537     }
538 
539     bool HasCCOut = (Opcode != ARM::t2ADDspImm12 && Opcode != ARM::t2ADDri12);
540 
541     if (Offset < 0) {
542       Offset = -Offset;
543       isSub = true;
544       MI.setDesc(IsSP ? TII.get(ARM::t2SUBspImm) : TII.get(ARM::t2SUBri));
545     } else {
546       MI.setDesc(IsSP ? TII.get(ARM::t2ADDspImm) : TII.get(ARM::t2ADDri));
547     }
548 
549     // Common case: small offset, fits into instruction.
550     if (ARM_AM::getT2SOImmVal(Offset) != -1) {
551       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
552       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
553       // Add cc_out operand if the original instruction did not have one.
554       if (!HasCCOut)
555         MI.addOperand(MachineOperand::CreateReg(0, false));
556       Offset = 0;
557       return true;
558     }
559     // Another common case: imm12.
560     if (Offset < 4096 &&
561         (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
562       unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12
563                               : IsSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12;
564       MI.setDesc(TII.get(NewOpc));
565       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
566       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
567       // Remove the cc_out operand.
568       if (HasCCOut)
569         MI.RemoveOperand(MI.getNumOperands()-1);
570       Offset = 0;
571       return true;
572     }
573 
574     // Otherwise, extract 8 adjacent bits from the immediate into this
575     // t2ADDri/t2SUBri.
576     unsigned RotAmt = countLeadingZeros<unsigned>(Offset);
577     unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
578 
579     // We will handle these bits from offset, clear them.
580     Offset &= ~ThisImmVal;
581 
582     assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
583            "Bit extraction didn't work?");
584     MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
585     // Add cc_out operand if the original instruction did not have one.
586     if (!HasCCOut)
587       MI.addOperand(MachineOperand::CreateReg(0, false));
588   } else {
589     // AddrMode4 and AddrMode6 cannot handle any offset.
590     if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
591       return false;
592 
593     // AddrModeT2_so cannot handle any offset. If there is no offset
594     // register then we change to an immediate version.
595     unsigned NewOpc = Opcode;
596     if (AddrMode == ARMII::AddrModeT2_so) {
597       Register OffsetReg = MI.getOperand(FrameRegIdx + 1).getReg();
598       if (OffsetReg != 0) {
599         MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
600         return Offset == 0;
601       }
602 
603       MI.RemoveOperand(FrameRegIdx+1);
604       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
605       NewOpc = immediateOffsetOpcode(Opcode);
606       AddrMode = ARMII::AddrModeT2_i12;
607     }
608 
609     unsigned NumBits = 0;
610     unsigned Scale = 1;
611     if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
612       // i8 supports only negative, and i12 supports only positive, so
613       // based on Offset sign convert Opcode to the appropriate
614       // instruction
615       Offset += MI.getOperand(FrameRegIdx+1).getImm();
616       if (Offset < 0) {
617         NewOpc = negativeOffsetOpcode(Opcode);
618         NumBits = 8;
619         isSub = true;
620         Offset = -Offset;
621       } else {
622         NewOpc = positiveOffsetOpcode(Opcode);
623         NumBits = 12;
624       }
625     } else if (AddrMode == ARMII::AddrMode5) {
626       // VFP address mode.
627       const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
628       int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
629       if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
630         InstrOffs *= -1;
631       NumBits = 8;
632       Scale = 4;
633       Offset += InstrOffs * 4;
634       assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
635       if (Offset < 0) {
636         Offset = -Offset;
637         isSub = true;
638       }
639     } else if (AddrMode == ARMII::AddrMode5FP16) {
640       // VFP address mode.
641       const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
642       int InstrOffs = ARM_AM::getAM5FP16Offset(OffOp.getImm());
643       if (ARM_AM::getAM5FP16Op(OffOp.getImm()) == ARM_AM::sub)
644         InstrOffs *= -1;
645       NumBits = 8;
646       Scale = 2;
647       Offset += InstrOffs * 2;
648       assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
649       if (Offset < 0) {
650         Offset = -Offset;
651         isSub = true;
652       }
653     } else if (AddrMode == ARMII::AddrModeT2_i7s4 ||
654                AddrMode == ARMII::AddrModeT2_i7s2 ||
655                AddrMode == ARMII::AddrModeT2_i7) {
656       Offset += MI.getOperand(FrameRegIdx + 1).getImm();
657       unsigned OffsetMask;
658       switch (AddrMode) {
659       case ARMII::AddrModeT2_i7s4: NumBits = 9; OffsetMask = 0x3; break;
660       case ARMII::AddrModeT2_i7s2: NumBits = 8; OffsetMask = 0x1; break;
661       default:                     NumBits = 7; OffsetMask = 0x0; break;
662       }
663       // MCInst operand expects already scaled value.
664       Scale = 1;
665       assert((Offset & OffsetMask) == 0 && "Can't encode this offset!");
666       (void)OffsetMask; // squash unused-variable warning at -NDEBUG
667     } else if (AddrMode == ARMII::AddrModeT2_i8s4) {
668       Offset += MI.getOperand(FrameRegIdx + 1).getImm();
669       NumBits = 8 + 2;
670       // MCInst operand expects already scaled value.
671       Scale = 1;
672       assert((Offset & 3) == 0 && "Can't encode this offset!");
673     } else if (AddrMode == ARMII::AddrModeT2_ldrex) {
674       Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
675       NumBits = 8; // 8 bits scaled by 4
676       Scale = 4;
677       assert((Offset & 3) == 0 && "Can't encode this offset!");
678     } else {
679       llvm_unreachable("Unsupported addressing mode!");
680     }
681 
682     if (NewOpc != Opcode)
683       MI.setDesc(TII.get(NewOpc));
684 
685     MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
686 
687     // Attempt to fold address computation
688     // Common case: small offset, fits into instruction. We need to make sure
689     // the register class is correct too, for instructions like the MVE
690     // VLDRH.32, which only accepts low tGPR registers.
691     int ImmedOffset = Offset / Scale;
692     unsigned Mask = (1 << NumBits) - 1;
693     if ((unsigned)Offset <= Mask * Scale &&
694         (Register::isVirtualRegister(FrameReg) ||
695          RegClass->contains(FrameReg))) {
696       if (Register::isVirtualRegister(FrameReg)) {
697         // Make sure the register class for the virtual register is correct
698         MachineRegisterInfo *MRI = &MF.getRegInfo();
699         if (!MRI->constrainRegClass(FrameReg, RegClass))
700           llvm_unreachable("Unable to constrain virtual register class.");
701       }
702 
703       // Replace the FrameIndex with fp/sp
704       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
705       if (isSub) {
706         if (AddrMode == ARMII::AddrMode5 || AddrMode == ARMII::AddrMode5FP16)
707           // FIXME: Not consistent.
708           ImmedOffset |= 1 << NumBits;
709         else
710           ImmedOffset = -ImmedOffset;
711       }
712       ImmOp.ChangeToImmediate(ImmedOffset);
713       Offset = 0;
714       return true;
715     }
716 
717     // Otherwise, offset doesn't fit. Pull in what we can to simplify
718     ImmedOffset = ImmedOffset & Mask;
719     if (isSub) {
720       if (AddrMode == ARMII::AddrMode5 || AddrMode == ARMII::AddrMode5FP16)
721         // FIXME: Not consistent.
722         ImmedOffset |= 1 << NumBits;
723       else {
724         ImmedOffset = -ImmedOffset;
725         if (ImmedOffset == 0)
726           // Change the opcode back if the encoded offset is zero.
727           MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
728       }
729     }
730     ImmOp.ChangeToImmediate(ImmedOffset);
731     Offset &= ~(Mask*Scale);
732   }
733 
734   Offset = (isSub) ? -Offset : Offset;
735   return Offset == 0 && (Register::isVirtualRegister(FrameReg) ||
736                          RegClass->contains(FrameReg));
737 }
738 
739 ARMCC::CondCodes llvm::getITInstrPredicate(const MachineInstr &MI,
740                                            Register &PredReg) {
741   unsigned Opc = MI.getOpcode();
742   if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
743     return ARMCC::AL;
744   return getInstrPredicate(MI, PredReg);
745 }
746 
747 int llvm::findFirstVPTPredOperandIdx(const MachineInstr &MI) {
748   const MCInstrDesc &MCID = MI.getDesc();
749 
750   if (!MCID.OpInfo)
751     return -1;
752 
753   for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
754     if (ARM::isVpred(MCID.OpInfo[i].OperandType))
755       return i;
756 
757   return -1;
758 }
759 
760 ARMVCC::VPTCodes llvm::getVPTInstrPredicate(const MachineInstr &MI,
761                                             Register &PredReg) {
762   int PIdx = findFirstVPTPredOperandIdx(MI);
763   if (PIdx == -1) {
764     PredReg = 0;
765     return ARMVCC::None;
766   }
767 
768   PredReg = MI.getOperand(PIdx+1).getReg();
769   return (ARMVCC::VPTCodes)MI.getOperand(PIdx).getImm();
770 }
771 
772 void llvm::recomputeVPTBlockMask(MachineInstr &Instr) {
773   assert(isVPTOpcode(Instr.getOpcode()) && "Not a VPST or VPT Instruction!");
774 
775   MachineOperand &MaskOp = Instr.getOperand(0);
776   assert(MaskOp.isImm() && "Operand 0 is not the block mask of the VPT/VPST?!");
777 
778   MachineBasicBlock::iterator Iter = ++Instr.getIterator(),
779                               End = Instr.getParent()->end();
780 
781   // Verify that the instruction after the VPT/VPST is predicated (it should
782   // be), and skip it.
783   assert(
784       getVPTInstrPredicate(*Iter) == ARMVCC::Then &&
785       "VPT/VPST should be followed by an instruction with a 'then' predicate!");
786   ++Iter;
787 
788   // Iterate over the predicated instructions, updating the BlockMask as we go.
789   ARM::PredBlockMask BlockMask = ARM::PredBlockMask::T;
790   while (Iter != End) {
791     ARMVCC::VPTCodes Pred = getVPTInstrPredicate(*Iter);
792     if (Pred == ARMVCC::None)
793       break;
794     BlockMask = expandPredBlockMask(BlockMask, Pred);
795     ++Iter;
796   }
797 
798   // Rewrite the BlockMask.
799   MaskOp.setImm((int64_t)(BlockMask));
800 }
801