1 //===-- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information -------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Thumb2InstrInfo.h"
15 #include "ARM.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "MCTargetDesc/ARMAddressingModes.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/Support/CommandLine.h"
25 
26 using namespace llvm;
27 
28 static cl::opt<bool>
29 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
30            cl::desc("Use old-style Thumb2 if-conversion heuristics"),
31            cl::init(false));
32 
33 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
34   : ARMBaseInstrInfo(STI), RI(STI) {
35 }
36 
37 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
38 void Thumb2InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
39   NopInst.setOpcode(ARM::tNOP);
40   NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
41   NopInst.addOperand(MCOperand::CreateReg(0));
42 }
43 
44 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
45   // FIXME
46   return 0;
47 }
48 
49 void
50 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
51                                          MachineBasicBlock *NewDest) const {
52   MachineBasicBlock *MBB = Tail->getParent();
53   ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
54   if (!AFI->hasITBlocks()) {
55     TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
56     return;
57   }
58 
59   // If the first instruction of Tail is predicated, we may have to update
60   // the IT instruction.
61   unsigned PredReg = 0;
62   ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
63   MachineBasicBlock::iterator MBBI = Tail;
64   if (CC != ARMCC::AL)
65     // Expecting at least the t2IT instruction before it.
66     --MBBI;
67 
68   // Actually replace the tail.
69   TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
70 
71   // Fix up IT.
72   if (CC != ARMCC::AL) {
73     MachineBasicBlock::iterator E = MBB->begin();
74     unsigned Count = 4; // At most 4 instructions in an IT block.
75     while (Count && MBBI != E) {
76       if (MBBI->isDebugValue()) {
77         --MBBI;
78         continue;
79       }
80       if (MBBI->getOpcode() == ARM::t2IT) {
81         unsigned Mask = MBBI->getOperand(1).getImm();
82         if (Count == 4)
83           MBBI->eraseFromParent();
84         else {
85           unsigned MaskOn = 1 << Count;
86           unsigned MaskOff = ~(MaskOn - 1);
87           MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
88         }
89         return;
90       }
91       --MBBI;
92       --Count;
93     }
94 
95     // Ctrl flow can reach here if branch folding is run before IT block
96     // formation pass.
97   }
98 }
99 
100 bool
101 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
102                                      MachineBasicBlock::iterator MBBI) const {
103   while (MBBI->isDebugValue()) {
104     ++MBBI;
105     if (MBBI == MBB.end())
106       return false;
107   }
108 
109   unsigned PredReg = 0;
110   return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
111 }
112 
113 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
114                                   MachineBasicBlock::iterator I, DebugLoc DL,
115                                   unsigned DestReg, unsigned SrcReg,
116                                   bool KillSrc) const {
117   // Handle SPR, DPR, and QPR copies.
118   if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
119     return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
120 
121   AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
122     .addReg(SrcReg, getKillRegState(KillSrc)));
123 }
124 
125 void Thumb2InstrInfo::
126 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
127                     unsigned SrcReg, bool isKill, int FI,
128                     const TargetRegisterClass *RC,
129                     const TargetRegisterInfo *TRI) const {
130   DebugLoc DL;
131   if (I != MBB.end()) DL = I->getDebugLoc();
132 
133   MachineFunction &MF = *MBB.getParent();
134   MachineFrameInfo &MFI = *MF.getFrameInfo();
135   MachineMemOperand *MMO =
136     MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
137                             MachineMemOperand::MOStore,
138                             MFI.getObjectSize(FI),
139                             MFI.getObjectAlignment(FI));
140 
141   if (RC == &ARM::GPRRegClass   || RC == &ARM::tGPRRegClass ||
142       RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
143       RC == &ARM::GPRnopcRegClass) {
144     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
145                    .addReg(SrcReg, getKillRegState(isKill))
146                    .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
147     return;
148   }
149 
150   if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
151     // Thumb2 STRD expects its dest-registers to be in rGPR. Not a problem for
152     // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
153     // otherwise).
154     MachineRegisterInfo *MRI = &MF.getRegInfo();
155     MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
156 
157     MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
158     AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
159     AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
160     MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
161     AddDefaultPred(MIB);
162     return;
163   }
164 
165   ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
166 }
167 
168 void Thumb2InstrInfo::
169 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
170                      unsigned DestReg, int FI,
171                      const TargetRegisterClass *RC,
172                      const TargetRegisterInfo *TRI) const {
173   MachineFunction &MF = *MBB.getParent();
174   MachineFrameInfo &MFI = *MF.getFrameInfo();
175   MachineMemOperand *MMO =
176     MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
177                             MachineMemOperand::MOLoad,
178                             MFI.getObjectSize(FI),
179                             MFI.getObjectAlignment(FI));
180   DebugLoc DL;
181   if (I != MBB.end()) DL = I->getDebugLoc();
182 
183   if (RC == &ARM::GPRRegClass   || RC == &ARM::tGPRRegClass ||
184       RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
185       RC == &ARM::GPRnopcRegClass) {
186     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
187                    .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
188     return;
189   }
190 
191   if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
192     // Thumb2 LDRD expects its dest-registers to be in rGPR. Not a problem for
193     // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
194     // otherwise).
195     MachineRegisterInfo *MRI = &MF.getRegInfo();
196     MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
197 
198     MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
199     AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
200     AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
201     MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
202     AddDefaultPred(MIB);
203 
204     if (TargetRegisterInfo::isPhysicalRegister(DestReg))
205       MIB.addReg(DestReg, RegState::ImplicitDefine);
206     return;
207   }
208 
209   ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
210 }
211 
212 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
213                                MachineBasicBlock::iterator &MBBI, DebugLoc dl,
214                                unsigned DestReg, unsigned BaseReg, int NumBytes,
215                                ARMCC::CondCodes Pred, unsigned PredReg,
216                                const ARMBaseInstrInfo &TII, unsigned MIFlags) {
217   bool isSub = NumBytes < 0;
218   if (isSub) NumBytes = -NumBytes;
219 
220   // If profitable, use a movw or movt to materialize the offset.
221   // FIXME: Use the scavenger to grab a scratch register.
222   if (DestReg != ARM::SP && DestReg != BaseReg &&
223       NumBytes >= 4096 &&
224       ARM_AM::getT2SOImmVal(NumBytes) == -1) {
225     bool Fits = false;
226     if (NumBytes < 65536) {
227       // Use a movw to materialize the 16-bit constant.
228       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
229         .addImm(NumBytes)
230         .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
231       Fits = true;
232     } else if ((NumBytes & 0xffff) == 0) {
233       // Use a movt to materialize the 32-bit constant.
234       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
235         .addReg(DestReg)
236         .addImm(NumBytes >> 16)
237         .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
238       Fits = true;
239     }
240 
241     if (Fits) {
242       if (isSub) {
243         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
244           .addReg(BaseReg, RegState::Kill)
245           .addReg(DestReg, RegState::Kill)
246           .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
247           .setMIFlags(MIFlags);
248       } else {
249         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
250           .addReg(DestReg, RegState::Kill)
251           .addReg(BaseReg, RegState::Kill)
252           .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
253           .setMIFlags(MIFlags);
254       }
255       return;
256     }
257   }
258 
259   while (NumBytes) {
260     unsigned ThisVal = NumBytes;
261     unsigned Opc = 0;
262     if (DestReg == ARM::SP && BaseReg != ARM::SP) {
263       // mov sp, rn. Note t2MOVr cannot be used.
264       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)
265         .addReg(BaseReg).setMIFlags(MIFlags));
266       BaseReg = ARM::SP;
267       continue;
268     }
269 
270     bool HasCCOut = true;
271     if (BaseReg == ARM::SP) {
272       // sub sp, sp, #imm7
273       if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
274         assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
275         Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
276         AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
277           .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags));
278         NumBytes = 0;
279         continue;
280       }
281 
282       // sub rd, sp, so_imm
283       Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
284       if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
285         NumBytes = 0;
286       } else {
287         // FIXME: Move this to ARMAddressingModes.h?
288         unsigned RotAmt = countLeadingZeros(ThisVal);
289         ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
290         NumBytes &= ~ThisVal;
291         assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
292                "Bit extraction didn't work?");
293       }
294     } else {
295       assert(DestReg != ARM::SP && BaseReg != ARM::SP);
296       Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
297       if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
298         NumBytes = 0;
299       } else if (ThisVal < 4096) {
300         Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
301         HasCCOut = false;
302         NumBytes = 0;
303       } else {
304         // FIXME: Move this to ARMAddressingModes.h?
305         unsigned RotAmt = countLeadingZeros(ThisVal);
306         ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
307         NumBytes &= ~ThisVal;
308         assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
309                "Bit extraction didn't work?");
310       }
311     }
312 
313     // Build the new ADD / SUB.
314     MachineInstrBuilder MIB =
315       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
316                      .addReg(BaseReg, RegState::Kill)
317                      .addImm(ThisVal)).setMIFlags(MIFlags);
318     if (HasCCOut)
319       AddDefaultCC(MIB);
320 
321     BaseReg = DestReg;
322   }
323 }
324 
325 static unsigned
326 negativeOffsetOpcode(unsigned opcode)
327 {
328   switch (opcode) {
329   case ARM::t2LDRi12:   return ARM::t2LDRi8;
330   case ARM::t2LDRHi12:  return ARM::t2LDRHi8;
331   case ARM::t2LDRBi12:  return ARM::t2LDRBi8;
332   case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
333   case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
334   case ARM::t2STRi12:   return ARM::t2STRi8;
335   case ARM::t2STRBi12:  return ARM::t2STRBi8;
336   case ARM::t2STRHi12:  return ARM::t2STRHi8;
337   case ARM::t2PLDi12:   return ARM::t2PLDi8;
338 
339   case ARM::t2LDRi8:
340   case ARM::t2LDRHi8:
341   case ARM::t2LDRBi8:
342   case ARM::t2LDRSHi8:
343   case ARM::t2LDRSBi8:
344   case ARM::t2STRi8:
345   case ARM::t2STRBi8:
346   case ARM::t2STRHi8:
347   case ARM::t2PLDi8:
348     return opcode;
349 
350   default:
351     break;
352   }
353 
354   return 0;
355 }
356 
357 static unsigned
358 positiveOffsetOpcode(unsigned opcode)
359 {
360   switch (opcode) {
361   case ARM::t2LDRi8:   return ARM::t2LDRi12;
362   case ARM::t2LDRHi8:  return ARM::t2LDRHi12;
363   case ARM::t2LDRBi8:  return ARM::t2LDRBi12;
364   case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
365   case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
366   case ARM::t2STRi8:   return ARM::t2STRi12;
367   case ARM::t2STRBi8:  return ARM::t2STRBi12;
368   case ARM::t2STRHi8:  return ARM::t2STRHi12;
369   case ARM::t2PLDi8:   return ARM::t2PLDi12;
370 
371   case ARM::t2LDRi12:
372   case ARM::t2LDRHi12:
373   case ARM::t2LDRBi12:
374   case ARM::t2LDRSHi12:
375   case ARM::t2LDRSBi12:
376   case ARM::t2STRi12:
377   case ARM::t2STRBi12:
378   case ARM::t2STRHi12:
379   case ARM::t2PLDi12:
380     return opcode;
381 
382   default:
383     break;
384   }
385 
386   return 0;
387 }
388 
389 static unsigned
390 immediateOffsetOpcode(unsigned opcode)
391 {
392   switch (opcode) {
393   case ARM::t2LDRs:   return ARM::t2LDRi12;
394   case ARM::t2LDRHs:  return ARM::t2LDRHi12;
395   case ARM::t2LDRBs:  return ARM::t2LDRBi12;
396   case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
397   case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
398   case ARM::t2STRs:   return ARM::t2STRi12;
399   case ARM::t2STRBs:  return ARM::t2STRBi12;
400   case ARM::t2STRHs:  return ARM::t2STRHi12;
401   case ARM::t2PLDs:   return ARM::t2PLDi12;
402 
403   case ARM::t2LDRi12:
404   case ARM::t2LDRHi12:
405   case ARM::t2LDRBi12:
406   case ARM::t2LDRSHi12:
407   case ARM::t2LDRSBi12:
408   case ARM::t2STRi12:
409   case ARM::t2STRBi12:
410   case ARM::t2STRHi12:
411   case ARM::t2PLDi12:
412   case ARM::t2LDRi8:
413   case ARM::t2LDRHi8:
414   case ARM::t2LDRBi8:
415   case ARM::t2LDRSHi8:
416   case ARM::t2LDRSBi8:
417   case ARM::t2STRi8:
418   case ARM::t2STRBi8:
419   case ARM::t2STRHi8:
420   case ARM::t2PLDi8:
421     return opcode;
422 
423   default:
424     break;
425   }
426 
427   return 0;
428 }
429 
430 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
431                                unsigned FrameReg, int &Offset,
432                                const ARMBaseInstrInfo &TII) {
433   unsigned Opcode = MI.getOpcode();
434   const MCInstrDesc &Desc = MI.getDesc();
435   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
436   bool isSub = false;
437 
438   // Memory operands in inline assembly always use AddrModeT2_i12.
439   if (Opcode == ARM::INLINEASM)
440     AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
441 
442   if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
443     Offset += MI.getOperand(FrameRegIdx+1).getImm();
444 
445     unsigned PredReg;
446     if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
447       // Turn it into a move.
448       MI.setDesc(TII.get(ARM::tMOVr));
449       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
450       // Remove offset and remaining explicit predicate operands.
451       do MI.RemoveOperand(FrameRegIdx+1);
452       while (MI.getNumOperands() > FrameRegIdx+1);
453       MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
454       AddDefaultPred(MIB);
455       return true;
456     }
457 
458     bool HasCCOut = Opcode != ARM::t2ADDri12;
459 
460     if (Offset < 0) {
461       Offset = -Offset;
462       isSub = true;
463       MI.setDesc(TII.get(ARM::t2SUBri));
464     } else {
465       MI.setDesc(TII.get(ARM::t2ADDri));
466     }
467 
468     // Common case: small offset, fits into instruction.
469     if (ARM_AM::getT2SOImmVal(Offset) != -1) {
470       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
471       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
472       // Add cc_out operand if the original instruction did not have one.
473       if (!HasCCOut)
474         MI.addOperand(MachineOperand::CreateReg(0, false));
475       Offset = 0;
476       return true;
477     }
478     // Another common case: imm12.
479     if (Offset < 4096 &&
480         (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
481       unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
482       MI.setDesc(TII.get(NewOpc));
483       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
484       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
485       // Remove the cc_out operand.
486       if (HasCCOut)
487         MI.RemoveOperand(MI.getNumOperands()-1);
488       Offset = 0;
489       return true;
490     }
491 
492     // Otherwise, extract 8 adjacent bits from the immediate into this
493     // t2ADDri/t2SUBri.
494     unsigned RotAmt = countLeadingZeros<unsigned>(Offset);
495     unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
496 
497     // We will handle these bits from offset, clear them.
498     Offset &= ~ThisImmVal;
499 
500     assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
501            "Bit extraction didn't work?");
502     MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
503     // Add cc_out operand if the original instruction did not have one.
504     if (!HasCCOut)
505       MI.addOperand(MachineOperand::CreateReg(0, false));
506 
507   } else {
508 
509     // AddrMode4 and AddrMode6 cannot handle any offset.
510     if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
511       return false;
512 
513     // AddrModeT2_so cannot handle any offset. If there is no offset
514     // register then we change to an immediate version.
515     unsigned NewOpc = Opcode;
516     if (AddrMode == ARMII::AddrModeT2_so) {
517       unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
518       if (OffsetReg != 0) {
519         MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
520         return Offset == 0;
521       }
522 
523       MI.RemoveOperand(FrameRegIdx+1);
524       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
525       NewOpc = immediateOffsetOpcode(Opcode);
526       AddrMode = ARMII::AddrModeT2_i12;
527     }
528 
529     unsigned NumBits = 0;
530     unsigned Scale = 1;
531     if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
532       // i8 supports only negative, and i12 supports only positive, so
533       // based on Offset sign convert Opcode to the appropriate
534       // instruction
535       Offset += MI.getOperand(FrameRegIdx+1).getImm();
536       if (Offset < 0) {
537         NewOpc = negativeOffsetOpcode(Opcode);
538         NumBits = 8;
539         isSub = true;
540         Offset = -Offset;
541       } else {
542         NewOpc = positiveOffsetOpcode(Opcode);
543         NumBits = 12;
544       }
545     } else if (AddrMode == ARMII::AddrMode5) {
546       // VFP address mode.
547       const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
548       int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
549       if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
550         InstrOffs *= -1;
551       NumBits = 8;
552       Scale = 4;
553       Offset += InstrOffs * 4;
554       assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
555       if (Offset < 0) {
556         Offset = -Offset;
557         isSub = true;
558       }
559     } else if (AddrMode == ARMII::AddrModeT2_i8s4) {
560       Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
561       NumBits = 8;
562       // MCInst operand has already scaled value.
563       Scale = 1;
564       if (Offset < 0) {
565         isSub = true;
566         Offset = -Offset;
567       }
568     } else {
569       llvm_unreachable("Unsupported addressing mode!");
570     }
571 
572     if (NewOpc != Opcode)
573       MI.setDesc(TII.get(NewOpc));
574 
575     MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
576 
577     // Attempt to fold address computation
578     // Common case: small offset, fits into instruction.
579     int ImmedOffset = Offset / Scale;
580     unsigned Mask = (1 << NumBits) - 1;
581     if ((unsigned)Offset <= Mask * Scale) {
582       // Replace the FrameIndex with fp/sp
583       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
584       if (isSub) {
585         if (AddrMode == ARMII::AddrMode5)
586           // FIXME: Not consistent.
587           ImmedOffset |= 1 << NumBits;
588         else
589           ImmedOffset = -ImmedOffset;
590       }
591       ImmOp.ChangeToImmediate(ImmedOffset);
592       Offset = 0;
593       return true;
594     }
595 
596     // Otherwise, offset doesn't fit. Pull in what we can to simplify
597     ImmedOffset = ImmedOffset & Mask;
598     if (isSub) {
599       if (AddrMode == ARMII::AddrMode5)
600         // FIXME: Not consistent.
601         ImmedOffset |= 1 << NumBits;
602       else {
603         ImmedOffset = -ImmedOffset;
604         if (ImmedOffset == 0)
605           // Change the opcode back if the encoded offset is zero.
606           MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
607       }
608     }
609     ImmOp.ChangeToImmediate(ImmedOffset);
610     Offset &= ~(Mask*Scale);
611   }
612 
613   Offset = (isSub) ? -Offset : Offset;
614   return Offset == 0;
615 }
616 
617 ARMCC::CondCodes
618 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
619   unsigned Opc = MI->getOpcode();
620   if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
621     return ARMCC::AL;
622   return getInstrPredicate(MI, PredReg);
623 }
624