1 //===-- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information -------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Thumb2InstrInfo.h"
15 #include "ARM.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "MCTargetDesc/ARMAddressingModes.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/Support/CommandLine.h"
25 
26 using namespace llvm;
27 
28 static cl::opt<bool>
29 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
30            cl::desc("Use old-style Thumb2 if-conversion heuristics"),
31            cl::init(false));
32 
33 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
34   : ARMBaseInstrInfo(STI), RI(STI) {
35 }
36 
37 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
38 void Thumb2InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
39   NopInst.setOpcode(ARM::tHINT);
40   NopInst.addOperand(MCOperand::CreateImm(0));
41   NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
42   NopInst.addOperand(MCOperand::CreateReg(0));
43 }
44 
45 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
46   // FIXME
47   return 0;
48 }
49 
50 void
51 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
52                                          MachineBasicBlock *NewDest) const {
53   MachineBasicBlock *MBB = Tail->getParent();
54   ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
55   if (!AFI->hasITBlocks()) {
56     TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
57     return;
58   }
59 
60   // If the first instruction of Tail is predicated, we may have to update
61   // the IT instruction.
62   unsigned PredReg = 0;
63   ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
64   MachineBasicBlock::iterator MBBI = Tail;
65   if (CC != ARMCC::AL)
66     // Expecting at least the t2IT instruction before it.
67     --MBBI;
68 
69   // Actually replace the tail.
70   TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
71 
72   // Fix up IT.
73   if (CC != ARMCC::AL) {
74     MachineBasicBlock::iterator E = MBB->begin();
75     unsigned Count = 4; // At most 4 instructions in an IT block.
76     while (Count && MBBI != E) {
77       if (MBBI->isDebugValue()) {
78         --MBBI;
79         continue;
80       }
81       if (MBBI->getOpcode() == ARM::t2IT) {
82         unsigned Mask = MBBI->getOperand(1).getImm();
83         if (Count == 4)
84           MBBI->eraseFromParent();
85         else {
86           unsigned MaskOn = 1 << Count;
87           unsigned MaskOff = ~(MaskOn - 1);
88           MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
89         }
90         return;
91       }
92       --MBBI;
93       --Count;
94     }
95 
96     // Ctrl flow can reach here if branch folding is run before IT block
97     // formation pass.
98   }
99 }
100 
101 bool
102 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
103                                      MachineBasicBlock::iterator MBBI) const {
104   while (MBBI->isDebugValue()) {
105     ++MBBI;
106     if (MBBI == MBB.end())
107       return false;
108   }
109 
110   unsigned PredReg = 0;
111   return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
112 }
113 
114 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
115                                   MachineBasicBlock::iterator I, DebugLoc DL,
116                                   unsigned DestReg, unsigned SrcReg,
117                                   bool KillSrc) const {
118   // Handle SPR, DPR, and QPR copies.
119   if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
120     return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
121 
122   AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
123     .addReg(SrcReg, getKillRegState(KillSrc)));
124 }
125 
126 void Thumb2InstrInfo::
127 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
128                     unsigned SrcReg, bool isKill, int FI,
129                     const TargetRegisterClass *RC,
130                     const TargetRegisterInfo *TRI) const {
131   DebugLoc DL;
132   if (I != MBB.end()) DL = I->getDebugLoc();
133 
134   MachineFunction &MF = *MBB.getParent();
135   MachineFrameInfo &MFI = *MF.getFrameInfo();
136   MachineMemOperand *MMO =
137     MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
138                             MachineMemOperand::MOStore,
139                             MFI.getObjectSize(FI),
140                             MFI.getObjectAlignment(FI));
141 
142   if (RC == &ARM::GPRRegClass   || RC == &ARM::tGPRRegClass ||
143       RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
144       RC == &ARM::GPRnopcRegClass) {
145     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
146                    .addReg(SrcReg, getKillRegState(isKill))
147                    .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
148     return;
149   }
150 
151   if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
152     // Thumb2 STRD expects its dest-registers to be in rGPR. Not a problem for
153     // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
154     // otherwise).
155     MachineRegisterInfo *MRI = &MF.getRegInfo();
156     MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
157 
158     MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
159     AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
160     AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
161     MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
162     AddDefaultPred(MIB);
163     return;
164   }
165 
166   ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
167 }
168 
169 void Thumb2InstrInfo::
170 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
171                      unsigned DestReg, int FI,
172                      const TargetRegisterClass *RC,
173                      const TargetRegisterInfo *TRI) const {
174   MachineFunction &MF = *MBB.getParent();
175   MachineFrameInfo &MFI = *MF.getFrameInfo();
176   MachineMemOperand *MMO =
177     MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
178                             MachineMemOperand::MOLoad,
179                             MFI.getObjectSize(FI),
180                             MFI.getObjectAlignment(FI));
181   DebugLoc DL;
182   if (I != MBB.end()) DL = I->getDebugLoc();
183 
184   if (RC == &ARM::GPRRegClass   || RC == &ARM::tGPRRegClass ||
185       RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
186       RC == &ARM::GPRnopcRegClass) {
187     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
188                    .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
189     return;
190   }
191 
192   if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
193     // Thumb2 LDRD expects its dest-registers to be in rGPR. Not a problem for
194     // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
195     // otherwise).
196     MachineRegisterInfo *MRI = &MF.getRegInfo();
197     MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
198 
199     MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
200     AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
201     AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
202     MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
203     AddDefaultPred(MIB);
204 
205     if (TargetRegisterInfo::isPhysicalRegister(DestReg))
206       MIB.addReg(DestReg, RegState::ImplicitDefine);
207     return;
208   }
209 
210   ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
211 }
212 
213 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
214                                MachineBasicBlock::iterator &MBBI, DebugLoc dl,
215                                unsigned DestReg, unsigned BaseReg, int NumBytes,
216                                ARMCC::CondCodes Pred, unsigned PredReg,
217                                const ARMBaseInstrInfo &TII, unsigned MIFlags) {
218   bool isSub = NumBytes < 0;
219   if (isSub) NumBytes = -NumBytes;
220 
221   // If profitable, use a movw or movt to materialize the offset.
222   // FIXME: Use the scavenger to grab a scratch register.
223   if (DestReg != ARM::SP && DestReg != BaseReg &&
224       NumBytes >= 4096 &&
225       ARM_AM::getT2SOImmVal(NumBytes) == -1) {
226     bool Fits = false;
227     if (NumBytes < 65536) {
228       // Use a movw to materialize the 16-bit constant.
229       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
230         .addImm(NumBytes)
231         .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
232       Fits = true;
233     } else if ((NumBytes & 0xffff) == 0) {
234       // Use a movt to materialize the 32-bit constant.
235       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
236         .addReg(DestReg)
237         .addImm(NumBytes >> 16)
238         .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
239       Fits = true;
240     }
241 
242     if (Fits) {
243       if (isSub) {
244         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
245           .addReg(BaseReg, RegState::Kill)
246           .addReg(DestReg, RegState::Kill)
247           .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
248           .setMIFlags(MIFlags);
249       } else {
250         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
251           .addReg(DestReg, RegState::Kill)
252           .addReg(BaseReg, RegState::Kill)
253           .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
254           .setMIFlags(MIFlags);
255       }
256       return;
257     }
258   }
259 
260   while (NumBytes) {
261     unsigned ThisVal = NumBytes;
262     unsigned Opc = 0;
263     if (DestReg == ARM::SP && BaseReg != ARM::SP) {
264       // mov sp, rn. Note t2MOVr cannot be used.
265       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)
266         .addReg(BaseReg).setMIFlags(MIFlags));
267       BaseReg = ARM::SP;
268       continue;
269     }
270 
271     bool HasCCOut = true;
272     if (BaseReg == ARM::SP) {
273       // sub sp, sp, #imm7
274       if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
275         assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
276         Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
277         AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
278           .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags));
279         NumBytes = 0;
280         continue;
281       }
282 
283       // sub rd, sp, so_imm
284       Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
285       if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
286         NumBytes = 0;
287       } else {
288         // FIXME: Move this to ARMAddressingModes.h?
289         unsigned RotAmt = countLeadingZeros(ThisVal);
290         ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
291         NumBytes &= ~ThisVal;
292         assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
293                "Bit extraction didn't work?");
294       }
295     } else {
296       assert(DestReg != ARM::SP && BaseReg != ARM::SP);
297       Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
298       if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
299         NumBytes = 0;
300       } else if (ThisVal < 4096) {
301         Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
302         HasCCOut = false;
303         NumBytes = 0;
304       } else {
305         // FIXME: Move this to ARMAddressingModes.h?
306         unsigned RotAmt = countLeadingZeros(ThisVal);
307         ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
308         NumBytes &= ~ThisVal;
309         assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
310                "Bit extraction didn't work?");
311       }
312     }
313 
314     // Build the new ADD / SUB.
315     MachineInstrBuilder MIB =
316       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
317                      .addReg(BaseReg, RegState::Kill)
318                      .addImm(ThisVal)).setMIFlags(MIFlags);
319     if (HasCCOut)
320       AddDefaultCC(MIB);
321 
322     BaseReg = DestReg;
323   }
324 }
325 
326 static unsigned
327 negativeOffsetOpcode(unsigned opcode)
328 {
329   switch (opcode) {
330   case ARM::t2LDRi12:   return ARM::t2LDRi8;
331   case ARM::t2LDRHi12:  return ARM::t2LDRHi8;
332   case ARM::t2LDRBi12:  return ARM::t2LDRBi8;
333   case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
334   case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
335   case ARM::t2STRi12:   return ARM::t2STRi8;
336   case ARM::t2STRBi12:  return ARM::t2STRBi8;
337   case ARM::t2STRHi12:  return ARM::t2STRHi8;
338   case ARM::t2PLDi12:   return ARM::t2PLDi8;
339 
340   case ARM::t2LDRi8:
341   case ARM::t2LDRHi8:
342   case ARM::t2LDRBi8:
343   case ARM::t2LDRSHi8:
344   case ARM::t2LDRSBi8:
345   case ARM::t2STRi8:
346   case ARM::t2STRBi8:
347   case ARM::t2STRHi8:
348   case ARM::t2PLDi8:
349     return opcode;
350 
351   default:
352     break;
353   }
354 
355   return 0;
356 }
357 
358 static unsigned
359 positiveOffsetOpcode(unsigned opcode)
360 {
361   switch (opcode) {
362   case ARM::t2LDRi8:   return ARM::t2LDRi12;
363   case ARM::t2LDRHi8:  return ARM::t2LDRHi12;
364   case ARM::t2LDRBi8:  return ARM::t2LDRBi12;
365   case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
366   case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
367   case ARM::t2STRi8:   return ARM::t2STRi12;
368   case ARM::t2STRBi8:  return ARM::t2STRBi12;
369   case ARM::t2STRHi8:  return ARM::t2STRHi12;
370   case ARM::t2PLDi8:   return ARM::t2PLDi12;
371 
372   case ARM::t2LDRi12:
373   case ARM::t2LDRHi12:
374   case ARM::t2LDRBi12:
375   case ARM::t2LDRSHi12:
376   case ARM::t2LDRSBi12:
377   case ARM::t2STRi12:
378   case ARM::t2STRBi12:
379   case ARM::t2STRHi12:
380   case ARM::t2PLDi12:
381     return opcode;
382 
383   default:
384     break;
385   }
386 
387   return 0;
388 }
389 
390 static unsigned
391 immediateOffsetOpcode(unsigned opcode)
392 {
393   switch (opcode) {
394   case ARM::t2LDRs:   return ARM::t2LDRi12;
395   case ARM::t2LDRHs:  return ARM::t2LDRHi12;
396   case ARM::t2LDRBs:  return ARM::t2LDRBi12;
397   case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
398   case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
399   case ARM::t2STRs:   return ARM::t2STRi12;
400   case ARM::t2STRBs:  return ARM::t2STRBi12;
401   case ARM::t2STRHs:  return ARM::t2STRHi12;
402   case ARM::t2PLDs:   return ARM::t2PLDi12;
403 
404   case ARM::t2LDRi12:
405   case ARM::t2LDRHi12:
406   case ARM::t2LDRBi12:
407   case ARM::t2LDRSHi12:
408   case ARM::t2LDRSBi12:
409   case ARM::t2STRi12:
410   case ARM::t2STRBi12:
411   case ARM::t2STRHi12:
412   case ARM::t2PLDi12:
413   case ARM::t2LDRi8:
414   case ARM::t2LDRHi8:
415   case ARM::t2LDRBi8:
416   case ARM::t2LDRSHi8:
417   case ARM::t2LDRSBi8:
418   case ARM::t2STRi8:
419   case ARM::t2STRBi8:
420   case ARM::t2STRHi8:
421   case ARM::t2PLDi8:
422     return opcode;
423 
424   default:
425     break;
426   }
427 
428   return 0;
429 }
430 
431 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
432                                unsigned FrameReg, int &Offset,
433                                const ARMBaseInstrInfo &TII) {
434   unsigned Opcode = MI.getOpcode();
435   const MCInstrDesc &Desc = MI.getDesc();
436   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
437   bool isSub = false;
438 
439   // Memory operands in inline assembly always use AddrModeT2_i12.
440   if (Opcode == ARM::INLINEASM)
441     AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
442 
443   if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
444     Offset += MI.getOperand(FrameRegIdx+1).getImm();
445 
446     unsigned PredReg;
447     if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
448       // Turn it into a move.
449       MI.setDesc(TII.get(ARM::tMOVr));
450       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
451       // Remove offset and remaining explicit predicate operands.
452       do MI.RemoveOperand(FrameRegIdx+1);
453       while (MI.getNumOperands() > FrameRegIdx+1);
454       MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
455       AddDefaultPred(MIB);
456       return true;
457     }
458 
459     bool HasCCOut = Opcode != ARM::t2ADDri12;
460 
461     if (Offset < 0) {
462       Offset = -Offset;
463       isSub = true;
464       MI.setDesc(TII.get(ARM::t2SUBri));
465     } else {
466       MI.setDesc(TII.get(ARM::t2ADDri));
467     }
468 
469     // Common case: small offset, fits into instruction.
470     if (ARM_AM::getT2SOImmVal(Offset) != -1) {
471       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
472       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
473       // Add cc_out operand if the original instruction did not have one.
474       if (!HasCCOut)
475         MI.addOperand(MachineOperand::CreateReg(0, false));
476       Offset = 0;
477       return true;
478     }
479     // Another common case: imm12.
480     if (Offset < 4096 &&
481         (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
482       unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
483       MI.setDesc(TII.get(NewOpc));
484       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
485       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
486       // Remove the cc_out operand.
487       if (HasCCOut)
488         MI.RemoveOperand(MI.getNumOperands()-1);
489       Offset = 0;
490       return true;
491     }
492 
493     // Otherwise, extract 8 adjacent bits from the immediate into this
494     // t2ADDri/t2SUBri.
495     unsigned RotAmt = countLeadingZeros<unsigned>(Offset);
496     unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
497 
498     // We will handle these bits from offset, clear them.
499     Offset &= ~ThisImmVal;
500 
501     assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
502            "Bit extraction didn't work?");
503     MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
504     // Add cc_out operand if the original instruction did not have one.
505     if (!HasCCOut)
506       MI.addOperand(MachineOperand::CreateReg(0, false));
507 
508   } else {
509 
510     // AddrMode4 and AddrMode6 cannot handle any offset.
511     if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
512       return false;
513 
514     // AddrModeT2_so cannot handle any offset. If there is no offset
515     // register then we change to an immediate version.
516     unsigned NewOpc = Opcode;
517     if (AddrMode == ARMII::AddrModeT2_so) {
518       unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
519       if (OffsetReg != 0) {
520         MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
521         return Offset == 0;
522       }
523 
524       MI.RemoveOperand(FrameRegIdx+1);
525       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
526       NewOpc = immediateOffsetOpcode(Opcode);
527       AddrMode = ARMII::AddrModeT2_i12;
528     }
529 
530     unsigned NumBits = 0;
531     unsigned Scale = 1;
532     if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
533       // i8 supports only negative, and i12 supports only positive, so
534       // based on Offset sign convert Opcode to the appropriate
535       // instruction
536       Offset += MI.getOperand(FrameRegIdx+1).getImm();
537       if (Offset < 0) {
538         NewOpc = negativeOffsetOpcode(Opcode);
539         NumBits = 8;
540         isSub = true;
541         Offset = -Offset;
542       } else {
543         NewOpc = positiveOffsetOpcode(Opcode);
544         NumBits = 12;
545       }
546     } else if (AddrMode == ARMII::AddrMode5) {
547       // VFP address mode.
548       const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
549       int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
550       if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
551         InstrOffs *= -1;
552       NumBits = 8;
553       Scale = 4;
554       Offset += InstrOffs * 4;
555       assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
556       if (Offset < 0) {
557         Offset = -Offset;
558         isSub = true;
559       }
560     } else if (AddrMode == ARMII::AddrModeT2_i8s4) {
561       Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
562       NumBits = 8;
563       // MCInst operand has already scaled value.
564       Scale = 1;
565       if (Offset < 0) {
566         isSub = true;
567         Offset = -Offset;
568       }
569     } else {
570       llvm_unreachable("Unsupported addressing mode!");
571     }
572 
573     if (NewOpc != Opcode)
574       MI.setDesc(TII.get(NewOpc));
575 
576     MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
577 
578     // Attempt to fold address computation
579     // Common case: small offset, fits into instruction.
580     int ImmedOffset = Offset / Scale;
581     unsigned Mask = (1 << NumBits) - 1;
582     if ((unsigned)Offset <= Mask * Scale) {
583       // Replace the FrameIndex with fp/sp
584       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
585       if (isSub) {
586         if (AddrMode == ARMII::AddrMode5)
587           // FIXME: Not consistent.
588           ImmedOffset |= 1 << NumBits;
589         else
590           ImmedOffset = -ImmedOffset;
591       }
592       ImmOp.ChangeToImmediate(ImmedOffset);
593       Offset = 0;
594       return true;
595     }
596 
597     // Otherwise, offset doesn't fit. Pull in what we can to simplify
598     ImmedOffset = ImmedOffset & Mask;
599     if (isSub) {
600       if (AddrMode == ARMII::AddrMode5)
601         // FIXME: Not consistent.
602         ImmedOffset |= 1 << NumBits;
603       else {
604         ImmedOffset = -ImmedOffset;
605         if (ImmedOffset == 0)
606           // Change the opcode back if the encoded offset is zero.
607           MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
608       }
609     }
610     ImmOp.ChangeToImmediate(ImmedOffset);
611     Offset &= ~(Mask*Scale);
612   }
613 
614   Offset = (isSub) ? -Offset : Offset;
615   return Offset == 0;
616 }
617 
618 ARMCC::CondCodes
619 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
620   unsigned Opc = MI->getOpcode();
621   if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
622     return ARMCC::AL;
623   return getInstrPredicate(MI, PredReg);
624 }
625