1 //===-- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information -------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Thumb2InstrInfo.h"
15 #include "ARMConstantPoolValue.h"
16 #include "ARMMachineFunctionInfo.h"
17 #include "MCTargetDesc/ARMAddressingModes.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/Support/CommandLine.h"
24 
25 using namespace llvm;
26 
27 static cl::opt<bool>
28 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
29            cl::desc("Use old-style Thumb2 if-conversion heuristics"),
30            cl::init(false));
31 
32 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
33     : ARMBaseInstrInfo(STI), RI() {}
34 
35 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
36 void Thumb2InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
37   NopInst.setOpcode(ARM::tHINT);
38   NopInst.addOperand(MCOperand::createImm(0));
39   NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
40   NopInst.addOperand(MCOperand::createReg(0));
41 }
42 
43 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
44   // FIXME
45   return 0;
46 }
47 
48 void
49 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
50                                          MachineBasicBlock *NewDest) const {
51   MachineBasicBlock *MBB = Tail->getParent();
52   ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
53   if (!AFI->hasITBlocks() || Tail->isBranch()) {
54     TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
55     return;
56   }
57 
58   // If the first instruction of Tail is predicated, we may have to update
59   // the IT instruction.
60   unsigned PredReg = 0;
61   ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg);
62   MachineBasicBlock::iterator MBBI = Tail;
63   if (CC != ARMCC::AL)
64     // Expecting at least the t2IT instruction before it.
65     --MBBI;
66 
67   // Actually replace the tail.
68   TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
69 
70   // Fix up IT.
71   if (CC != ARMCC::AL) {
72     MachineBasicBlock::iterator E = MBB->begin();
73     unsigned Count = 4; // At most 4 instructions in an IT block.
74     while (Count && MBBI != E) {
75       if (MBBI->isDebugValue()) {
76         --MBBI;
77         continue;
78       }
79       if (MBBI->getOpcode() == ARM::t2IT) {
80         unsigned Mask = MBBI->getOperand(1).getImm();
81         if (Count == 4)
82           MBBI->eraseFromParent();
83         else {
84           unsigned MaskOn = 1 << Count;
85           unsigned MaskOff = ~(MaskOn - 1);
86           MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
87         }
88         return;
89       }
90       --MBBI;
91       --Count;
92     }
93 
94     // Ctrl flow can reach here if branch folding is run before IT block
95     // formation pass.
96   }
97 }
98 
99 bool
100 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
101                                      MachineBasicBlock::iterator MBBI) const {
102   while (MBBI->isDebugValue()) {
103     ++MBBI;
104     if (MBBI == MBB.end())
105       return false;
106   }
107 
108   unsigned PredReg = 0;
109   return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL;
110 }
111 
112 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
113                                   MachineBasicBlock::iterator I,
114                                   const DebugLoc &DL, unsigned DestReg,
115                                   unsigned SrcReg, bool KillSrc) const {
116   // Handle SPR, DPR, and QPR copies.
117   if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
118     return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
119 
120   BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
121       .addReg(SrcReg, getKillRegState(KillSrc))
122       .add(predOps(ARMCC::AL));
123 }
124 
125 void Thumb2InstrInfo::
126 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
127                     unsigned SrcReg, bool isKill, int FI,
128                     const TargetRegisterClass *RC,
129                     const TargetRegisterInfo *TRI) const {
130   DebugLoc DL;
131   if (I != MBB.end()) DL = I->getDebugLoc();
132 
133   MachineFunction &MF = *MBB.getParent();
134   MachineFrameInfo &MFI = MF.getFrameInfo();
135   MachineMemOperand *MMO = MF.getMachineMemOperand(
136       MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
137       MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
138 
139   if (RC == &ARM::GPRRegClass   || RC == &ARM::tGPRRegClass ||
140       RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
141       RC == &ARM::GPRnopcRegClass) {
142     BuildMI(MBB, I, DL, get(ARM::t2STRi12))
143         .addReg(SrcReg, getKillRegState(isKill))
144         .addFrameIndex(FI)
145         .addImm(0)
146         .addMemOperand(MMO)
147         .add(predOps(ARMCC::AL));
148     return;
149   }
150 
151   if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
152     // Thumb2 STRD expects its dest-registers to be in rGPR. Not a problem for
153     // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
154     // otherwise).
155     if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
156       MachineRegisterInfo *MRI = &MF.getRegInfo();
157       MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
158     }
159 
160     MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
161     AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
162     AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
163     MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO).add(predOps(ARMCC::AL));
164     return;
165   }
166 
167   ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
168 }
169 
170 void Thumb2InstrInfo::
171 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
172                      unsigned DestReg, int FI,
173                      const TargetRegisterClass *RC,
174                      const TargetRegisterInfo *TRI) const {
175   MachineFunction &MF = *MBB.getParent();
176   MachineFrameInfo &MFI = MF.getFrameInfo();
177   MachineMemOperand *MMO = MF.getMachineMemOperand(
178       MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
179       MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
180   DebugLoc DL;
181   if (I != MBB.end()) DL = I->getDebugLoc();
182 
183   if (RC == &ARM::GPRRegClass   || RC == &ARM::tGPRRegClass ||
184       RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
185       RC == &ARM::GPRnopcRegClass) {
186     BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
187         .addFrameIndex(FI)
188         .addImm(0)
189         .addMemOperand(MMO)
190         .add(predOps(ARMCC::AL));
191     return;
192   }
193 
194   if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
195     // Thumb2 LDRD expects its dest-registers to be in rGPR. Not a problem for
196     // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
197     // otherwise).
198     if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
199       MachineRegisterInfo *MRI = &MF.getRegInfo();
200       MRI->constrainRegClass(DestReg,
201                              &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
202     }
203 
204     MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
205     AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
206     AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
207     MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO).add(predOps(ARMCC::AL));
208 
209     if (TargetRegisterInfo::isPhysicalRegister(DestReg))
210       MIB.addReg(DestReg, RegState::ImplicitDefine);
211     return;
212   }
213 
214   ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
215 }
216 
217 void Thumb2InstrInfo::expandLoadStackGuard(
218     MachineBasicBlock::iterator MI) const {
219   MachineFunction &MF = *MI->getParent()->getParent();
220   if (MF.getTarget().isPositionIndependent())
221     expandLoadStackGuardBase(MI, ARM::t2MOV_ga_pcrel, ARM::t2LDRi12);
222   else
223     expandLoadStackGuardBase(MI, ARM::t2MOVi32imm, ARM::t2LDRi12);
224 }
225 
226 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
227                                   MachineBasicBlock::iterator &MBBI,
228                                   const DebugLoc &dl, unsigned DestReg,
229                                   unsigned BaseReg, int NumBytes,
230                                   ARMCC::CondCodes Pred, unsigned PredReg,
231                                   const ARMBaseInstrInfo &TII,
232                                   unsigned MIFlags) {
233   if (NumBytes == 0 && DestReg != BaseReg) {
234     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
235       .addReg(BaseReg, RegState::Kill)
236       .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
237     return;
238   }
239 
240   bool isSub = NumBytes < 0;
241   if (isSub) NumBytes = -NumBytes;
242 
243   // If profitable, use a movw or movt to materialize the offset.
244   // FIXME: Use the scavenger to grab a scratch register.
245   if (DestReg != ARM::SP && DestReg != BaseReg &&
246       NumBytes >= 4096 &&
247       ARM_AM::getT2SOImmVal(NumBytes) == -1) {
248     bool Fits = false;
249     if (NumBytes < 65536) {
250       // Use a movw to materialize the 16-bit constant.
251       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
252         .addImm(NumBytes)
253         .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
254       Fits = true;
255     } else if ((NumBytes & 0xffff) == 0) {
256       // Use a movt to materialize the 32-bit constant.
257       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
258         .addReg(DestReg)
259         .addImm(NumBytes >> 16)
260         .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
261       Fits = true;
262     }
263 
264     if (Fits) {
265       if (isSub) {
266         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
267             .addReg(BaseReg)
268             .addReg(DestReg, RegState::Kill)
269             .add(predOps(Pred, PredReg))
270             .add(condCodeOp())
271             .setMIFlags(MIFlags);
272       } else {
273         // Here we know that DestReg is not SP but we do not
274         // know anything about BaseReg. t2ADDrr is an invalid
275         // instruction is SP is used as the second argument, but
276         // is fine if SP is the first argument. To be sure we
277         // do not generate invalid encoding, put BaseReg first.
278         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
279             .addReg(BaseReg)
280             .addReg(DestReg, RegState::Kill)
281             .add(predOps(Pred, PredReg))
282             .add(condCodeOp())
283             .setMIFlags(MIFlags);
284       }
285       return;
286     }
287   }
288 
289   while (NumBytes) {
290     unsigned ThisVal = NumBytes;
291     unsigned Opc = 0;
292     if (DestReg == ARM::SP && BaseReg != ARM::SP) {
293       // mov sp, rn. Note t2MOVr cannot be used.
294       BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
295           .addReg(BaseReg)
296           .setMIFlags(MIFlags)
297           .add(predOps(ARMCC::AL));
298       BaseReg = ARM::SP;
299       continue;
300     }
301 
302     bool HasCCOut = true;
303     if (BaseReg == ARM::SP) {
304       // sub sp, sp, #imm7
305       if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
306         assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
307         Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
308         BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
309             .addReg(BaseReg)
310             .addImm(ThisVal / 4)
311             .setMIFlags(MIFlags)
312             .add(predOps(ARMCC::AL));
313         NumBytes = 0;
314         continue;
315       }
316 
317       // sub rd, sp, so_imm
318       Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
319       if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
320         NumBytes = 0;
321       } else {
322         // FIXME: Move this to ARMAddressingModes.h?
323         unsigned RotAmt = countLeadingZeros(ThisVal);
324         ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
325         NumBytes &= ~ThisVal;
326         assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
327                "Bit extraction didn't work?");
328       }
329     } else {
330       assert(DestReg != ARM::SP && BaseReg != ARM::SP);
331       Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
332       if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
333         NumBytes = 0;
334       } else if (ThisVal < 4096) {
335         Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
336         HasCCOut = false;
337         NumBytes = 0;
338       } else {
339         // FIXME: Move this to ARMAddressingModes.h?
340         unsigned RotAmt = countLeadingZeros(ThisVal);
341         ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
342         NumBytes &= ~ThisVal;
343         assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
344                "Bit extraction didn't work?");
345       }
346     }
347 
348     // Build the new ADD / SUB.
349     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
350                                   .addReg(BaseReg, RegState::Kill)
351                                   .addImm(ThisVal)
352                                   .add(predOps(ARMCC::AL))
353                                   .setMIFlags(MIFlags);
354     if (HasCCOut)
355       MIB.add(condCodeOp());
356 
357     BaseReg = DestReg;
358   }
359 }
360 
361 static unsigned
362 negativeOffsetOpcode(unsigned opcode)
363 {
364   switch (opcode) {
365   case ARM::t2LDRi12:   return ARM::t2LDRi8;
366   case ARM::t2LDRHi12:  return ARM::t2LDRHi8;
367   case ARM::t2LDRBi12:  return ARM::t2LDRBi8;
368   case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
369   case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
370   case ARM::t2STRi12:   return ARM::t2STRi8;
371   case ARM::t2STRBi12:  return ARM::t2STRBi8;
372   case ARM::t2STRHi12:  return ARM::t2STRHi8;
373   case ARM::t2PLDi12:   return ARM::t2PLDi8;
374 
375   case ARM::t2LDRi8:
376   case ARM::t2LDRHi8:
377   case ARM::t2LDRBi8:
378   case ARM::t2LDRSHi8:
379   case ARM::t2LDRSBi8:
380   case ARM::t2STRi8:
381   case ARM::t2STRBi8:
382   case ARM::t2STRHi8:
383   case ARM::t2PLDi8:
384     return opcode;
385 
386   default:
387     break;
388   }
389 
390   return 0;
391 }
392 
393 static unsigned
394 positiveOffsetOpcode(unsigned opcode)
395 {
396   switch (opcode) {
397   case ARM::t2LDRi8:   return ARM::t2LDRi12;
398   case ARM::t2LDRHi8:  return ARM::t2LDRHi12;
399   case ARM::t2LDRBi8:  return ARM::t2LDRBi12;
400   case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
401   case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
402   case ARM::t2STRi8:   return ARM::t2STRi12;
403   case ARM::t2STRBi8:  return ARM::t2STRBi12;
404   case ARM::t2STRHi8:  return ARM::t2STRHi12;
405   case ARM::t2PLDi8:   return ARM::t2PLDi12;
406 
407   case ARM::t2LDRi12:
408   case ARM::t2LDRHi12:
409   case ARM::t2LDRBi12:
410   case ARM::t2LDRSHi12:
411   case ARM::t2LDRSBi12:
412   case ARM::t2STRi12:
413   case ARM::t2STRBi12:
414   case ARM::t2STRHi12:
415   case ARM::t2PLDi12:
416     return opcode;
417 
418   default:
419     break;
420   }
421 
422   return 0;
423 }
424 
425 static unsigned
426 immediateOffsetOpcode(unsigned opcode)
427 {
428   switch (opcode) {
429   case ARM::t2LDRs:   return ARM::t2LDRi12;
430   case ARM::t2LDRHs:  return ARM::t2LDRHi12;
431   case ARM::t2LDRBs:  return ARM::t2LDRBi12;
432   case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
433   case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
434   case ARM::t2STRs:   return ARM::t2STRi12;
435   case ARM::t2STRBs:  return ARM::t2STRBi12;
436   case ARM::t2STRHs:  return ARM::t2STRHi12;
437   case ARM::t2PLDs:   return ARM::t2PLDi12;
438 
439   case ARM::t2LDRi12:
440   case ARM::t2LDRHi12:
441   case ARM::t2LDRBi12:
442   case ARM::t2LDRSHi12:
443   case ARM::t2LDRSBi12:
444   case ARM::t2STRi12:
445   case ARM::t2STRBi12:
446   case ARM::t2STRHi12:
447   case ARM::t2PLDi12:
448   case ARM::t2LDRi8:
449   case ARM::t2LDRHi8:
450   case ARM::t2LDRBi8:
451   case ARM::t2LDRSHi8:
452   case ARM::t2LDRSBi8:
453   case ARM::t2STRi8:
454   case ARM::t2STRBi8:
455   case ARM::t2STRHi8:
456   case ARM::t2PLDi8:
457     return opcode;
458 
459   default:
460     break;
461   }
462 
463   return 0;
464 }
465 
466 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
467                                unsigned FrameReg, int &Offset,
468                                const ARMBaseInstrInfo &TII) {
469   unsigned Opcode = MI.getOpcode();
470   const MCInstrDesc &Desc = MI.getDesc();
471   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
472   bool isSub = false;
473 
474   // Memory operands in inline assembly always use AddrModeT2_i12.
475   if (Opcode == ARM::INLINEASM)
476     AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
477 
478   if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
479     Offset += MI.getOperand(FrameRegIdx+1).getImm();
480 
481     unsigned PredReg;
482     if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL) {
483       // Turn it into a move.
484       MI.setDesc(TII.get(ARM::tMOVr));
485       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
486       // Remove offset and remaining explicit predicate operands.
487       do MI.RemoveOperand(FrameRegIdx+1);
488       while (MI.getNumOperands() > FrameRegIdx+1);
489       MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
490       MIB.add(predOps(ARMCC::AL));
491       return true;
492     }
493 
494     bool HasCCOut = Opcode != ARM::t2ADDri12;
495 
496     if (Offset < 0) {
497       Offset = -Offset;
498       isSub = true;
499       MI.setDesc(TII.get(ARM::t2SUBri));
500     } else {
501       MI.setDesc(TII.get(ARM::t2ADDri));
502     }
503 
504     // Common case: small offset, fits into instruction.
505     if (ARM_AM::getT2SOImmVal(Offset) != -1) {
506       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
507       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
508       // Add cc_out operand if the original instruction did not have one.
509       if (!HasCCOut)
510         MI.addOperand(MachineOperand::CreateReg(0, false));
511       Offset = 0;
512       return true;
513     }
514     // Another common case: imm12.
515     if (Offset < 4096 &&
516         (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
517       unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
518       MI.setDesc(TII.get(NewOpc));
519       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
520       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
521       // Remove the cc_out operand.
522       if (HasCCOut)
523         MI.RemoveOperand(MI.getNumOperands()-1);
524       Offset = 0;
525       return true;
526     }
527 
528     // Otherwise, extract 8 adjacent bits from the immediate into this
529     // t2ADDri/t2SUBri.
530     unsigned RotAmt = countLeadingZeros<unsigned>(Offset);
531     unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
532 
533     // We will handle these bits from offset, clear them.
534     Offset &= ~ThisImmVal;
535 
536     assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
537            "Bit extraction didn't work?");
538     MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
539     // Add cc_out operand if the original instruction did not have one.
540     if (!HasCCOut)
541       MI.addOperand(MachineOperand::CreateReg(0, false));
542 
543   } else {
544 
545     // AddrMode4 and AddrMode6 cannot handle any offset.
546     if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
547       return false;
548 
549     // AddrModeT2_so cannot handle any offset. If there is no offset
550     // register then we change to an immediate version.
551     unsigned NewOpc = Opcode;
552     if (AddrMode == ARMII::AddrModeT2_so) {
553       unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
554       if (OffsetReg != 0) {
555         MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
556         return Offset == 0;
557       }
558 
559       MI.RemoveOperand(FrameRegIdx+1);
560       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
561       NewOpc = immediateOffsetOpcode(Opcode);
562       AddrMode = ARMII::AddrModeT2_i12;
563     }
564 
565     unsigned NumBits = 0;
566     unsigned Scale = 1;
567     if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
568       // i8 supports only negative, and i12 supports only positive, so
569       // based on Offset sign convert Opcode to the appropriate
570       // instruction
571       Offset += MI.getOperand(FrameRegIdx+1).getImm();
572       if (Offset < 0) {
573         NewOpc = negativeOffsetOpcode(Opcode);
574         NumBits = 8;
575         isSub = true;
576         Offset = -Offset;
577       } else {
578         NewOpc = positiveOffsetOpcode(Opcode);
579         NumBits = 12;
580       }
581     } else if (AddrMode == ARMII::AddrMode5) {
582       // VFP address mode.
583       const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
584       int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
585       if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
586         InstrOffs *= -1;
587       NumBits = 8;
588       Scale = 4;
589       Offset += InstrOffs * 4;
590       assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
591       if (Offset < 0) {
592         Offset = -Offset;
593         isSub = true;
594       }
595     } else if (AddrMode == ARMII::AddrModeT2_i8s4) {
596       Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
597       NumBits = 10; // 8 bits scaled by 4
598       // MCInst operand expects already scaled value.
599       Scale = 1;
600       assert((Offset & 3) == 0 && "Can't encode this offset!");
601     } else {
602       llvm_unreachable("Unsupported addressing mode!");
603     }
604 
605     if (NewOpc != Opcode)
606       MI.setDesc(TII.get(NewOpc));
607 
608     MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
609 
610     // Attempt to fold address computation
611     // Common case: small offset, fits into instruction.
612     int ImmedOffset = Offset / Scale;
613     unsigned Mask = (1 << NumBits) - 1;
614     if ((unsigned)Offset <= Mask * Scale) {
615       // Replace the FrameIndex with fp/sp
616       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
617       if (isSub) {
618         if (AddrMode == ARMII::AddrMode5)
619           // FIXME: Not consistent.
620           ImmedOffset |= 1 << NumBits;
621         else
622           ImmedOffset = -ImmedOffset;
623       }
624       ImmOp.ChangeToImmediate(ImmedOffset);
625       Offset = 0;
626       return true;
627     }
628 
629     // Otherwise, offset doesn't fit. Pull in what we can to simplify
630     ImmedOffset = ImmedOffset & Mask;
631     if (isSub) {
632       if (AddrMode == ARMII::AddrMode5)
633         // FIXME: Not consistent.
634         ImmedOffset |= 1 << NumBits;
635       else {
636         ImmedOffset = -ImmedOffset;
637         if (ImmedOffset == 0)
638           // Change the opcode back if the encoded offset is zero.
639           MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
640       }
641     }
642     ImmOp.ChangeToImmediate(ImmedOffset);
643     Offset &= ~(Mask*Scale);
644   }
645 
646   Offset = (isSub) ? -Offset : Offset;
647   return Offset == 0;
648 }
649 
650 ARMCC::CondCodes llvm::getITInstrPredicate(const MachineInstr &MI,
651                                            unsigned &PredReg) {
652   unsigned Opc = MI.getOpcode();
653   if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
654     return ARMCC::AL;
655   return getInstrPredicate(MI, PredReg);
656 }
657