1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Thumb2InstrInfo.h"
15 #include "ARM.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "Thumb2InstrInfo.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/Support/CommandLine.h"
27 
28 using namespace llvm;
29 
30 static cl::opt<bool>
31 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
32            cl::desc("Use old-style Thumb2 if-conversion heuristics"),
33            cl::init(false));
34 
35 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
36   : ARMBaseInstrInfo(STI), RI(*this, STI) {
37 }
38 
39 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
40   // FIXME
41   return 0;
42 }
43 
44 void
45 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
46                                          MachineBasicBlock *NewDest) const {
47   MachineBasicBlock *MBB = Tail->getParent();
48   ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
49   if (!AFI->hasITBlocks()) {
50     TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
51     return;
52   }
53 
54   // If the first instruction of Tail is predicated, we may have to update
55   // the IT instruction.
56   unsigned PredReg = 0;
57   ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg);
58   MachineBasicBlock::iterator MBBI = Tail;
59   if (CC != ARMCC::AL)
60     // Expecting at least the t2IT instruction before it.
61     --MBBI;
62 
63   // Actually replace the tail.
64   TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
65 
66   // Fix up IT.
67   if (CC != ARMCC::AL) {
68     MachineBasicBlock::iterator E = MBB->begin();
69     unsigned Count = 4; // At most 4 instructions in an IT block.
70     while (Count && MBBI != E) {
71       if (MBBI->isDebugValue()) {
72         --MBBI;
73         continue;
74       }
75       if (MBBI->getOpcode() == ARM::t2IT) {
76         unsigned Mask = MBBI->getOperand(1).getImm();
77         if (Count == 4)
78           MBBI->eraseFromParent();
79         else {
80           unsigned MaskOn = 1 << Count;
81           unsigned MaskOff = ~(MaskOn - 1);
82           MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
83         }
84         return;
85       }
86       --MBBI;
87       --Count;
88     }
89 
90     // Ctrl flow can reach here if branch folding is run before IT block
91     // formation pass.
92   }
93 }
94 
95 bool
96 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
97                                      MachineBasicBlock::iterator MBBI) const {
98   while (MBBI->isDebugValue()) {
99     ++MBBI;
100     if (MBBI == MBB.end())
101       return false;
102   }
103 
104   unsigned PredReg = 0;
105   return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
106 }
107 
108 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
109                                   MachineBasicBlock::iterator I, DebugLoc DL,
110                                   unsigned DestReg, unsigned SrcReg,
111                                   bool KillSrc) const {
112   // Handle SPR, DPR, and QPR copies.
113   if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
114     return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
115 
116   bool tDest = ARM::tGPRRegClass.contains(DestReg);
117   bool tSrc  = ARM::tGPRRegClass.contains(SrcReg);
118   unsigned Opc = ARM::tMOVgpr2gpr;
119   if (tDest && tSrc)
120     Opc = ARM::tMOVr;
121   else if (tSrc)
122     Opc = ARM::tMOVtgpr2gpr;
123   else if (tDest)
124     Opc = ARM::tMOVgpr2tgpr;
125 
126   BuildMI(MBB, I, DL, get(Opc), DestReg)
127     .addReg(SrcReg, getKillRegState(KillSrc));
128 }
129 
130 void Thumb2InstrInfo::
131 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
132                     unsigned SrcReg, bool isKill, int FI,
133                     const TargetRegisterClass *RC,
134                     const TargetRegisterInfo *TRI) const {
135   if (RC == ARM::GPRRegisterClass   || RC == ARM::tGPRRegisterClass ||
136       RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
137     DebugLoc DL;
138     if (I != MBB.end()) DL = I->getDebugLoc();
139 
140     MachineFunction &MF = *MBB.getParent();
141     MachineFrameInfo &MFI = *MF.getFrameInfo();
142     MachineMemOperand *MMO =
143       MF.getMachineMemOperand(
144                       MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
145                               MachineMemOperand::MOStore,
146                               MFI.getObjectSize(FI),
147                               MFI.getObjectAlignment(FI));
148     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
149                    .addReg(SrcReg, getKillRegState(isKill))
150                    .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
151     return;
152   }
153 
154   ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
155 }
156 
157 void Thumb2InstrInfo::
158 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
159                      unsigned DestReg, int FI,
160                      const TargetRegisterClass *RC,
161                      const TargetRegisterInfo *TRI) const {
162   if (RC == ARM::GPRRegisterClass   || RC == ARM::tGPRRegisterClass ||
163       RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
164     DebugLoc DL;
165     if (I != MBB.end()) DL = I->getDebugLoc();
166 
167     MachineFunction &MF = *MBB.getParent();
168     MachineFrameInfo &MFI = *MF.getFrameInfo();
169     MachineMemOperand *MMO =
170       MF.getMachineMemOperand(
171                       MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
172                               MachineMemOperand::MOLoad,
173                               MFI.getObjectSize(FI),
174                               MFI.getObjectAlignment(FI));
175     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
176                    .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
177     return;
178   }
179 
180   ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
181 }
182 
183 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
184                                MachineBasicBlock::iterator &MBBI, DebugLoc dl,
185                                unsigned DestReg, unsigned BaseReg, int NumBytes,
186                                ARMCC::CondCodes Pred, unsigned PredReg,
187                                const ARMBaseInstrInfo &TII, unsigned MIFlags) {
188   bool isSub = NumBytes < 0;
189   if (isSub) NumBytes = -NumBytes;
190 
191   // If profitable, use a movw or movt to materialize the offset.
192   // FIXME: Use the scavenger to grab a scratch register.
193   if (DestReg != ARM::SP && DestReg != BaseReg &&
194       NumBytes >= 4096 &&
195       ARM_AM::getT2SOImmVal(NumBytes) == -1) {
196     bool Fits = false;
197     if (NumBytes < 65536) {
198       // Use a movw to materialize the 16-bit constant.
199       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
200         .addImm(NumBytes)
201         .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
202       Fits = true;
203     } else if ((NumBytes & 0xffff) == 0) {
204       // Use a movt to materialize the 32-bit constant.
205       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
206         .addReg(DestReg)
207         .addImm(NumBytes >> 16)
208         .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
209       Fits = true;
210     }
211 
212     if (Fits) {
213       if (isSub) {
214         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
215           .addReg(BaseReg, RegState::Kill)
216           .addReg(DestReg, RegState::Kill)
217           .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
218           .setMIFlags(MIFlags);
219       } else {
220         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
221           .addReg(DestReg, RegState::Kill)
222           .addReg(BaseReg, RegState::Kill)
223           .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
224           .setMIFlags(MIFlags);
225       }
226       return;
227     }
228   }
229 
230   while (NumBytes) {
231     unsigned ThisVal = NumBytes;
232     unsigned Opc = 0;
233     if (DestReg == ARM::SP && BaseReg != ARM::SP) {
234       // mov sp, rn. Note t2MOVr cannot be used.
235       BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg)
236         .addReg(BaseReg).setMIFlags(MIFlags);
237       BaseReg = ARM::SP;
238       continue;
239     }
240 
241     bool HasCCOut = true;
242     if (BaseReg == ARM::SP) {
243       // sub sp, sp, #imm7
244       if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
245         assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
246         Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
247         // FIXME: Fix Thumb1 immediate encoding.
248         BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
249           .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags);
250         NumBytes = 0;
251         continue;
252       }
253 
254       // sub rd, sp, so_imm
255       Opc = isSub ? ARM::t2SUBrSPi : ARM::t2ADDrSPi;
256       if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
257         NumBytes = 0;
258       } else {
259         // FIXME: Move this to ARMAddressingModes.h?
260         unsigned RotAmt = CountLeadingZeros_32(ThisVal);
261         ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
262         NumBytes &= ~ThisVal;
263         assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
264                "Bit extraction didn't work?");
265       }
266     } else {
267       assert(DestReg != ARM::SP && BaseReg != ARM::SP);
268       Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
269       if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
270         NumBytes = 0;
271       } else if (ThisVal < 4096) {
272         Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
273         HasCCOut = false;
274         NumBytes = 0;
275       } else {
276         // FIXME: Move this to ARMAddressingModes.h?
277         unsigned RotAmt = CountLeadingZeros_32(ThisVal);
278         ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
279         NumBytes &= ~ThisVal;
280         assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
281                "Bit extraction didn't work?");
282       }
283     }
284 
285     // Build the new ADD / SUB.
286     MachineInstrBuilder MIB =
287       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
288                      .addReg(BaseReg, RegState::Kill)
289                      .addImm(ThisVal)).setMIFlags(MIFlags);
290     if (HasCCOut)
291       AddDefaultCC(MIB);
292 
293     BaseReg = DestReg;
294   }
295 }
296 
297 static unsigned
298 negativeOffsetOpcode(unsigned opcode)
299 {
300   switch (opcode) {
301   case ARM::t2LDRi12:   return ARM::t2LDRi8;
302   case ARM::t2LDRHi12:  return ARM::t2LDRHi8;
303   case ARM::t2LDRBi12:  return ARM::t2LDRBi8;
304   case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
305   case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
306   case ARM::t2STRi12:   return ARM::t2STRi8;
307   case ARM::t2STRBi12:  return ARM::t2STRBi8;
308   case ARM::t2STRHi12:  return ARM::t2STRHi8;
309 
310   case ARM::t2LDRi8:
311   case ARM::t2LDRHi8:
312   case ARM::t2LDRBi8:
313   case ARM::t2LDRSHi8:
314   case ARM::t2LDRSBi8:
315   case ARM::t2STRi8:
316   case ARM::t2STRBi8:
317   case ARM::t2STRHi8:
318     return opcode;
319 
320   default:
321     break;
322   }
323 
324   return 0;
325 }
326 
327 static unsigned
328 positiveOffsetOpcode(unsigned opcode)
329 {
330   switch (opcode) {
331   case ARM::t2LDRi8:   return ARM::t2LDRi12;
332   case ARM::t2LDRHi8:  return ARM::t2LDRHi12;
333   case ARM::t2LDRBi8:  return ARM::t2LDRBi12;
334   case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
335   case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
336   case ARM::t2STRi8:   return ARM::t2STRi12;
337   case ARM::t2STRBi8:  return ARM::t2STRBi12;
338   case ARM::t2STRHi8:  return ARM::t2STRHi12;
339 
340   case ARM::t2LDRi12:
341   case ARM::t2LDRHi12:
342   case ARM::t2LDRBi12:
343   case ARM::t2LDRSHi12:
344   case ARM::t2LDRSBi12:
345   case ARM::t2STRi12:
346   case ARM::t2STRBi12:
347   case ARM::t2STRHi12:
348     return opcode;
349 
350   default:
351     break;
352   }
353 
354   return 0;
355 }
356 
357 static unsigned
358 immediateOffsetOpcode(unsigned opcode)
359 {
360   switch (opcode) {
361   case ARM::t2LDRs:   return ARM::t2LDRi12;
362   case ARM::t2LDRHs:  return ARM::t2LDRHi12;
363   case ARM::t2LDRBs:  return ARM::t2LDRBi12;
364   case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
365   case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
366   case ARM::t2STRs:   return ARM::t2STRi12;
367   case ARM::t2STRBs:  return ARM::t2STRBi12;
368   case ARM::t2STRHs:  return ARM::t2STRHi12;
369 
370   case ARM::t2LDRi12:
371   case ARM::t2LDRHi12:
372   case ARM::t2LDRBi12:
373   case ARM::t2LDRSHi12:
374   case ARM::t2LDRSBi12:
375   case ARM::t2STRi12:
376   case ARM::t2STRBi12:
377   case ARM::t2STRHi12:
378   case ARM::t2LDRi8:
379   case ARM::t2LDRHi8:
380   case ARM::t2LDRBi8:
381   case ARM::t2LDRSHi8:
382   case ARM::t2LDRSBi8:
383   case ARM::t2STRi8:
384   case ARM::t2STRBi8:
385   case ARM::t2STRHi8:
386     return opcode;
387 
388   default:
389     break;
390   }
391 
392   return 0;
393 }
394 
395 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
396                                unsigned FrameReg, int &Offset,
397                                const ARMBaseInstrInfo &TII) {
398   unsigned Opcode = MI.getOpcode();
399   const TargetInstrDesc &Desc = MI.getDesc();
400   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
401   bool isSub = false;
402 
403   // Memory operands in inline assembly always use AddrModeT2_i12.
404   if (Opcode == ARM::INLINEASM)
405     AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
406 
407   if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
408     Offset += MI.getOperand(FrameRegIdx+1).getImm();
409 
410     unsigned PredReg;
411     if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
412       // Turn it into a move.
413       MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
414       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
415       // Remove offset and remaining explicit predicate operands.
416       do MI.RemoveOperand(FrameRegIdx+1);
417       while (MI.getNumOperands() > FrameRegIdx+1 &&
418              (!MI.getOperand(FrameRegIdx+1).isReg() ||
419               !MI.getOperand(FrameRegIdx+1).isImm()));
420       return true;
421     }
422 
423     bool isSP = FrameReg == ARM::SP;
424     bool HasCCOut = Opcode != ARM::t2ADDri12;
425 
426     if (Offset < 0) {
427       Offset = -Offset;
428       isSub = true;
429       MI.setDesc(TII.get(isSP ? ARM::t2SUBrSPi : ARM::t2SUBri));
430     } else {
431       MI.setDesc(TII.get(isSP ? ARM::t2ADDrSPi : ARM::t2ADDri));
432     }
433 
434     // Common case: small offset, fits into instruction.
435     if (ARM_AM::getT2SOImmVal(Offset) != -1) {
436       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
437       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
438       // Add cc_out operand if the original instruction did not have one.
439       if (!HasCCOut)
440         MI.addOperand(MachineOperand::CreateReg(0, false));
441       Offset = 0;
442       return true;
443     }
444     // Another common case: imm12.
445     if (Offset < 4096 &&
446         (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
447       unsigned NewOpc = isSP
448         ? (isSub ? ARM::t2SUBrSPi12 : ARM::t2ADDrSPi12)
449         : (isSub ? ARM::t2SUBri12   : ARM::t2ADDri12);
450       MI.setDesc(TII.get(NewOpc));
451       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
452       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
453       // Remove the cc_out operand.
454       if (HasCCOut)
455         MI.RemoveOperand(MI.getNumOperands()-1);
456       Offset = 0;
457       return true;
458     }
459 
460     // Otherwise, extract 8 adjacent bits from the immediate into this
461     // t2ADDri/t2SUBri.
462     unsigned RotAmt = CountLeadingZeros_32(Offset);
463     unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
464 
465     // We will handle these bits from offset, clear them.
466     Offset &= ~ThisImmVal;
467 
468     assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
469            "Bit extraction didn't work?");
470     MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
471     // Add cc_out operand if the original instruction did not have one.
472     if (!HasCCOut)
473       MI.addOperand(MachineOperand::CreateReg(0, false));
474 
475   } else {
476 
477     // AddrMode4 and AddrMode6 cannot handle any offset.
478     if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
479       return false;
480 
481     // AddrModeT2_so cannot handle any offset. If there is no offset
482     // register then we change to an immediate version.
483     unsigned NewOpc = Opcode;
484     if (AddrMode == ARMII::AddrModeT2_so) {
485       unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
486       if (OffsetReg != 0) {
487         MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
488         return Offset == 0;
489       }
490 
491       MI.RemoveOperand(FrameRegIdx+1);
492       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
493       NewOpc = immediateOffsetOpcode(Opcode);
494       AddrMode = ARMII::AddrModeT2_i12;
495     }
496 
497     unsigned NumBits = 0;
498     unsigned Scale = 1;
499     if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
500       // i8 supports only negative, and i12 supports only positive, so
501       // based on Offset sign convert Opcode to the appropriate
502       // instruction
503       Offset += MI.getOperand(FrameRegIdx+1).getImm();
504       if (Offset < 0) {
505         NewOpc = negativeOffsetOpcode(Opcode);
506         NumBits = 8;
507         isSub = true;
508         Offset = -Offset;
509       } else {
510         NewOpc = positiveOffsetOpcode(Opcode);
511         NumBits = 12;
512       }
513     } else if (AddrMode == ARMII::AddrMode5) {
514       // VFP address mode.
515       const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
516       int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
517       if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
518         InstrOffs *= -1;
519       NumBits = 8;
520       Scale = 4;
521       Offset += InstrOffs * 4;
522       assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
523       if (Offset < 0) {
524         Offset = -Offset;
525         isSub = true;
526       }
527     } else {
528       llvm_unreachable("Unsupported addressing mode!");
529     }
530 
531     if (NewOpc != Opcode)
532       MI.setDesc(TII.get(NewOpc));
533 
534     MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
535 
536     // Attempt to fold address computation
537     // Common case: small offset, fits into instruction.
538     int ImmedOffset = Offset / Scale;
539     unsigned Mask = (1 << NumBits) - 1;
540     if ((unsigned)Offset <= Mask * Scale) {
541       // Replace the FrameIndex with fp/sp
542       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
543       if (isSub) {
544         if (AddrMode == ARMII::AddrMode5)
545           // FIXME: Not consistent.
546           ImmedOffset |= 1 << NumBits;
547         else
548           ImmedOffset = -ImmedOffset;
549       }
550       ImmOp.ChangeToImmediate(ImmedOffset);
551       Offset = 0;
552       return true;
553     }
554 
555     // Otherwise, offset doesn't fit. Pull in what we can to simplify
556     ImmedOffset = ImmedOffset & Mask;
557     if (isSub) {
558       if (AddrMode == ARMII::AddrMode5)
559         // FIXME: Not consistent.
560         ImmedOffset |= 1 << NumBits;
561       else {
562         ImmedOffset = -ImmedOffset;
563         if (ImmedOffset == 0)
564           // Change the opcode back if the encoded offset is zero.
565           MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
566       }
567     }
568     ImmOp.ChangeToImmediate(ImmedOffset);
569     Offset &= ~(Mask*Scale);
570   }
571 
572   Offset = (isSub) ? -Offset : Offset;
573   return Offset == 0;
574 }
575 
576 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
577 /// two-addrss instruction inserted by two-address pass.
578 void
579 Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
580                                        MachineInstr *UseMI,
581                                        const TargetRegisterInfo &TRI) const {
582   if (SrcMI->getOpcode() != ARM::tMOVgpr2gpr ||
583       SrcMI->getOperand(1).isKill())
584     return;
585 
586   unsigned PredReg = 0;
587   ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg);
588   if (CC == ARMCC::AL || PredReg != ARM::CPSR)
589     return;
590 
591   // Schedule the copy so it doesn't come between previous instructions
592   // and UseMI which can form an IT block.
593   unsigned SrcReg = SrcMI->getOperand(1).getReg();
594   ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
595   MachineBasicBlock *MBB = UseMI->getParent();
596   MachineBasicBlock::iterator MBBI = SrcMI;
597   unsigned NumInsts = 0;
598   while (--MBBI != MBB->begin()) {
599     if (MBBI->isDebugValue())
600       continue;
601 
602     MachineInstr *NMI = &*MBBI;
603     ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg);
604     if (!(NCC == CC || NCC == OCC) ||
605         NMI->modifiesRegister(SrcReg, &TRI) ||
606         NMI->definesRegister(ARM::CPSR))
607       break;
608     if (++NumInsts == 4)
609       // Too many in a row!
610       return;
611   }
612 
613   if (NumInsts) {
614     MBB->remove(SrcMI);
615     MBB->insert(++MBBI, SrcMI);
616   }
617 }
618 
619 ARMCC::CondCodes
620 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
621   unsigned Opc = MI->getOpcode();
622   if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
623     return ARMCC::AL;
624   return llvm::getInstrPredicate(MI, PredReg);
625 }
626