1 //===-- Thumb2ITBlockPass.cpp - Insert Thumb-2 IT blocks ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #define DEBUG_TYPE "thumb2-it"
11 #include "ARM.h"
12 #include "ARMMachineFunctionInfo.h"
13 #include "Thumb2InstrInfo.h"
14 #include "llvm/ADT/SmallSet.h"
15 #include "llvm/ADT/Statistic.h"
16 #include "llvm/CodeGen/MachineFunctionPass.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineInstrBundle.h"
20 using namespace llvm;
21 
22 STATISTIC(NumITs,        "Number of IT blocks inserted");
23 STATISTIC(NumMovedInsts, "Number of predicated instructions moved");
24 
25 namespace {
26   class Thumb2ITBlockPass : public MachineFunctionPass {
27   public:
28     static char ID;
29     Thumb2ITBlockPass() : MachineFunctionPass(ID) {}
30 
31     bool hasV8Ops;
32     const Thumb2InstrInfo *TII;
33     const TargetRegisterInfo *TRI;
34     ARMFunctionInfo *AFI;
35 
36     virtual bool runOnMachineFunction(MachineFunction &Fn);
37 
38     virtual const char *getPassName() const {
39       return "Thumb IT blocks insertion pass";
40     }
41 
42   private:
43     bool MoveCopyOutOfITBlock(MachineInstr *MI,
44                               ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
45                               SmallSet<unsigned, 4> &Defs,
46                               SmallSet<unsigned, 4> &Uses);
47     bool InsertITInstructions(MachineBasicBlock &MBB);
48   };
49   char Thumb2ITBlockPass::ID = 0;
50 }
51 
52 /// TrackDefUses - Tracking what registers are being defined and used by
53 /// instructions in the IT block. This also tracks "dependencies", i.e. uses
54 /// in the IT block that are defined before the IT instruction.
55 static void TrackDefUses(MachineInstr *MI,
56                          SmallSet<unsigned, 4> &Defs,
57                          SmallSet<unsigned, 4> &Uses,
58                          const TargetRegisterInfo *TRI) {
59   SmallVector<unsigned, 4> LocalDefs;
60   SmallVector<unsigned, 4> LocalUses;
61 
62   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
63     MachineOperand &MO = MI->getOperand(i);
64     if (!MO.isReg())
65       continue;
66     unsigned Reg = MO.getReg();
67     if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
68       continue;
69     if (MO.isUse())
70       LocalUses.push_back(Reg);
71     else
72       LocalDefs.push_back(Reg);
73   }
74 
75   for (unsigned i = 0, e = LocalUses.size(); i != e; ++i) {
76     unsigned Reg = LocalUses[i];
77     for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true);
78          Subreg.isValid(); ++Subreg)
79       Uses.insert(*Subreg);
80   }
81 
82   for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) {
83     unsigned Reg = LocalDefs[i];
84     for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true);
85          Subreg.isValid(); ++Subreg)
86       Defs.insert(*Subreg);
87     if (Reg == ARM::CPSR)
88       continue;
89   }
90 }
91 
92 static bool isCopy(MachineInstr *MI) {
93   switch (MI->getOpcode()) {
94   default:
95     return false;
96   case ARM::MOVr:
97   case ARM::MOVr_TC:
98   case ARM::tMOVr:
99   case ARM::t2MOVr:
100     return true;
101   }
102 }
103 
104 bool
105 Thumb2ITBlockPass::MoveCopyOutOfITBlock(MachineInstr *MI,
106                                       ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
107                                         SmallSet<unsigned, 4> &Defs,
108                                         SmallSet<unsigned, 4> &Uses) {
109   if (!isCopy(MI))
110     return false;
111   // llvm models select's as two-address instructions. That means a copy
112   // is inserted before a t2MOVccr, etc. If the copy is scheduled in
113   // between selects we would end up creating multiple IT blocks.
114   assert(MI->getOperand(0).getSubReg() == 0 &&
115          MI->getOperand(1).getSubReg() == 0 &&
116          "Sub-register indices still around?");
117 
118   unsigned DstReg = MI->getOperand(0).getReg();
119   unsigned SrcReg = MI->getOperand(1).getReg();
120 
121   // First check if it's safe to move it.
122   if (Uses.count(DstReg) || Defs.count(SrcReg))
123     return false;
124 
125   // If the CPSR is defined by this copy, then we don't want to move it. E.g.,
126   // if we have:
127   //
128   //   movs  r1, r1
129   //   rsb   r1, 0
130   //   movs  r2, r2
131   //   rsb   r2, 0
132   //
133   // we don't want this to be converted to:
134   //
135   //   movs  r1, r1
136   //   movs  r2, r2
137   //   itt   mi
138   //   rsb   r1, 0
139   //   rsb   r2, 0
140   //
141   const MCInstrDesc &MCID = MI->getDesc();
142   if (MI->hasOptionalDef() &&
143       MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
144     return false;
145 
146   // Then peek at the next instruction to see if it's predicated on CC or OCC.
147   // If not, then there is nothing to be gained by moving the copy.
148   MachineBasicBlock::iterator I = MI; ++I;
149   MachineBasicBlock::iterator E = MI->getParent()->end();
150   while (I != E && I->isDebugValue())
151     ++I;
152   if (I != E) {
153     unsigned NPredReg = 0;
154     ARMCC::CondCodes NCC = getITInstrPredicate(I, NPredReg);
155     if (NCC == CC || NCC == OCC)
156       return true;
157   }
158   return false;
159 }
160 
161 bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) {
162   bool Modified = false;
163 
164   SmallSet<unsigned, 4> Defs;
165   SmallSet<unsigned, 4> Uses;
166   MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
167   while (MBBI != E) {
168     MachineInstr *MI = &*MBBI;
169     DebugLoc dl = MI->getDebugLoc();
170     unsigned PredReg = 0;
171     ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
172     if (CC == ARMCC::AL) {
173       ++MBBI;
174       continue;
175     }
176 
177     Defs.clear();
178     Uses.clear();
179     TrackDefUses(MI, Defs, Uses, TRI);
180 
181     // Insert an IT instruction.
182     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
183       .addImm(CC);
184 
185     // Add implicit use of ITSTATE to IT block instructions.
186     MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
187                                              true/*isImp*/, false/*isKill*/));
188 
189     MachineInstr *LastITMI = MI;
190     MachineBasicBlock::iterator InsertPos = MIB;
191     ++MBBI;
192 
193     // Form IT block.
194     ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
195     unsigned Mask = 0, Pos = 3;
196 
197     // v8 IT blocks are limited to one conditional op: skip the loop
198     if (!hasV8Ops) {
199       // Branches, including tricky ones like LDM_RET, need to end an IT
200       // block so check the instruction we just put in the block.
201       for (; MBBI != E && Pos &&
202              (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) {
203         if (MBBI->isDebugValue())
204           continue;
205 
206         MachineInstr *NMI = &*MBBI;
207         MI = NMI;
208 
209         unsigned NPredReg = 0;
210         ARMCC::CondCodes NCC = getITInstrPredicate(NMI, NPredReg);
211         if (NCC == CC || NCC == OCC) {
212           Mask |= (NCC & 1) << Pos;
213           // Add implicit use of ITSTATE.
214           NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
215                                                  true/*isImp*/, false/*isKill*/));
216           LastITMI = NMI;
217         } else {
218           if (NCC == ARMCC::AL &&
219               MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
220             --MBBI;
221             MBB.remove(NMI);
222             MBB.insert(InsertPos, NMI);
223             ++NumMovedInsts;
224             continue;
225           }
226           break;
227         }
228         TrackDefUses(NMI, Defs, Uses, TRI);
229         --Pos;
230       }
231     }
232 
233     // Finalize IT mask.
234     Mask |= (1 << Pos);
235     // Tag along (firstcond[0] << 4) with the mask.
236     Mask |= (CC & 1) << 4;
237     MIB.addImm(Mask);
238 
239     // Last instruction in IT block kills ITSTATE.
240     LastITMI->findRegisterUseOperand(ARM::ITSTATE)->setIsKill();
241 
242     // Finalize the bundle.
243     MachineBasicBlock::instr_iterator LI = LastITMI;
244     finalizeBundle(MBB, InsertPos.getInstrIterator(), llvm::next(LI));
245 
246     Modified = true;
247     ++NumITs;
248   }
249 
250   return Modified;
251 }
252 
253 bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) {
254   const TargetMachine &TM = Fn.getTarget();
255   AFI = Fn.getInfo<ARMFunctionInfo>();
256   TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
257   TRI = TM.getRegisterInfo();
258   hasV8Ops = TM.getSubtarget<ARMSubtarget>().hasV8Ops();
259 
260   if (!AFI->isThumbFunction())
261     return false;
262 
263   bool Modified = false;
264   for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E; ) {
265     MachineBasicBlock &MBB = *MFI;
266     ++MFI;
267     Modified |= InsertITInstructions(MBB);
268   }
269 
270   if (Modified)
271     AFI->setHasITBlocks(true);
272 
273   return Modified;
274 }
275 
276 /// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks
277 /// insertion pass.
278 FunctionPass *llvm::createThumb2ITBlockPass() {
279   return new Thumb2ITBlockPass();
280 }
281