1 //===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMSubtarget.h"
15 #include "Thumb1InstrInfo.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineMemOperand.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/MC/MCInst.h"
21 
22 using namespace llvm;
23 
24 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
25   : ARMBaseInstrInfo(STI), RI(STI) {
26 }
27 
28 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
29 void Thumb1InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
30   NopInst.setOpcode(ARM::tMOVr);
31   NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
32   NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
33   NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
34   NopInst.addOperand(MCOperand::CreateReg(0));
35 }
36 
37 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
38   return 0;
39 }
40 
41 void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
42                                   MachineBasicBlock::iterator I, DebugLoc DL,
43                                   unsigned DestReg, unsigned SrcReg,
44                                   bool KillSrc) const {
45   // Need to check the arch.
46   MachineFunction &MF = *MBB.getParent();
47   const ARMSubtarget &st = MF.getTarget().getSubtarget<ARMSubtarget>();
48 
49   assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
50          "Thumb1 can only copy GPR registers");
51 
52   if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg)
53       || !ARM::tGPRRegClass.contains(DestReg))
54     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
55       .addReg(SrcReg, getKillRegState(KillSrc)));
56   else {
57     // FIXME: The performance consequences of this are going to be atrocious.
58     // Some things to try that should be better:
59     //   * 'mov hi, $src; mov $dst, hi', with hi as either r10 or r11
60     //   * 'movs $dst, $src' if cpsr isn't live
61     // See: http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-August/075998.html
62 
63     // 'MOV lo, lo' is unpredictable on < v6, so use the stack to do it
64     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tPUSH)))
65       .addReg(SrcReg, getKillRegState(KillSrc));
66     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tPOP)))
67       .addReg(DestReg, getDefRegState(true));
68   }
69 }
70 
71 void Thumb1InstrInfo::
72 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
73                     unsigned SrcReg, bool isKill, int FI,
74                     const TargetRegisterClass *RC,
75                     const TargetRegisterInfo *TRI) const {
76   assert((RC == &ARM::tGPRRegClass ||
77           (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
78            isARMLowRegister(SrcReg))) && "Unknown regclass!");
79 
80   if (RC == &ARM::tGPRRegClass ||
81       (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
82        isARMLowRegister(SrcReg))) {
83     DebugLoc DL;
84     if (I != MBB.end()) DL = I->getDebugLoc();
85 
86     MachineFunction &MF = *MBB.getParent();
87     MachineFrameInfo &MFI = *MF.getFrameInfo();
88     MachineMemOperand *MMO =
89       MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
90                               MachineMemOperand::MOStore,
91                               MFI.getObjectSize(FI),
92                               MFI.getObjectAlignment(FI));
93     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi))
94                    .addReg(SrcReg, getKillRegState(isKill))
95                    .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
96   }
97 }
98 
99 void Thumb1InstrInfo::
100 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
101                      unsigned DestReg, int FI,
102                      const TargetRegisterClass *RC,
103                      const TargetRegisterInfo *TRI) const {
104   assert((RC == &ARM::tGPRRegClass ||
105           (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
106            isARMLowRegister(DestReg))) && "Unknown regclass!");
107 
108   if (RC == &ARM::tGPRRegClass ||
109       (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
110        isARMLowRegister(DestReg))) {
111     DebugLoc DL;
112     if (I != MBB.end()) DL = I->getDebugLoc();
113 
114     MachineFunction &MF = *MBB.getParent();
115     MachineFrameInfo &MFI = *MF.getFrameInfo();
116     MachineMemOperand *MMO =
117       MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
118                               MachineMemOperand::MOLoad,
119                               MFI.getObjectSize(FI),
120                               MFI.getObjectAlignment(FI));
121     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
122                    .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
123   }
124 }
125 
126 void
127 Thumb1InstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI,
128                                       Reloc::Model RM) const {
129   if (RM == Reloc::PIC_)
130     expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_pcrel, ARM::tLDRi, RM);
131   else
132     expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_abs, ARM::tLDRi, RM);
133 }
134