1 //===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "ARMSubtarget.h" 15 #include "Thumb1InstrInfo.h" 16 #include "llvm/CodeGen/MachineFrameInfo.h" 17 #include "llvm/CodeGen/MachineInstrBuilder.h" 18 #include "llvm/CodeGen/MachineMemOperand.h" 19 #include "llvm/CodeGen/MachineRegisterInfo.h" 20 #include "llvm/MC/MCInst.h" 21 22 using namespace llvm; 23 24 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) 25 : ARMBaseInstrInfo(STI), RI() {} 26 27 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 28 void Thumb1InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { 29 NopInst.setOpcode(ARM::tMOVr); 30 NopInst.addOperand(MCOperand::createReg(ARM::R8)); 31 NopInst.addOperand(MCOperand::createReg(ARM::R8)); 32 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); 33 NopInst.addOperand(MCOperand::createReg(0)); 34 } 35 36 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const { 37 return 0; 38 } 39 40 void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 41 MachineBasicBlock::iterator I, 42 const DebugLoc &DL, unsigned DestReg, 43 unsigned SrcReg, bool KillSrc) const { 44 // Need to check the arch. 45 MachineFunction &MF = *MBB.getParent(); 46 const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>(); 47 48 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && 49 "Thumb1 can only copy GPR registers"); 50 51 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg) 52 || !ARM::tGPRRegClass.contains(DestReg)) 53 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) 54 .addReg(SrcReg, getKillRegState(KillSrc)) 55 .add(predOps(ARMCC::AL)); 56 else { 57 // FIXME: The performance consequences of this are going to be atrocious. 58 // Some things to try that should be better: 59 // * 'mov hi, $src; mov $dst, hi', with hi as either r10 or r11 60 // * 'movs $dst, $src' if cpsr isn't live 61 // See: http://lists.llvm.org/pipermail/llvm-dev/2014-August/075998.html 62 63 // 'MOV lo, lo' is unpredictable on < v6, so use the stack to do it 64 BuildMI(MBB, I, DL, get(ARM::tPUSH)) 65 .add(predOps(ARMCC::AL)) 66 .addReg(SrcReg, getKillRegState(KillSrc)); 67 BuildMI(MBB, I, DL, get(ARM::tPOP)) 68 .add(predOps(ARMCC::AL)) 69 .addReg(DestReg, getDefRegState(true)); 70 } 71 } 72 73 void Thumb1InstrInfo:: 74 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 75 unsigned SrcReg, bool isKill, int FI, 76 const TargetRegisterClass *RC, 77 const TargetRegisterInfo *TRI) const { 78 assert((RC == &ARM::tGPRRegClass || 79 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && 80 isARMLowRegister(SrcReg))) && "Unknown regclass!"); 81 82 if (RC == &ARM::tGPRRegClass || 83 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && 84 isARMLowRegister(SrcReg))) { 85 DebugLoc DL; 86 if (I != MBB.end()) DL = I->getDebugLoc(); 87 88 MachineFunction &MF = *MBB.getParent(); 89 MachineFrameInfo &MFI = MF.getFrameInfo(); 90 MachineMemOperand *MMO = MF.getMachineMemOperand( 91 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore, 92 MFI.getObjectSize(FI), MFI.getObjectAlignment(FI)); 93 BuildMI(MBB, I, DL, get(ARM::tSTRspi)) 94 .addReg(SrcReg, getKillRegState(isKill)) 95 .addFrameIndex(FI) 96 .addImm(0) 97 .addMemOperand(MMO) 98 .add(predOps(ARMCC::AL)); 99 } 100 } 101 102 void Thumb1InstrInfo:: 103 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 104 unsigned DestReg, int FI, 105 const TargetRegisterClass *RC, 106 const TargetRegisterInfo *TRI) const { 107 assert((RC == &ARM::tGPRRegClass || 108 (TargetRegisterInfo::isPhysicalRegister(DestReg) && 109 isARMLowRegister(DestReg))) && "Unknown regclass!"); 110 111 if (RC == &ARM::tGPRRegClass || 112 (TargetRegisterInfo::isPhysicalRegister(DestReg) && 113 isARMLowRegister(DestReg))) { 114 DebugLoc DL; 115 if (I != MBB.end()) DL = I->getDebugLoc(); 116 117 MachineFunction &MF = *MBB.getParent(); 118 MachineFrameInfo &MFI = MF.getFrameInfo(); 119 MachineMemOperand *MMO = MF.getMachineMemOperand( 120 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad, 121 MFI.getObjectSize(FI), MFI.getObjectAlignment(FI)); 122 BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg) 123 .addFrameIndex(FI) 124 .addImm(0) 125 .addMemOperand(MMO) 126 .add(predOps(ARMCC::AL)); 127 } 128 } 129 130 void Thumb1InstrInfo::expandLoadStackGuard( 131 MachineBasicBlock::iterator MI) const { 132 MachineFunction &MF = *MI->getParent()->getParent(); 133 const TargetMachine &TM = MF.getTarget(); 134 if (TM.isPositionIndependent()) 135 expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_pcrel, ARM::tLDRi); 136 else 137 expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_abs, ARM::tLDRi); 138 } 139