1 //===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Thumb1 implementation of TargetFrameLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Thumb1FrameLowering.h"
15 #include "ARMMachineFunctionInfo.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineModuleInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 
22 using namespace llvm;
23 
24 bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{
25   const MachineFrameInfo *FFI = MF.getFrameInfo();
26   unsigned CFSize = FFI->getMaxCallFrameSize();
27   // It's not always a good idea to include the call frame as part of the
28   // stack frame. ARM (especially Thumb) has small immediate offset to
29   // address the stack frame. So a large call frame can cause poor codegen
30   // and may even makes it impossible to scavenge a register.
31   if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
32     return false;
33 
34   return !MF.getFrameInfo()->hasVarSizedObjects();
35 }
36 
37 static void
38 emitSPUpdate(MachineBasicBlock &MBB,
39              MachineBasicBlock::iterator &MBBI,
40              const TargetInstrInfo &TII, DebugLoc dl,
41              const Thumb1RegisterInfo &MRI,
42              int NumBytes, unsigned MIFlags = MachineInstr::NoFlags)  {
43   emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
44                             MRI, MIFlags);
45 }
46 
47 
48 void Thumb1FrameLowering::
49 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
50                               MachineBasicBlock::iterator I) const {
51   const Thumb1InstrInfo &TII =
52     *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo());
53   const Thumb1RegisterInfo *RegInfo =
54     static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo());
55   if (!hasReservedCallFrame(MF)) {
56     // If we have alloca, convert as follows:
57     // ADJCALLSTACKDOWN -> sub, sp, sp, amount
58     // ADJCALLSTACKUP   -> add, sp, sp, amount
59     MachineInstr *Old = I;
60     DebugLoc dl = Old->getDebugLoc();
61     unsigned Amount = Old->getOperand(0).getImm();
62     if (Amount != 0) {
63       // We need to keep the stack aligned properly.  To do this, we round the
64       // amount of space needed for the outgoing arguments up to the next
65       // alignment boundary.
66       unsigned Align = getStackAlignment();
67       Amount = (Amount+Align-1)/Align*Align;
68 
69       // Replace the pseudo instruction with a new instruction...
70       unsigned Opc = Old->getOpcode();
71       if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
72         emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
73       } else {
74         assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
75         emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
76       }
77     }
78   }
79   MBB.erase(I);
80 }
81 
82 void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const {
83   MachineBasicBlock &MBB = MF.front();
84   MachineBasicBlock::iterator MBBI = MBB.begin();
85   MachineFrameInfo  *MFI = MF.getFrameInfo();
86   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
87   MachineModuleInfo &MMI = MF.getMMI();
88   const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
89   const Thumb1RegisterInfo *RegInfo =
90     static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo());
91   const Thumb1InstrInfo &TII =
92     *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo());
93 
94   unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
95   unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
96   unsigned NumBytes = MFI->getStackSize();
97   assert(NumBytes >= ArgRegsSaveSize &&
98          "ArgRegsSaveSize is included in NumBytes");
99   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
100   DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
101   unsigned FramePtr = RegInfo->getFrameRegister(MF);
102   unsigned BasePtr = RegInfo->getBaseRegister();
103   int CFAOffset = 0;
104 
105   // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
106   NumBytes = (NumBytes + 3) & ~3;
107   MFI->setStackSize(NumBytes);
108 
109   // Determine the sizes of each callee-save spill areas and record which frame
110   // belongs to which callee-save spill areas.
111   unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
112   int FramePtrSpillFI = 0;
113 
114   if (ArgRegsSaveSize) {
115     emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
116                  MachineInstr::FrameSetup);
117     CFAOffset -= ArgRegsSaveSize;
118     unsigned CFIIndex = MMI.addFrameInst(
119         MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
120     BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
121         .addCFIIndex(CFIIndex);
122   }
123 
124   if (!AFI->hasStackFrame()) {
125     if (NumBytes - ArgRegsSaveSize != 0) {
126       emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
127                    MachineInstr::FrameSetup);
128       CFAOffset -= NumBytes - ArgRegsSaveSize;
129       unsigned CFIIndex = MMI.addFrameInst(
130           MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
131       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
132           .addCFIIndex(CFIIndex);
133     }
134     return;
135   }
136 
137   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
138     unsigned Reg = CSI[i].getReg();
139     int FI = CSI[i].getFrameIdx();
140     switch (Reg) {
141     case ARM::R8:
142     case ARM::R9:
143     case ARM::R10:
144     case ARM::R11:
145       if (STI.isTargetMachO()) {
146         GPRCS2Size += 4;
147         break;
148       }
149       // fallthrough
150     case ARM::R4:
151     case ARM::R5:
152     case ARM::R6:
153     case ARM::R7:
154     case ARM::LR:
155       if (Reg == FramePtr)
156         FramePtrSpillFI = FI;
157       GPRCS1Size += 4;
158       break;
159     default:
160       DPRCSSize += 8;
161     }
162   }
163 
164   if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
165     ++MBBI;
166     if (MBBI != MBB.end())
167       dl = MBBI->getDebugLoc();
168   }
169 
170   // Determine starting offsets of spill areas.
171   unsigned DPRCSOffset  = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);
172   unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
173   unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
174   bool HasFP = hasFP(MF);
175   if (HasFP)
176     AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
177                                 NumBytes);
178   AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
179   AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
180   AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
181   NumBytes = DPRCSOffset;
182 
183   int FramePtrOffsetInBlock = 0;
184   unsigned adjustedGPRCS1Size = GPRCS1Size;
185   if (tryFoldSPUpdateIntoPushPop(STI, MF, std::prev(MBBI), NumBytes)) {
186     FramePtrOffsetInBlock = NumBytes;
187     adjustedGPRCS1Size += NumBytes;
188     NumBytes = 0;
189   }
190 
191   if (adjustedGPRCS1Size) {
192     CFAOffset -= adjustedGPRCS1Size;
193     unsigned CFIIndex = MMI.addFrameInst(
194         MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
195     BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
196         .addCFIIndex(CFIIndex);
197   }
198   for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
199          E = CSI.end(); I != E; ++I) {
200     unsigned Reg = I->getReg();
201     int FI = I->getFrameIdx();
202     switch (Reg) {
203     case ARM::R8:
204     case ARM::R9:
205     case ARM::R10:
206     case ARM::R11:
207     case ARM::R12:
208       if (STI.isTargetMachO())
209         break;
210       // fallthough
211     case ARM::R0:
212     case ARM::R1:
213     case ARM::R2:
214     case ARM::R3:
215     case ARM::R4:
216     case ARM::R5:
217     case ARM::R6:
218     case ARM::R7:
219     case ARM::LR:
220       unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
221           nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI)));
222       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
223           .addCFIIndex(CFIIndex);
224       break;
225     }
226   }
227 
228 
229   // Adjust FP so it point to the stack slot that contains the previous FP.
230   if (HasFP) {
231     FramePtrOffsetInBlock += MFI->getObjectOffset(FramePtrSpillFI)
232 		                     + GPRCS1Size + ArgRegsSaveSize;
233     AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
234       .addReg(ARM::SP).addImm(FramePtrOffsetInBlock / 4)
235       .setMIFlags(MachineInstr::FrameSetup));
236     if(FramePtrOffsetInBlock) {
237       CFAOffset += FramePtrOffsetInBlock;
238       unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa(
239           nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
240       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
241           .addCFIIndex(CFIIndex);
242     } else {
243       unsigned CFIIndex =
244           MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
245               nullptr, MRI->getDwarfRegNum(FramePtr, true)));
246       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
247           .addCFIIndex(CFIIndex);
248     }
249     if (NumBytes > 508)
250       // If offset is > 508 then sp cannot be adjusted in a single instruction,
251       // try restoring from fp instead.
252       AFI->setShouldRestoreSPFromFP(true);
253   }
254 
255   if (NumBytes) {
256     // Insert it after all the callee-save spills.
257     emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
258                  MachineInstr::FrameSetup);
259     if (!HasFP) {
260       CFAOffset -= NumBytes;
261       unsigned CFIIndex = MMI.addFrameInst(
262           MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
263       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
264           .addCFIIndex(CFIIndex);
265     }
266   }
267 
268   if (STI.isTargetELF() && HasFP)
269     MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
270                              AFI->getFramePtrSpillOffset());
271 
272   AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
273   AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
274   AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
275 
276   // Thumb1 does not currently support dynamic stack realignment.  Report a
277   // fatal error rather then silently generate bad code.
278   if (RegInfo->needsStackRealignment(MF))
279       report_fatal_error("Dynamic stack realignment not supported for thumb1.");
280 
281   // If we need a base pointer, set it up here. It's whatever the value
282   // of the stack pointer is at this point. Any variable size objects
283   // will be allocated after this, so we can still use the base pointer
284   // to reference locals.
285   if (RegInfo->hasBasePointer(MF))
286     AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
287                    .addReg(ARM::SP));
288 
289   // If the frame has variable sized objects then the epilogue must restore
290   // the sp from fp. We can assume there's an FP here since hasFP already
291   // checks for hasVarSizedObjects.
292   if (MFI->hasVarSizedObjects())
293     AFI->setShouldRestoreSPFromFP(true);
294 }
295 
296 static bool isCSRestore(MachineInstr *MI, const MCPhysReg *CSRegs) {
297   if (MI->getOpcode() == ARM::tLDRspi &&
298       MI->getOperand(1).isFI() &&
299       isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
300     return true;
301   else if (MI->getOpcode() == ARM::tPOP) {
302     // The first two operands are predicates. The last two are
303     // imp-def and imp-use of SP. Check everything in between.
304     for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
305       if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
306         return false;
307     return true;
308   }
309   return false;
310 }
311 
312 void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
313                                    MachineBasicBlock &MBB) const {
314   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
315   assert((MBBI->getOpcode() == ARM::tBX_RET ||
316           MBBI->getOpcode() == ARM::tPOP_RET) &&
317          "Can only insert epilog into returning blocks");
318   DebugLoc dl = MBBI->getDebugLoc();
319   MachineFrameInfo *MFI = MF.getFrameInfo();
320   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
321   const Thumb1RegisterInfo *RegInfo =
322     static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo());
323   const Thumb1InstrInfo &TII =
324     *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo());
325 
326   unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
327   unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
328   int NumBytes = (int)MFI->getStackSize();
329   assert((unsigned)NumBytes >= ArgRegsSaveSize &&
330          "ArgRegsSaveSize is included in NumBytes");
331   const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs();
332   unsigned FramePtr = RegInfo->getFrameRegister(MF);
333 
334   if (!AFI->hasStackFrame()) {
335     if (NumBytes - ArgRegsSaveSize != 0)
336       emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize);
337   } else {
338     // Unwind MBBI to point to first LDR / VLDRD.
339     if (MBBI != MBB.begin()) {
340       do
341         --MBBI;
342       while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
343       if (!isCSRestore(MBBI, CSRegs))
344         ++MBBI;
345     }
346 
347     // Move SP to start of FP callee save spill area.
348     NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
349                  AFI->getGPRCalleeSavedArea2Size() +
350                  AFI->getDPRCalleeSavedAreaSize() +
351                  ArgRegsSaveSize);
352 
353     if (AFI->shouldRestoreSPFromFP()) {
354       NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
355       // Reset SP based on frame pointer only if the stack frame extends beyond
356       // frame pointer stack slot, the target is ELF and the function has FP, or
357       // the target uses var sized objects.
358       if (NumBytes) {
359         assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
360                "No scratch register to restore SP from FP!");
361         emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
362                                   TII, *RegInfo);
363         AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
364                                ARM::SP)
365           .addReg(ARM::R4));
366       } else
367         AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
368                                ARM::SP)
369           .addReg(FramePtr));
370     } else {
371       if (MBBI->getOpcode() == ARM::tBX_RET &&
372           &MBB.front() != MBBI &&
373           std::prev(MBBI)->getOpcode() == ARM::tPOP) {
374         MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
375         if (!tryFoldSPUpdateIntoPushPop(STI, MF, PMBBI, NumBytes))
376           emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
377       } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes))
378         emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
379     }
380   }
381 
382   if (ArgRegsSaveSize) {
383     // Unlike T2 and ARM mode, the T1 pop instruction cannot restore
384     // to LR, and we can't pop the value directly to the PC since
385     // we need to update the SP after popping the value. Therefore, we
386     // pop the old LR into R3 as a temporary.
387 
388     // Get the last instruction, tBX_RET
389     MBBI = MBB.getLastNonDebugInstr();
390     assert (MBBI->getOpcode() == ARM::tBX_RET);
391     // Epilogue for vararg functions: pop LR to R3 and branch off it.
392     AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
393       .addReg(ARM::R3, RegState::Define);
394 
395     emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
396 
397     MachineInstrBuilder MIB =
398       BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
399       .addReg(ARM::R3, RegState::Kill);
400     AddDefaultPred(MIB);
401     MIB.copyImplicitOps(&*MBBI);
402     // erase the old tBX_RET instruction
403     MBB.erase(MBBI);
404   }
405 }
406 
407 bool Thumb1FrameLowering::
408 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
409                           MachineBasicBlock::iterator MI,
410                           const std::vector<CalleeSavedInfo> &CSI,
411                           const TargetRegisterInfo *TRI) const {
412   if (CSI.empty())
413     return false;
414 
415   DebugLoc DL;
416   MachineFunction &MF = *MBB.getParent();
417   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
418 
419   if (MI != MBB.end()) DL = MI->getDebugLoc();
420 
421   MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
422   AddDefaultPred(MIB);
423   for (unsigned i = CSI.size(); i != 0; --i) {
424     unsigned Reg = CSI[i-1].getReg();
425     bool isKill = true;
426 
427     // Add the callee-saved register as live-in unless it's LR and
428     // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
429     // then it's already added to the function and entry block live-in sets.
430     if (Reg == ARM::LR) {
431       MachineFunction &MF = *MBB.getParent();
432       if (MF.getFrameInfo()->isReturnAddressTaken() &&
433           MF.getRegInfo().isLiveIn(Reg))
434         isKill = false;
435     }
436 
437     if (isKill)
438       MBB.addLiveIn(Reg);
439 
440     MIB.addReg(Reg, getKillRegState(isKill));
441   }
442   MIB.setMIFlags(MachineInstr::FrameSetup);
443   return true;
444 }
445 
446 bool Thumb1FrameLowering::
447 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
448                             MachineBasicBlock::iterator MI,
449                             const std::vector<CalleeSavedInfo> &CSI,
450                             const TargetRegisterInfo *TRI) const {
451   if (CSI.empty())
452     return false;
453 
454   MachineFunction &MF = *MBB.getParent();
455   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
456   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
457 
458   bool isVarArg = AFI->getArgRegsSaveSize() > 0;
459   DebugLoc DL = MI->getDebugLoc();
460   MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
461   AddDefaultPred(MIB);
462 
463   bool NumRegs = false;
464   for (unsigned i = CSI.size(); i != 0; --i) {
465     unsigned Reg = CSI[i-1].getReg();
466     if (Reg == ARM::LR) {
467       // Special epilogue for vararg functions. See emitEpilogue
468       if (isVarArg)
469         continue;
470       Reg = ARM::PC;
471       (*MIB).setDesc(TII.get(ARM::tPOP_RET));
472       MIB.copyImplicitOps(&*MI);
473       MI = MBB.erase(MI);
474     }
475     MIB.addReg(Reg, getDefRegState(true));
476     NumRegs = true;
477   }
478 
479   // It's illegal to emit pop instruction without operands.
480   if (NumRegs)
481     MBB.insert(MI, &*MIB);
482   else
483     MF.DeleteMachineInstr(MIB);
484 
485   return true;
486 }
487