1 //===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Thumb1 implementation of TargetFrameLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Thumb1FrameLowering.h"
15 #include "ARMMachineFunctionInfo.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 
21 using namespace llvm;
22 
23 bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{
24   const MachineFrameInfo *FFI = MF.getFrameInfo();
25   unsigned CFSize = FFI->getMaxCallFrameSize();
26   // It's not always a good idea to include the call frame as part of the
27   // stack frame. ARM (especially Thumb) has small immediate offset to
28   // address the stack frame. So a large call frame can cause poor codegen
29   // and may even makes it impossible to scavenge a register.
30   if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
31     return false;
32 
33   return !MF.getFrameInfo()->hasVarSizedObjects();
34 }
35 
36 static void
37 emitSPUpdate(MachineBasicBlock &MBB,
38              MachineBasicBlock::iterator &MBBI,
39              const TargetInstrInfo &TII, DebugLoc dl,
40              const Thumb1RegisterInfo &MRI,
41              int NumBytes, unsigned MIFlags = MachineInstr::NoFlags)  {
42   emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
43                             MRI, MIFlags);
44 }
45 
46 
47 void Thumb1FrameLowering::
48 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
49                               MachineBasicBlock::iterator I) const {
50   const Thumb1InstrInfo &TII =
51     *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo());
52   const Thumb1RegisterInfo *RegInfo =
53     static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo());
54   if (!hasReservedCallFrame(MF)) {
55     // If we have alloca, convert as follows:
56     // ADJCALLSTACKDOWN -> sub, sp, sp, amount
57     // ADJCALLSTACKUP   -> add, sp, sp, amount
58     MachineInstr *Old = I;
59     DebugLoc dl = Old->getDebugLoc();
60     unsigned Amount = Old->getOperand(0).getImm();
61     if (Amount != 0) {
62       // We need to keep the stack aligned properly.  To do this, we round the
63       // amount of space needed for the outgoing arguments up to the next
64       // alignment boundary.
65       unsigned Align = getStackAlignment();
66       Amount = (Amount+Align-1)/Align*Align;
67 
68       // Replace the pseudo instruction with a new instruction...
69       unsigned Opc = Old->getOpcode();
70       if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
71         emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
72       } else {
73         assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
74         emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
75       }
76     }
77   }
78   MBB.erase(I);
79 }
80 
81 void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const {
82   MachineBasicBlock &MBB = MF.front();
83   MachineBasicBlock::iterator MBBI = MBB.begin();
84   MachineFrameInfo  *MFI = MF.getFrameInfo();
85   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
86   const Thumb1RegisterInfo *RegInfo =
87     static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo());
88   const Thumb1InstrInfo &TII =
89     *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo());
90 
91   unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
92   unsigned NumBytes = MFI->getStackSize();
93   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
94   DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
95   unsigned FramePtr = RegInfo->getFrameRegister(MF);
96   unsigned BasePtr = RegInfo->getBaseRegister();
97 
98   // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
99   NumBytes = (NumBytes + 3) & ~3;
100   MFI->setStackSize(NumBytes);
101 
102   // Determine the sizes of each callee-save spill areas and record which frame
103   // belongs to which callee-save spill areas.
104   unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
105   int FramePtrSpillFI = 0;
106 
107   if (VARegSaveSize)
108     emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -VARegSaveSize,
109                  MachineInstr::FrameSetup);
110 
111   if (!AFI->hasStackFrame()) {
112     if (NumBytes != 0)
113       emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
114                    MachineInstr::FrameSetup);
115     return;
116   }
117 
118   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
119     unsigned Reg = CSI[i].getReg();
120     int FI = CSI[i].getFrameIdx();
121     switch (Reg) {
122     case ARM::R4:
123     case ARM::R5:
124     case ARM::R6:
125     case ARM::R7:
126     case ARM::LR:
127       if (Reg == FramePtr)
128         FramePtrSpillFI = FI;
129       AFI->addGPRCalleeSavedArea1Frame(FI);
130       GPRCS1Size += 4;
131       break;
132     case ARM::R8:
133     case ARM::R9:
134     case ARM::R10:
135     case ARM::R11:
136       if (Reg == FramePtr)
137         FramePtrSpillFI = FI;
138       if (STI.isTargetIOS()) {
139         AFI->addGPRCalleeSavedArea2Frame(FI);
140         GPRCS2Size += 4;
141       } else {
142         AFI->addGPRCalleeSavedArea1Frame(FI);
143         GPRCS1Size += 4;
144       }
145       break;
146     default:
147       AFI->addDPRCalleeSavedAreaFrame(FI);
148       DPRCSSize += 8;
149     }
150   }
151 
152   if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
153     ++MBBI;
154     if (MBBI != MBB.end())
155       dl = MBBI->getDebugLoc();
156   }
157 
158   // Determine starting offsets of spill areas.
159   unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
160   unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
161   unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
162   bool HasFP = hasFP(MF);
163   if (HasFP)
164     AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
165                                 NumBytes);
166   AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
167   AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
168   AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
169   NumBytes = DPRCSOffset;
170 
171   // Adjust FP so it point to the stack slot that contains the previous FP.
172   if (HasFP) {
173     AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
174       .addFrameIndex(FramePtrSpillFI).addImm(0)
175       .setMIFlags(MachineInstr::FrameSetup));
176     if (NumBytes > 508)
177       // If offset is > 508 then sp cannot be adjusted in a single instruction,
178       // try restoring from fp instead.
179       AFI->setShouldRestoreSPFromFP(true);
180   }
181 
182   if (NumBytes)
183     // Insert it after all the callee-save spills.
184     emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
185                  MachineInstr::FrameSetup);
186 
187   if (STI.isTargetELF() && HasFP)
188     MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
189                              AFI->getFramePtrSpillOffset());
190 
191   AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
192   AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
193   AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
194 
195   // Thumb1 does not currently support dynamic stack realignment.  Report a
196   // fatal error rather then silently generate bad code.
197   if (RegInfo->needsStackRealignment(MF))
198       report_fatal_error("Dynamic stack realignment not supported for thumb1.");
199 
200   // If we need a base pointer, set it up here. It's whatever the value
201   // of the stack pointer is at this point. Any variable size objects
202   // will be allocated after this, so we can still use the base pointer
203   // to reference locals.
204   if (RegInfo->hasBasePointer(MF))
205     AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
206                    .addReg(ARM::SP));
207 
208   // If the frame has variable sized objects then the epilogue must restore
209   // the sp from fp. We can assume there's an FP here since hasFP already
210   // checks for hasVarSizedObjects.
211   if (MFI->hasVarSizedObjects())
212     AFI->setShouldRestoreSPFromFP(true);
213 }
214 
215 static bool isCalleeSavedRegister(unsigned Reg, const uint16_t *CSRegs) {
216   for (unsigned i = 0; CSRegs[i]; ++i)
217     if (Reg == CSRegs[i])
218       return true;
219   return false;
220 }
221 
222 static bool isCSRestore(MachineInstr *MI, const uint16_t *CSRegs) {
223   if (MI->getOpcode() == ARM::tLDRspi &&
224       MI->getOperand(1).isFI() &&
225       isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
226     return true;
227   else if (MI->getOpcode() == ARM::tPOP) {
228     // The first two operands are predicates. The last two are
229     // imp-def and imp-use of SP. Check everything in between.
230     for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
231       if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
232         return false;
233     return true;
234   }
235   return false;
236 }
237 
238 void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
239                                    MachineBasicBlock &MBB) const {
240   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
241   assert((MBBI->getOpcode() == ARM::tBX_RET ||
242           MBBI->getOpcode() == ARM::tPOP_RET) &&
243          "Can only insert epilog into returning blocks");
244   DebugLoc dl = MBBI->getDebugLoc();
245   MachineFrameInfo *MFI = MF.getFrameInfo();
246   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
247   const Thumb1RegisterInfo *RegInfo =
248     static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo());
249   const Thumb1InstrInfo &TII =
250     *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo());
251 
252   unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
253   int NumBytes = (int)MFI->getStackSize();
254   const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs();
255   unsigned FramePtr = RegInfo->getFrameRegister(MF);
256 
257   if (!AFI->hasStackFrame()) {
258     if (NumBytes != 0)
259       emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
260   } else {
261     // Unwind MBBI to point to first LDR / VLDRD.
262     if (MBBI != MBB.begin()) {
263       do
264         --MBBI;
265       while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
266       if (!isCSRestore(MBBI, CSRegs))
267         ++MBBI;
268     }
269 
270     // Move SP to start of FP callee save spill area.
271     NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
272                  AFI->getGPRCalleeSavedArea2Size() +
273                  AFI->getDPRCalleeSavedAreaSize());
274 
275     if (AFI->shouldRestoreSPFromFP()) {
276       NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
277       // Reset SP based on frame pointer only if the stack frame extends beyond
278       // frame pointer stack slot, the target is ELF and the function has FP, or
279       // the target uses var sized objects.
280       if (NumBytes) {
281         assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
282                "No scratch register to restore SP from FP!");
283         emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
284                                   TII, *RegInfo);
285         AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
286                                ARM::SP)
287           .addReg(ARM::R4));
288       } else
289         AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
290                                ARM::SP)
291           .addReg(FramePtr));
292     } else {
293       if (MBBI->getOpcode() == ARM::tBX_RET &&
294           &MBB.front() != MBBI &&
295           prior(MBBI)->getOpcode() == ARM::tPOP) {
296         MachineBasicBlock::iterator PMBBI = prior(MBBI);
297         emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
298       } else
299         emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
300     }
301   }
302 
303   if (VARegSaveSize) {
304     // Unlike T2 and ARM mode, the T1 pop instruction cannot restore
305     // to LR, and we can't pop the value directly to the PC since
306     // we need to update the SP after popping the value. Therefore, we
307     // pop the old LR into R3 as a temporary.
308 
309     // Move back past the callee-saved register restoration
310     while (MBBI != MBB.end() && isCSRestore(MBBI, CSRegs))
311       ++MBBI;
312     // Epilogue for vararg functions: pop LR to R3 and branch off it.
313     AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
314       .addReg(ARM::R3, RegState::Define);
315 
316     emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, VARegSaveSize);
317 
318     MachineInstrBuilder MIB =
319       BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
320       .addReg(ARM::R3, RegState::Kill);
321     AddDefaultPred(MIB);
322     MIB.copyImplicitOps(&*MBBI);
323     // erase the old tBX_RET instruction
324     MBB.erase(MBBI);
325   }
326 }
327 
328 bool Thumb1FrameLowering::
329 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
330                           MachineBasicBlock::iterator MI,
331                           const std::vector<CalleeSavedInfo> &CSI,
332                           const TargetRegisterInfo *TRI) const {
333   if (CSI.empty())
334     return false;
335 
336   DebugLoc DL;
337   MachineFunction &MF = *MBB.getParent();
338   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
339 
340   if (MI != MBB.end()) DL = MI->getDebugLoc();
341 
342   MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
343   AddDefaultPred(MIB);
344   for (unsigned i = CSI.size(); i != 0; --i) {
345     unsigned Reg = CSI[i-1].getReg();
346     bool isKill = true;
347 
348     // Add the callee-saved register as live-in unless it's LR and
349     // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
350     // then it's already added to the function and entry block live-in sets.
351     if (Reg == ARM::LR) {
352       MachineFunction &MF = *MBB.getParent();
353       if (MF.getFrameInfo()->isReturnAddressTaken() &&
354           MF.getRegInfo().isLiveIn(Reg))
355         isKill = false;
356     }
357 
358     if (isKill)
359       MBB.addLiveIn(Reg);
360 
361     MIB.addReg(Reg, getKillRegState(isKill));
362   }
363   MIB.setMIFlags(MachineInstr::FrameSetup);
364   return true;
365 }
366 
367 bool Thumb1FrameLowering::
368 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
369                             MachineBasicBlock::iterator MI,
370                             const std::vector<CalleeSavedInfo> &CSI,
371                             const TargetRegisterInfo *TRI) const {
372   if (CSI.empty())
373     return false;
374 
375   MachineFunction &MF = *MBB.getParent();
376   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
377   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
378 
379   bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
380   DebugLoc DL = MI->getDebugLoc();
381   MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
382   AddDefaultPred(MIB);
383 
384   bool NumRegs = false;
385   for (unsigned i = CSI.size(); i != 0; --i) {
386     unsigned Reg = CSI[i-1].getReg();
387     if (Reg == ARM::LR) {
388       // Special epilogue for vararg functions. See emitEpilogue
389       if (isVarArg)
390         continue;
391       Reg = ARM::PC;
392       (*MIB).setDesc(TII.get(ARM::tPOP_RET));
393       MIB.copyImplicitOps(&*MI);
394       MI = MBB.erase(MI);
395     }
396     MIB.addReg(Reg, getDefRegState(true));
397     NumRegs = true;
398   }
399 
400   // It's illegal to emit pop instruction without operands.
401   if (NumRegs)
402     MBB.insert(MI, &*MIB);
403   else
404     MF.DeleteMachineInstr(MIB);
405 
406   return true;
407 }
408