1 //===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Thumb1 implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Thumb1FrameLowering.h" 15 #include "ARMMachineFunctionInfo.h" 16 #include "llvm/CodeGen/MachineFrameInfo.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/MachineInstrBuilder.h" 19 #include "llvm/CodeGen/MachineModuleInfo.h" 20 #include "llvm/CodeGen/MachineRegisterInfo.h" 21 22 using namespace llvm; 23 24 Thumb1FrameLowering::Thumb1FrameLowering(const ARMSubtarget &sti) 25 : ARMFrameLowering(sti) {} 26 27 bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{ 28 const MachineFrameInfo *FFI = MF.getFrameInfo(); 29 unsigned CFSize = FFI->getMaxCallFrameSize(); 30 // It's not always a good idea to include the call frame as part of the 31 // stack frame. ARM (especially Thumb) has small immediate offset to 32 // address the stack frame. So a large call frame can cause poor codegen 33 // and may even makes it impossible to scavenge a register. 34 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4 35 return false; 36 37 return !MF.getFrameInfo()->hasVarSizedObjects(); 38 } 39 40 static void 41 emitSPUpdate(MachineBasicBlock &MBB, 42 MachineBasicBlock::iterator &MBBI, 43 const TargetInstrInfo &TII, DebugLoc dl, 44 const Thumb1RegisterInfo &MRI, 45 int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) { 46 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, 47 MRI, MIFlags); 48 } 49 50 51 void Thumb1FrameLowering:: 52 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 53 MachineBasicBlock::iterator I) const { 54 const Thumb1InstrInfo &TII = 55 *static_cast<const Thumb1InstrInfo *>(MF.getSubtarget().getInstrInfo()); 56 const Thumb1RegisterInfo *RegInfo = static_cast<const Thumb1RegisterInfo *>( 57 MF.getSubtarget().getRegisterInfo()); 58 if (!hasReservedCallFrame(MF)) { 59 // If we have alloca, convert as follows: 60 // ADJCALLSTACKDOWN -> sub, sp, sp, amount 61 // ADJCALLSTACKUP -> add, sp, sp, amount 62 MachineInstr *Old = I; 63 DebugLoc dl = Old->getDebugLoc(); 64 unsigned Amount = Old->getOperand(0).getImm(); 65 if (Amount != 0) { 66 // We need to keep the stack aligned properly. To do this, we round the 67 // amount of space needed for the outgoing arguments up to the next 68 // alignment boundary. 69 unsigned Align = getStackAlignment(); 70 Amount = (Amount+Align-1)/Align*Align; 71 72 // Replace the pseudo instruction with a new instruction... 73 unsigned Opc = Old->getOpcode(); 74 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 75 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); 76 } else { 77 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 78 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); 79 } 80 } 81 } 82 MBB.erase(I); 83 } 84 85 void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const { 86 MachineBasicBlock &MBB = MF.front(); 87 MachineBasicBlock::iterator MBBI = MBB.begin(); 88 MachineFrameInfo *MFI = MF.getFrameInfo(); 89 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 90 MachineModuleInfo &MMI = MF.getMMI(); 91 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); 92 const Thumb1RegisterInfo *RegInfo = static_cast<const Thumb1RegisterInfo *>( 93 MF.getSubtarget().getRegisterInfo()); 94 const Thumb1InstrInfo &TII = 95 *static_cast<const Thumb1InstrInfo *>(MF.getSubtarget().getInstrInfo()); 96 97 unsigned Align = MF.getTarget() 98 .getSubtargetImpl() 99 ->getFrameLowering() 100 ->getStackAlignment(); 101 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align); 102 unsigned NumBytes = MFI->getStackSize(); 103 assert(NumBytes >= ArgRegsSaveSize && 104 "ArgRegsSaveSize is included in NumBytes"); 105 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 106 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 107 unsigned FramePtr = RegInfo->getFrameRegister(MF); 108 unsigned BasePtr = RegInfo->getBaseRegister(); 109 int CFAOffset = 0; 110 111 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 112 NumBytes = (NumBytes + 3) & ~3; 113 MFI->setStackSize(NumBytes); 114 115 // Determine the sizes of each callee-save spill areas and record which frame 116 // belongs to which callee-save spill areas. 117 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 118 int FramePtrSpillFI = 0; 119 120 if (ArgRegsSaveSize) { 121 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, 122 MachineInstr::FrameSetup); 123 CFAOffset -= ArgRegsSaveSize; 124 unsigned CFIIndex = MMI.addFrameInst( 125 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset)); 126 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 127 .addCFIIndex(CFIIndex); 128 } 129 130 if (!AFI->hasStackFrame()) { 131 if (NumBytes - ArgRegsSaveSize != 0) { 132 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize), 133 MachineInstr::FrameSetup); 134 CFAOffset -= NumBytes - ArgRegsSaveSize; 135 unsigned CFIIndex = MMI.addFrameInst( 136 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset)); 137 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 138 .addCFIIndex(CFIIndex); 139 } 140 return; 141 } 142 143 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 144 unsigned Reg = CSI[i].getReg(); 145 int FI = CSI[i].getFrameIdx(); 146 switch (Reg) { 147 case ARM::R8: 148 case ARM::R9: 149 case ARM::R10: 150 case ARM::R11: 151 if (STI.isTargetMachO()) { 152 GPRCS2Size += 4; 153 break; 154 } 155 // fallthrough 156 case ARM::R4: 157 case ARM::R5: 158 case ARM::R6: 159 case ARM::R7: 160 case ARM::LR: 161 if (Reg == FramePtr) 162 FramePtrSpillFI = FI; 163 GPRCS1Size += 4; 164 break; 165 default: 166 DPRCSSize += 8; 167 } 168 } 169 170 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) { 171 ++MBBI; 172 if (MBBI != MBB.end()) 173 dl = MBBI->getDebugLoc(); 174 } 175 176 // Determine starting offsets of spill areas. 177 unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize); 178 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 179 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 180 bool HasFP = hasFP(MF); 181 if (HasFP) 182 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + 183 NumBytes); 184 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 185 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 186 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 187 NumBytes = DPRCSOffset; 188 189 int FramePtrOffsetInBlock = 0; 190 unsigned adjustedGPRCS1Size = GPRCS1Size; 191 if (tryFoldSPUpdateIntoPushPop(STI, MF, std::prev(MBBI), NumBytes)) { 192 FramePtrOffsetInBlock = NumBytes; 193 adjustedGPRCS1Size += NumBytes; 194 NumBytes = 0; 195 } 196 197 if (adjustedGPRCS1Size) { 198 CFAOffset -= adjustedGPRCS1Size; 199 unsigned CFIIndex = MMI.addFrameInst( 200 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset)); 201 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 202 .addCFIIndex(CFIIndex); 203 } 204 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(), 205 E = CSI.end(); I != E; ++I) { 206 unsigned Reg = I->getReg(); 207 int FI = I->getFrameIdx(); 208 switch (Reg) { 209 case ARM::R8: 210 case ARM::R9: 211 case ARM::R10: 212 case ARM::R11: 213 case ARM::R12: 214 if (STI.isTargetMachO()) 215 break; 216 // fallthough 217 case ARM::R0: 218 case ARM::R1: 219 case ARM::R2: 220 case ARM::R3: 221 case ARM::R4: 222 case ARM::R5: 223 case ARM::R6: 224 case ARM::R7: 225 case ARM::LR: 226 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 227 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI))); 228 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 229 .addCFIIndex(CFIIndex); 230 break; 231 } 232 } 233 234 235 // Adjust FP so it point to the stack slot that contains the previous FP. 236 if (HasFP) { 237 FramePtrOffsetInBlock += MFI->getObjectOffset(FramePtrSpillFI) 238 + GPRCS1Size + ArgRegsSaveSize; 239 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr) 240 .addReg(ARM::SP).addImm(FramePtrOffsetInBlock / 4) 241 .setMIFlags(MachineInstr::FrameSetup)); 242 if(FramePtrOffsetInBlock) { 243 CFAOffset += FramePtrOffsetInBlock; 244 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa( 245 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset)); 246 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 247 .addCFIIndex(CFIIndex); 248 } else { 249 unsigned CFIIndex = 250 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister( 251 nullptr, MRI->getDwarfRegNum(FramePtr, true))); 252 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 253 .addCFIIndex(CFIIndex); 254 } 255 if (NumBytes > 508) 256 // If offset is > 508 then sp cannot be adjusted in a single instruction, 257 // try restoring from fp instead. 258 AFI->setShouldRestoreSPFromFP(true); 259 } 260 261 if (NumBytes) { 262 // Insert it after all the callee-save spills. 263 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, 264 MachineInstr::FrameSetup); 265 if (!HasFP) { 266 CFAOffset -= NumBytes; 267 unsigned CFIIndex = MMI.addFrameInst( 268 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset)); 269 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 270 .addCFIIndex(CFIIndex); 271 } 272 } 273 274 if (STI.isTargetELF() && HasFP) 275 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 276 AFI->getFramePtrSpillOffset()); 277 278 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 279 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 280 AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 281 282 // Thumb1 does not currently support dynamic stack realignment. Report a 283 // fatal error rather then silently generate bad code. 284 if (RegInfo->needsStackRealignment(MF)) 285 report_fatal_error("Dynamic stack realignment not supported for thumb1."); 286 287 // If we need a base pointer, set it up here. It's whatever the value 288 // of the stack pointer is at this point. Any variable size objects 289 // will be allocated after this, so we can still use the base pointer 290 // to reference locals. 291 if (RegInfo->hasBasePointer(MF)) 292 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr) 293 .addReg(ARM::SP)); 294 295 // If the frame has variable sized objects then the epilogue must restore 296 // the sp from fp. We can assume there's an FP here since hasFP already 297 // checks for hasVarSizedObjects. 298 if (MFI->hasVarSizedObjects()) 299 AFI->setShouldRestoreSPFromFP(true); 300 } 301 302 static bool isCSRestore(MachineInstr *MI, const MCPhysReg *CSRegs) { 303 if (MI->getOpcode() == ARM::tLDRspi && 304 MI->getOperand(1).isFI() && 305 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)) 306 return true; 307 else if (MI->getOpcode() == ARM::tPOP) { 308 // The first two operands are predicates. The last two are 309 // imp-def and imp-use of SP. Check everything in between. 310 for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i) 311 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs)) 312 return false; 313 return true; 314 } 315 return false; 316 } 317 318 void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF, 319 MachineBasicBlock &MBB) const { 320 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 321 assert((MBBI->getOpcode() == ARM::tBX_RET || 322 MBBI->getOpcode() == ARM::tPOP_RET) && 323 "Can only insert epilog into returning blocks"); 324 DebugLoc dl = MBBI->getDebugLoc(); 325 MachineFrameInfo *MFI = MF.getFrameInfo(); 326 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 327 const Thumb1RegisterInfo *RegInfo = static_cast<const Thumb1RegisterInfo *>( 328 MF.getSubtarget().getRegisterInfo()); 329 const Thumb1InstrInfo &TII = 330 *static_cast<const Thumb1InstrInfo *>(MF.getSubtarget().getInstrInfo()); 331 332 unsigned Align = MF.getTarget() 333 .getSubtargetImpl() 334 ->getFrameLowering() 335 ->getStackAlignment(); 336 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align); 337 int NumBytes = (int)MFI->getStackSize(); 338 assert((unsigned)NumBytes >= ArgRegsSaveSize && 339 "ArgRegsSaveSize is included in NumBytes"); 340 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(); 341 unsigned FramePtr = RegInfo->getFrameRegister(MF); 342 343 if (!AFI->hasStackFrame()) { 344 if (NumBytes - ArgRegsSaveSize != 0) 345 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize); 346 } else { 347 // Unwind MBBI to point to first LDR / VLDRD. 348 if (MBBI != MBB.begin()) { 349 do 350 --MBBI; 351 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); 352 if (!isCSRestore(MBBI, CSRegs)) 353 ++MBBI; 354 } 355 356 // Move SP to start of FP callee save spill area. 357 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 358 AFI->getGPRCalleeSavedArea2Size() + 359 AFI->getDPRCalleeSavedAreaSize() + 360 ArgRegsSaveSize); 361 362 if (AFI->shouldRestoreSPFromFP()) { 363 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 364 // Reset SP based on frame pointer only if the stack frame extends beyond 365 // frame pointer stack slot, the target is ELF and the function has FP, or 366 // the target uses var sized objects. 367 if (NumBytes) { 368 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) && 369 "No scratch register to restore SP from FP!"); 370 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, 371 TII, *RegInfo); 372 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 373 ARM::SP) 374 .addReg(ARM::R4)); 375 } else 376 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 377 ARM::SP) 378 .addReg(FramePtr)); 379 } else { 380 if (MBBI->getOpcode() == ARM::tBX_RET && 381 &MBB.front() != MBBI && 382 std::prev(MBBI)->getOpcode() == ARM::tPOP) { 383 MachineBasicBlock::iterator PMBBI = std::prev(MBBI); 384 if (!tryFoldSPUpdateIntoPushPop(STI, MF, PMBBI, NumBytes)) 385 emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes); 386 } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes)) 387 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes); 388 } 389 } 390 391 bool IsV4PopReturn = false; 392 for (const CalleeSavedInfo &CSI : MFI->getCalleeSavedInfo()) 393 if (CSI.getReg() == ARM::LR) 394 IsV4PopReturn = true; 395 IsV4PopReturn &= STI.hasV4TOps() && !STI.hasV5TOps(); 396 397 // Unlike T2 and ARM mode, the T1 pop instruction cannot restore 398 // to LR, and we can't pop the value directly to the PC since 399 // we need to update the SP after popping the value. So instead 400 // we have to emit: 401 // POP {r3} 402 // ADD sp, #offset 403 // BX r3 404 // If this would clobber a return value, then generate this sequence instead: 405 // MOV ip, r3 406 // POP {r3} 407 // ADD sp, #offset 408 // MOV lr, r3 409 // MOV r3, ip 410 // BX lr 411 if (ArgRegsSaveSize || IsV4PopReturn) { 412 // Get the last instruction, tBX_RET 413 MBBI = MBB.getLastNonDebugInstr(); 414 assert (MBBI->getOpcode() == ARM::tBX_RET); 415 DebugLoc dl = MBBI->getDebugLoc(); 416 417 if (AFI->getReturnRegsCount() <= 3) { 418 // Epilogue: pop saved LR to R3 and branch off it. 419 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))) 420 .addReg(ARM::R3, RegState::Define); 421 422 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize); 423 424 MachineInstrBuilder MIB = 425 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX)) 426 .addReg(ARM::R3, RegState::Kill); 427 AddDefaultPred(MIB); 428 MIB.copyImplicitOps(&*MBBI); 429 // erase the old tBX_RET instruction 430 MBB.erase(MBBI); 431 } else { 432 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) 433 .addReg(ARM::R12, RegState::Define) 434 .addReg(ARM::R3, RegState::Kill)); 435 436 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))) 437 .addReg(ARM::R3, RegState::Define); 438 439 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize); 440 441 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) 442 .addReg(ARM::LR, RegState::Define) 443 .addReg(ARM::R3, RegState::Kill)); 444 445 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) 446 .addReg(ARM::R3, RegState::Define) 447 .addReg(ARM::R12, RegState::Kill)); 448 // Keep the tBX_RET instruction 449 } 450 } 451 } 452 453 bool Thumb1FrameLowering:: 454 spillCalleeSavedRegisters(MachineBasicBlock &MBB, 455 MachineBasicBlock::iterator MI, 456 const std::vector<CalleeSavedInfo> &CSI, 457 const TargetRegisterInfo *TRI) const { 458 if (CSI.empty()) 459 return false; 460 461 DebugLoc DL; 462 MachineFunction &MF = *MBB.getParent(); 463 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 464 465 if (MI != MBB.end()) DL = MI->getDebugLoc(); 466 467 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)); 468 AddDefaultPred(MIB); 469 for (unsigned i = CSI.size(); i != 0; --i) { 470 unsigned Reg = CSI[i-1].getReg(); 471 bool isKill = true; 472 473 // Add the callee-saved register as live-in unless it's LR and 474 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress 475 // then it's already added to the function and entry block live-in sets. 476 if (Reg == ARM::LR) { 477 MachineFunction &MF = *MBB.getParent(); 478 if (MF.getFrameInfo()->isReturnAddressTaken() && 479 MF.getRegInfo().isLiveIn(Reg)) 480 isKill = false; 481 } 482 483 if (isKill) 484 MBB.addLiveIn(Reg); 485 486 MIB.addReg(Reg, getKillRegState(isKill)); 487 } 488 MIB.setMIFlags(MachineInstr::FrameSetup); 489 return true; 490 } 491 492 bool Thumb1FrameLowering:: 493 restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 494 MachineBasicBlock::iterator MI, 495 const std::vector<CalleeSavedInfo> &CSI, 496 const TargetRegisterInfo *TRI) const { 497 if (CSI.empty()) 498 return false; 499 500 MachineFunction &MF = *MBB.getParent(); 501 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 502 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 503 504 bool isVarArg = AFI->getArgRegsSaveSize() > 0; 505 DebugLoc DL = MI->getDebugLoc(); 506 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP)); 507 AddDefaultPred(MIB); 508 509 bool NumRegs = false; 510 for (unsigned i = CSI.size(); i != 0; --i) { 511 unsigned Reg = CSI[i-1].getReg(); 512 if (Reg == ARM::LR) { 513 // Special epilogue for vararg functions. See emitEpilogue 514 if (isVarArg) 515 continue; 516 // ARMv4T requires BX, see emitEpilogue 517 if (STI.hasV4TOps() && !STI.hasV5TOps()) 518 continue; 519 Reg = ARM::PC; 520 (*MIB).setDesc(TII.get(ARM::tPOP_RET)); 521 MIB.copyImplicitOps(&*MI); 522 MI = MBB.erase(MI); 523 } 524 MIB.addReg(Reg, getDefRegState(true)); 525 NumRegs = true; 526 } 527 528 // It's illegal to emit pop instruction without operands. 529 if (NumRegs) 530 MBB.insert(MI, &*MIB); 531 else 532 MF.DeleteMachineInstr(MIB); 533 534 return true; 535 } 536