1 //===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Thumb1 implementation of TargetFrameLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Thumb1FrameLowering.h"
15 #include "ARMMachineFunctionInfo.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineModuleInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 
22 using namespace llvm;
23 
24 Thumb1FrameLowering::Thumb1FrameLowering(const ARMSubtarget &sti)
25     : ARMFrameLowering(sti) {}
26 
27 bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{
28   const MachineFrameInfo *FFI = MF.getFrameInfo();
29   unsigned CFSize = FFI->getMaxCallFrameSize();
30   // It's not always a good idea to include the call frame as part of the
31   // stack frame. ARM (especially Thumb) has small immediate offset to
32   // address the stack frame. So a large call frame can cause poor codegen
33   // and may even makes it impossible to scavenge a register.
34   if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
35     return false;
36 
37   return !MF.getFrameInfo()->hasVarSizedObjects();
38 }
39 
40 static void
41 emitSPUpdate(MachineBasicBlock &MBB,
42              MachineBasicBlock::iterator &MBBI,
43              const TargetInstrInfo &TII, DebugLoc dl,
44              const Thumb1RegisterInfo &MRI,
45              int NumBytes, unsigned MIFlags = MachineInstr::NoFlags)  {
46   emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
47                             MRI, MIFlags);
48 }
49 
50 
51 void Thumb1FrameLowering::
52 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
53                               MachineBasicBlock::iterator I) const {
54   const Thumb1InstrInfo &TII =
55       *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
56   const Thumb1RegisterInfo *RegInfo =
57       static_cast<const Thumb1RegisterInfo *>(STI.getRegisterInfo());
58   if (!hasReservedCallFrame(MF)) {
59     // If we have alloca, convert as follows:
60     // ADJCALLSTACKDOWN -> sub, sp, sp, amount
61     // ADJCALLSTACKUP   -> add, sp, sp, amount
62     MachineInstr *Old = I;
63     DebugLoc dl = Old->getDebugLoc();
64     unsigned Amount = Old->getOperand(0).getImm();
65     if (Amount != 0) {
66       // We need to keep the stack aligned properly.  To do this, we round the
67       // amount of space needed for the outgoing arguments up to the next
68       // alignment boundary.
69       unsigned Align = getStackAlignment();
70       Amount = (Amount+Align-1)/Align*Align;
71 
72       // Replace the pseudo instruction with a new instruction...
73       unsigned Opc = Old->getOpcode();
74       if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
75         emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
76       } else {
77         assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
78         emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
79       }
80     }
81   }
82   MBB.erase(I);
83 }
84 
85 void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const {
86   MachineBasicBlock &MBB = MF.front();
87   MachineBasicBlock::iterator MBBI = MBB.begin();
88   MachineFrameInfo  *MFI = MF.getFrameInfo();
89   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
90   MachineModuleInfo &MMI = MF.getMMI();
91   const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
92   const Thumb1RegisterInfo *RegInfo =
93       static_cast<const Thumb1RegisterInfo *>(STI.getRegisterInfo());
94   const Thumb1InstrInfo &TII =
95       *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
96 
97   unsigned Align = STI.getFrameLowering()->getStackAlignment();
98   unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
99   unsigned NumBytes = MFI->getStackSize();
100   assert(NumBytes >= ArgRegsSaveSize &&
101          "ArgRegsSaveSize is included in NumBytes");
102   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
103   DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
104   unsigned FramePtr = RegInfo->getFrameRegister(MF);
105   unsigned BasePtr = RegInfo->getBaseRegister();
106   int CFAOffset = 0;
107 
108   // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
109   NumBytes = (NumBytes + 3) & ~3;
110   MFI->setStackSize(NumBytes);
111 
112   // Determine the sizes of each callee-save spill areas and record which frame
113   // belongs to which callee-save spill areas.
114   unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
115   int FramePtrSpillFI = 0;
116 
117   if (ArgRegsSaveSize) {
118     emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
119                  MachineInstr::FrameSetup);
120     CFAOffset -= ArgRegsSaveSize;
121     unsigned CFIIndex = MMI.addFrameInst(
122         MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
123     BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
124         .addCFIIndex(CFIIndex)
125         .setMIFlags(MachineInstr::FrameSetup);
126   }
127 
128   if (!AFI->hasStackFrame()) {
129     if (NumBytes - ArgRegsSaveSize != 0) {
130       emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
131                    MachineInstr::FrameSetup);
132       CFAOffset -= NumBytes - ArgRegsSaveSize;
133       unsigned CFIIndex = MMI.addFrameInst(
134           MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
135       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
136           .addCFIIndex(CFIIndex)
137           .setMIFlags(MachineInstr::FrameSetup);
138     }
139     return;
140   }
141 
142   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
143     unsigned Reg = CSI[i].getReg();
144     int FI = CSI[i].getFrameIdx();
145     switch (Reg) {
146     case ARM::R8:
147     case ARM::R9:
148     case ARM::R10:
149     case ARM::R11:
150       if (STI.isTargetMachO()) {
151         GPRCS2Size += 4;
152         break;
153       }
154       // fallthrough
155     case ARM::R4:
156     case ARM::R5:
157     case ARM::R6:
158     case ARM::R7:
159     case ARM::LR:
160       if (Reg == FramePtr)
161         FramePtrSpillFI = FI;
162       GPRCS1Size += 4;
163       break;
164     default:
165       DPRCSSize += 8;
166     }
167   }
168 
169   if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
170     ++MBBI;
171     if (MBBI != MBB.end())
172       dl = MBBI->getDebugLoc();
173   }
174 
175   // Determine starting offsets of spill areas.
176   unsigned DPRCSOffset  = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);
177   unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
178   unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
179   bool HasFP = hasFP(MF);
180   if (HasFP)
181     AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
182                                 NumBytes);
183   AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
184   AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
185   AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
186   NumBytes = DPRCSOffset;
187 
188   int FramePtrOffsetInBlock = 0;
189   unsigned adjustedGPRCS1Size = GPRCS1Size;
190   if (tryFoldSPUpdateIntoPushPop(STI, MF, std::prev(MBBI), NumBytes)) {
191     FramePtrOffsetInBlock = NumBytes;
192     adjustedGPRCS1Size += NumBytes;
193     NumBytes = 0;
194   }
195 
196   if (adjustedGPRCS1Size) {
197     CFAOffset -= adjustedGPRCS1Size;
198     unsigned CFIIndex = MMI.addFrameInst(
199         MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
200     BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
201         .addCFIIndex(CFIIndex)
202         .setMIFlags(MachineInstr::FrameSetup);
203   }
204   for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
205          E = CSI.end(); I != E; ++I) {
206     unsigned Reg = I->getReg();
207     int FI = I->getFrameIdx();
208     switch (Reg) {
209     case ARM::R8:
210     case ARM::R9:
211     case ARM::R10:
212     case ARM::R11:
213     case ARM::R12:
214       if (STI.isTargetMachO())
215         break;
216       // fallthough
217     case ARM::R0:
218     case ARM::R1:
219     case ARM::R2:
220     case ARM::R3:
221     case ARM::R4:
222     case ARM::R5:
223     case ARM::R6:
224     case ARM::R7:
225     case ARM::LR:
226       unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
227           nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI)));
228       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
229           .addCFIIndex(CFIIndex)
230           .setMIFlags(MachineInstr::FrameSetup);
231       break;
232     }
233   }
234 
235 
236   // Adjust FP so it point to the stack slot that contains the previous FP.
237   if (HasFP) {
238     FramePtrOffsetInBlock += MFI->getObjectOffset(FramePtrSpillFI)
239 		                     + GPRCS1Size + ArgRegsSaveSize;
240     AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
241       .addReg(ARM::SP).addImm(FramePtrOffsetInBlock / 4)
242       .setMIFlags(MachineInstr::FrameSetup));
243     if(FramePtrOffsetInBlock) {
244       CFAOffset += FramePtrOffsetInBlock;
245       unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa(
246           nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
247       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
248           .addCFIIndex(CFIIndex)
249           .setMIFlags(MachineInstr::FrameSetup);
250     } else {
251       unsigned CFIIndex =
252           MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
253               nullptr, MRI->getDwarfRegNum(FramePtr, true)));
254       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
255           .addCFIIndex(CFIIndex)
256           .setMIFlags(MachineInstr::FrameSetup);
257     }
258     if (NumBytes > 508)
259       // If offset is > 508 then sp cannot be adjusted in a single instruction,
260       // try restoring from fp instead.
261       AFI->setShouldRestoreSPFromFP(true);
262   }
263 
264   if (NumBytes) {
265     // Insert it after all the callee-save spills.
266     emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
267                  MachineInstr::FrameSetup);
268     if (!HasFP) {
269       CFAOffset -= NumBytes;
270       unsigned CFIIndex = MMI.addFrameInst(
271           MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
272       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
273           .addCFIIndex(CFIIndex)
274           .setMIFlags(MachineInstr::FrameSetup);
275     }
276   }
277 
278   if (STI.isTargetELF() && HasFP)
279     MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
280                              AFI->getFramePtrSpillOffset());
281 
282   AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
283   AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
284   AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
285 
286   // Thumb1 does not currently support dynamic stack realignment.  Report a
287   // fatal error rather then silently generate bad code.
288   if (RegInfo->needsStackRealignment(MF))
289       report_fatal_error("Dynamic stack realignment not supported for thumb1.");
290 
291   // If we need a base pointer, set it up here. It's whatever the value
292   // of the stack pointer is at this point. Any variable size objects
293   // will be allocated after this, so we can still use the base pointer
294   // to reference locals.
295   if (RegInfo->hasBasePointer(MF))
296     AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
297                    .addReg(ARM::SP));
298 
299   // If the frame has variable sized objects then the epilogue must restore
300   // the sp from fp. We can assume there's an FP here since hasFP already
301   // checks for hasVarSizedObjects.
302   if (MFI->hasVarSizedObjects())
303     AFI->setShouldRestoreSPFromFP(true);
304 }
305 
306 static bool isCSRestore(MachineInstr *MI, const MCPhysReg *CSRegs) {
307   if (MI->getOpcode() == ARM::tLDRspi &&
308       MI->getOperand(1).isFI() &&
309       isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
310     return true;
311   else if (MI->getOpcode() == ARM::tPOP) {
312     // The first two operands are predicates. The last two are
313     // imp-def and imp-use of SP. Check everything in between.
314     for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
315       if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
316         return false;
317     return true;
318   }
319   return false;
320 }
321 
322 void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
323                                    MachineBasicBlock &MBB) const {
324   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
325   assert((MBBI->getOpcode() == ARM::tBX_RET ||
326           MBBI->getOpcode() == ARM::tPOP_RET) &&
327          "Can only insert epilog into returning blocks");
328   DebugLoc dl = MBBI->getDebugLoc();
329   MachineFrameInfo *MFI = MF.getFrameInfo();
330   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
331   const Thumb1RegisterInfo *RegInfo =
332       static_cast<const Thumb1RegisterInfo *>(STI.getRegisterInfo());
333   const Thumb1InstrInfo &TII =
334       *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
335 
336   unsigned Align = STI.getFrameLowering()->getStackAlignment();
337   unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
338   int NumBytes = (int)MFI->getStackSize();
339   assert((unsigned)NumBytes >= ArgRegsSaveSize &&
340          "ArgRegsSaveSize is included in NumBytes");
341   const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs();
342   unsigned FramePtr = RegInfo->getFrameRegister(MF);
343 
344   if (!AFI->hasStackFrame()) {
345     if (NumBytes - ArgRegsSaveSize != 0)
346       emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize);
347   } else {
348     // Unwind MBBI to point to first LDR / VLDRD.
349     if (MBBI != MBB.begin()) {
350       do
351         --MBBI;
352       while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
353       if (!isCSRestore(MBBI, CSRegs))
354         ++MBBI;
355     }
356 
357     // Move SP to start of FP callee save spill area.
358     NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
359                  AFI->getGPRCalleeSavedArea2Size() +
360                  AFI->getDPRCalleeSavedAreaSize() +
361                  ArgRegsSaveSize);
362 
363     if (AFI->shouldRestoreSPFromFP()) {
364       NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
365       // Reset SP based on frame pointer only if the stack frame extends beyond
366       // frame pointer stack slot, the target is ELF and the function has FP, or
367       // the target uses var sized objects.
368       if (NumBytes) {
369         assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
370                "No scratch register to restore SP from FP!");
371         emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
372                                   TII, *RegInfo);
373         AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
374                                ARM::SP)
375           .addReg(ARM::R4));
376       } else
377         AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
378                                ARM::SP)
379           .addReg(FramePtr));
380     } else {
381       if (MBBI->getOpcode() == ARM::tBX_RET &&
382           &MBB.front() != MBBI &&
383           std::prev(MBBI)->getOpcode() == ARM::tPOP) {
384         MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
385         if (!tryFoldSPUpdateIntoPushPop(STI, MF, PMBBI, NumBytes))
386           emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
387       } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes))
388         emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
389     }
390   }
391 
392   bool IsV4PopReturn = false;
393   for (const CalleeSavedInfo &CSI : MFI->getCalleeSavedInfo())
394     if (CSI.getReg() == ARM::LR)
395       IsV4PopReturn = true;
396   IsV4PopReturn &= STI.hasV4TOps() && !STI.hasV5TOps();
397 
398   // Unlike T2 and ARM mode, the T1 pop instruction cannot restore
399   // to LR, and we can't pop the value directly to the PC since
400   // we need to update the SP after popping the value. So instead
401   // we have to emit:
402   //   POP {r3}
403   //   ADD sp, #offset
404   //   BX r3
405   // If this would clobber a return value, then generate this sequence instead:
406   //   MOV ip, r3
407   //   POP {r3}
408   //   ADD sp, #offset
409   //   MOV lr, r3
410   //   MOV r3, ip
411   //   BX lr
412   if (ArgRegsSaveSize || IsV4PopReturn) {
413     // Get the last instruction, tBX_RET
414     MBBI = MBB.getLastNonDebugInstr();
415     assert (MBBI->getOpcode() == ARM::tBX_RET);
416     DebugLoc dl = MBBI->getDebugLoc();
417 
418     if (AFI->getReturnRegsCount() <= 3) {
419       // Epilogue: pop saved LR to R3 and branch off it.
420       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
421         .addReg(ARM::R3, RegState::Define);
422 
423       emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
424 
425       MachineInstrBuilder MIB =
426         BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX))
427         .addReg(ARM::R3, RegState::Kill);
428       AddDefaultPred(MIB);
429       MIB.copyImplicitOps(&*MBBI);
430       // erase the old tBX_RET instruction
431       MBB.erase(MBBI);
432     } else {
433       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
434         .addReg(ARM::R12, RegState::Define)
435         .addReg(ARM::R3, RegState::Kill));
436 
437       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
438         .addReg(ARM::R3, RegState::Define);
439 
440       emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
441 
442       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
443         .addReg(ARM::LR, RegState::Define)
444         .addReg(ARM::R3, RegState::Kill));
445 
446       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
447         .addReg(ARM::R3, RegState::Define)
448         .addReg(ARM::R12, RegState::Kill));
449       // Keep the tBX_RET instruction
450     }
451   }
452 }
453 
454 bool Thumb1FrameLowering::
455 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
456                           MachineBasicBlock::iterator MI,
457                           const std::vector<CalleeSavedInfo> &CSI,
458                           const TargetRegisterInfo *TRI) const {
459   if (CSI.empty())
460     return false;
461 
462   DebugLoc DL;
463   const TargetInstrInfo &TII = *STI.getInstrInfo();
464 
465   if (MI != MBB.end()) DL = MI->getDebugLoc();
466 
467   MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
468   AddDefaultPred(MIB);
469   for (unsigned i = CSI.size(); i != 0; --i) {
470     unsigned Reg = CSI[i-1].getReg();
471     bool isKill = true;
472 
473     // Add the callee-saved register as live-in unless it's LR and
474     // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
475     // then it's already added to the function and entry block live-in sets.
476     if (Reg == ARM::LR) {
477       MachineFunction &MF = *MBB.getParent();
478       if (MF.getFrameInfo()->isReturnAddressTaken() &&
479           MF.getRegInfo().isLiveIn(Reg))
480         isKill = false;
481     }
482 
483     if (isKill)
484       MBB.addLiveIn(Reg);
485 
486     MIB.addReg(Reg, getKillRegState(isKill));
487   }
488   MIB.setMIFlags(MachineInstr::FrameSetup);
489   return true;
490 }
491 
492 bool Thumb1FrameLowering::
493 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
494                             MachineBasicBlock::iterator MI,
495                             const std::vector<CalleeSavedInfo> &CSI,
496                             const TargetRegisterInfo *TRI) const {
497   if (CSI.empty())
498     return false;
499 
500   MachineFunction &MF = *MBB.getParent();
501   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
502   const TargetInstrInfo &TII = *STI.getInstrInfo();
503 
504   bool isVarArg = AFI->getArgRegsSaveSize() > 0;
505   DebugLoc DL = MI->getDebugLoc();
506   MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
507   AddDefaultPred(MIB);
508 
509   bool NumRegs = false;
510   for (unsigned i = CSI.size(); i != 0; --i) {
511     unsigned Reg = CSI[i-1].getReg();
512     if (Reg == ARM::LR) {
513       // Special epilogue for vararg functions. See emitEpilogue
514       if (isVarArg)
515         continue;
516       // ARMv4T requires BX, see emitEpilogue
517       if (STI.hasV4TOps() && !STI.hasV5TOps())
518         continue;
519       Reg = ARM::PC;
520       (*MIB).setDesc(TII.get(ARM::tPOP_RET));
521       MIB.copyImplicitOps(&*MI);
522       MI = MBB.erase(MI);
523     }
524     MIB.addReg(Reg, getDefRegState(true));
525     NumRegs = true;
526   }
527 
528   // It's illegal to emit pop instruction without operands.
529   if (NumRegs)
530     MBB.insert(MI, &*MIB);
531   else
532     MF.DeleteMachineInstr(MIB);
533 
534   return true;
535 }
536