1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides ARM specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMBaseInfo.h"
15 #include "ARMMCAsmInfo.h"
16 #include "ARMMCTargetDesc.h"
17 #include "InstPrinter/ARMInstPrinter.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCELFStreamer.h"
21 #include "llvm/MC/MCInstrAnalysis.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/TargetRegistry.h"
28 
29 using namespace llvm;
30 
31 #define GET_REGINFO_MC_DESC
32 #include "ARMGenRegisterInfo.inc"
33 
34 static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
35                                   std::string &Info) {
36   if (STI.getFeatureBits() & llvm::ARM::HasV7Ops &&
37       (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
38       (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
39       // Checks for the deprecated CP15ISB encoding:
40       // mcr p15, #0, rX, c7, c5, #4
41       (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
42     if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
43       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
44         Info = "deprecated since v7, use 'isb'";
45         return true;
46       }
47 
48       // Checks for the deprecated CP15DSB encoding:
49       // mcr p15, #0, rX, c7, c10, #4
50       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
51         Info = "deprecated since v7, use 'dsb'";
52         return true;
53       }
54     }
55     // Checks for the deprecated CP15DMB encoding:
56     // mcr p15, #0, rX, c7, c10, #5
57     if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
58         (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
59       Info = "deprecated since v7, use 'dmb'";
60       return true;
61     }
62   }
63   return false;
64 }
65 
66 static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
67                                   std::string &Info) {
68   if (STI.getFeatureBits() & llvm::ARM::HasV8Ops &&
69       MI.getOperand(1).isImm() && MI.getOperand(1).getImm() != 8) {
70     Info = "applying IT instruction to more than one subsequent instruction is deprecated";
71     return true;
72   }
73 
74   return false;
75 }
76 
77 #define GET_INSTRINFO_MC_DESC
78 #include "ARMGenInstrInfo.inc"
79 
80 #define GET_SUBTARGETINFO_MC_DESC
81 #include "ARMGenSubtargetInfo.inc"
82 
83 
84 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
85   Triple triple(TT);
86 
87   bool isThumb = triple.getArch() == Triple::thumb ||
88                  triple.getArch() == Triple::thumbeb;
89 
90   bool NoCPU = CPU == "generic" || CPU.empty();
91   std::string ARMArchFeature;
92   switch (triple.getSubArch()) {
93   case Triple::ARMSubArch_v8:
94     if (NoCPU)
95       // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
96       //      FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
97       //      FeatureT2XtPk, FeatureCrypto, FeatureCRC
98       ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
99                        "+trustzone,+t2xtpk,+crypto,+crc";
100     else
101       // Use CPU to figure out the exact features
102       ARMArchFeature = "+v8";
103     break;
104   case Triple::ARMSubArch_v7m:
105     isThumb = true;
106     if (NoCPU)
107       // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
108       ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
109     else
110       // Use CPU to figure out the exact features.
111       ARMArchFeature = "+v7";
112     break;
113   case Triple::ARMSubArch_v7em:
114     if (NoCPU)
115       // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
116       //       FeatureT2XtPk, FeatureMClass
117       ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
118     else
119       // Use CPU to figure out the exact features.
120       ARMArchFeature = "+v7";
121     break;
122   case Triple::ARMSubArch_v7s:
123     if (NoCPU)
124       // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
125       //      Swift
126       ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
127     else
128       // Use CPU to figure out the exact features.
129       ARMArchFeature = "+v7";
130     break;
131   case Triple::ARMSubArch_v7:
132     // v7 CPUs have lots of different feature sets. If no CPU is specified,
133     // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
134     // the "minimum" feature set and use CPU string to figure out the exact
135     // features.
136     if (NoCPU)
137       // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
138       ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
139     else
140       // Use CPU to figure out the exact features.
141       ARMArchFeature = "+v7";
142     break;
143   case Triple::ARMSubArch_v6t2:
144     ARMArchFeature = "+v6t2";
145     break;
146   case Triple::ARMSubArch_v6m:
147     isThumb = true;
148     if (NoCPU)
149       // v6m: FeatureNoARM, FeatureMClass
150       ARMArchFeature = "+v6m,+noarm,+mclass";
151     else
152       ARMArchFeature = "+v6";
153     break;
154   case Triple::ARMSubArch_v6:
155     ARMArchFeature = "+v6";
156     break;
157   case Triple::ARMSubArch_v5te:
158     ARMArchFeature = "+v5te";
159     break;
160   case Triple::ARMSubArch_v5:
161     ARMArchFeature = "+v5t";
162     break;
163   case Triple::ARMSubArch_v4t:
164     ARMArchFeature = "+v4t";
165     break;
166   case Triple::NoSubArch:
167     break;
168   }
169 
170   if (isThumb) {
171     if (ARMArchFeature.empty())
172       ARMArchFeature = "+thumb-mode";
173     else
174       ARMArchFeature += ",+thumb-mode";
175   }
176 
177   if (triple.isOSNaCl()) {
178     if (ARMArchFeature.empty())
179       ARMArchFeature = "+nacl-trap";
180     else
181       ARMArchFeature += ",+nacl-trap";
182   }
183 
184   return ARMArchFeature;
185 }
186 
187 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
188                                                   StringRef FS) {
189   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
190   if (!FS.empty()) {
191     if (!ArchFS.empty())
192       ArchFS = ArchFS + "," + FS.str();
193     else
194       ArchFS = FS;
195   }
196 
197   MCSubtargetInfo *X = new MCSubtargetInfo();
198   InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
199   return X;
200 }
201 
202 static MCInstrInfo *createARMMCInstrInfo() {
203   MCInstrInfo *X = new MCInstrInfo();
204   InitARMMCInstrInfo(X);
205   return X;
206 }
207 
208 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
209   MCRegisterInfo *X = new MCRegisterInfo();
210   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
211   return X;
212 }
213 
214 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
215   Triple TheTriple(TT);
216 
217   MCAsmInfo *MAI;
218   switch (TheTriple.getOS()) {
219   case llvm::Triple::Darwin:
220   case llvm::Triple::IOS:
221   case llvm::Triple::MacOSX:
222     MAI = new ARMMCAsmInfoDarwin(TT);
223     break;
224   case llvm::Triple::Win32:
225     switch (TheTriple.getEnvironment()) {
226     case llvm::Triple::Itanium:
227       MAI = new ARMCOFFMCAsmInfoGNU();
228       break;
229     case llvm::Triple::MSVC:
230       MAI = new ARMCOFFMCAsmInfoMicrosoft();
231       break;
232     default:
233       llvm_unreachable("invalid environment");
234     }
235     break;
236   default:
237     if (TheTriple.isOSBinFormatMachO())
238       MAI = new ARMMCAsmInfoDarwin(TT);
239     else
240       MAI = new ARMELFMCAsmInfo(TT);
241     break;
242   }
243 
244   unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
245   MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
246 
247   return MAI;
248 }
249 
250 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
251                                              CodeModel::Model CM,
252                                              CodeGenOpt::Level OL) {
253   MCCodeGenInfo *X = new MCCodeGenInfo();
254   if (RM == Reloc::Default) {
255     Triple TheTriple(TT);
256     // Default relocation model on Darwin is PIC, not DynamicNoPIC.
257     RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
258   }
259   X->InitMCCodeGenInfo(RM, CM, OL);
260   return X;
261 }
262 
263 // This is duplicated code. Refactor this.
264 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
265                                     MCContext &Ctx, MCAsmBackend &MAB,
266                                     raw_ostream &OS,
267                                     MCCodeEmitter *Emitter,
268                                     const MCSubtargetInfo &STI,
269                                     bool RelaxAll,
270                                     bool NoExecStack) {
271   Triple TheTriple(TT);
272 
273   switch (TheTriple.getObjectFormat()) {
274   default: llvm_unreachable("unsupported object format");
275   case Triple::MachO: {
276     MCStreamer *S = createMachOStreamer(Ctx, MAB, OS, Emitter, false);
277     new ARMTargetStreamer(*S);
278     return S;
279   }
280   case Triple::COFF:
281     assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
282     return createARMWinCOFFStreamer(Ctx, MAB, *Emitter, OS);
283   case Triple::ELF:
284     return createARMELFStreamer(Ctx, MAB, OS, Emitter, false, NoExecStack,
285                                 TheTriple.getArch() == Triple::thumb);
286   }
287 }
288 
289 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
290                                              unsigned SyntaxVariant,
291                                              const MCAsmInfo &MAI,
292                                              const MCInstrInfo &MII,
293                                              const MCRegisterInfo &MRI,
294                                              const MCSubtargetInfo &STI) {
295   if (SyntaxVariant == 0)
296     return new ARMInstPrinter(MAI, MII, MRI, STI);
297   return nullptr;
298 }
299 
300 static MCRelocationInfo *createARMMCRelocationInfo(StringRef TT,
301                                                    MCContext &Ctx) {
302   Triple TheTriple(TT);
303   if (TheTriple.isOSBinFormatMachO())
304     return createARMMachORelocationInfo(Ctx);
305   // Default to the stock relocation info.
306   return llvm::createMCRelocationInfo(TT, Ctx);
307 }
308 
309 namespace {
310 
311 class ARMMCInstrAnalysis : public MCInstrAnalysis {
312 public:
313   ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
314 
315   bool isUnconditionalBranch(const MCInst &Inst) const override {
316     // BCCs with the "always" predicate are unconditional branches.
317     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
318       return true;
319     return MCInstrAnalysis::isUnconditionalBranch(Inst);
320   }
321 
322   bool isConditionalBranch(const MCInst &Inst) const override {
323     // BCCs with the "always" predicate are unconditional branches.
324     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
325       return false;
326     return MCInstrAnalysis::isConditionalBranch(Inst);
327   }
328 
329   bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
330                       uint64_t Size, uint64_t &Target) const override {
331     // We only handle PCRel branches for now.
332     if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
333       return false;
334 
335     int64_t Imm = Inst.getOperand(0).getImm();
336     // FIXME: This is not right for thumb.
337     Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
338     return true;
339   }
340 };
341 
342 }
343 
344 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
345   return new ARMMCInstrAnalysis(Info);
346 }
347 
348 // Force static initialization.
349 extern "C" void LLVMInitializeARMTargetMC() {
350   // Register the MC asm info.
351   RegisterMCAsmInfoFn X(TheARMLETarget, createARMMCAsmInfo);
352   RegisterMCAsmInfoFn Y(TheARMBETarget, createARMMCAsmInfo);
353   RegisterMCAsmInfoFn A(TheThumbLETarget, createARMMCAsmInfo);
354   RegisterMCAsmInfoFn B(TheThumbBETarget, createARMMCAsmInfo);
355 
356   // Register the MC codegen info.
357   TargetRegistry::RegisterMCCodeGenInfo(TheARMLETarget, createARMMCCodeGenInfo);
358   TargetRegistry::RegisterMCCodeGenInfo(TheARMBETarget, createARMMCCodeGenInfo);
359   TargetRegistry::RegisterMCCodeGenInfo(TheThumbLETarget,
360                                         createARMMCCodeGenInfo);
361   TargetRegistry::RegisterMCCodeGenInfo(TheThumbBETarget,
362                                         createARMMCCodeGenInfo);
363 
364   // Register the MC instruction info.
365   TargetRegistry::RegisterMCInstrInfo(TheARMLETarget, createARMMCInstrInfo);
366   TargetRegistry::RegisterMCInstrInfo(TheARMBETarget, createARMMCInstrInfo);
367   TargetRegistry::RegisterMCInstrInfo(TheThumbLETarget, createARMMCInstrInfo);
368   TargetRegistry::RegisterMCInstrInfo(TheThumbBETarget, createARMMCInstrInfo);
369 
370   // Register the MC register info.
371   TargetRegistry::RegisterMCRegInfo(TheARMLETarget, createARMMCRegisterInfo);
372   TargetRegistry::RegisterMCRegInfo(TheARMBETarget, createARMMCRegisterInfo);
373   TargetRegistry::RegisterMCRegInfo(TheThumbLETarget, createARMMCRegisterInfo);
374   TargetRegistry::RegisterMCRegInfo(TheThumbBETarget, createARMMCRegisterInfo);
375 
376   // Register the MC subtarget info.
377   TargetRegistry::RegisterMCSubtargetInfo(TheARMLETarget,
378                                           ARM_MC::createARMMCSubtargetInfo);
379   TargetRegistry::RegisterMCSubtargetInfo(TheARMBETarget,
380                                           ARM_MC::createARMMCSubtargetInfo);
381   TargetRegistry::RegisterMCSubtargetInfo(TheThumbLETarget,
382                                           ARM_MC::createARMMCSubtargetInfo);
383   TargetRegistry::RegisterMCSubtargetInfo(TheThumbBETarget,
384                                           ARM_MC::createARMMCSubtargetInfo);
385 
386   // Register the MC instruction analyzer.
387   TargetRegistry::RegisterMCInstrAnalysis(TheARMLETarget,
388                                           createARMMCInstrAnalysis);
389   TargetRegistry::RegisterMCInstrAnalysis(TheARMBETarget,
390                                           createARMMCInstrAnalysis);
391   TargetRegistry::RegisterMCInstrAnalysis(TheThumbLETarget,
392                                           createARMMCInstrAnalysis);
393   TargetRegistry::RegisterMCInstrAnalysis(TheThumbBETarget,
394                                           createARMMCInstrAnalysis);
395 
396   // Register the MC Code Emitter
397   TargetRegistry::RegisterMCCodeEmitter(TheARMLETarget,
398                                         createARMLEMCCodeEmitter);
399   TargetRegistry::RegisterMCCodeEmitter(TheARMBETarget,
400                                         createARMBEMCCodeEmitter);
401   TargetRegistry::RegisterMCCodeEmitter(TheThumbLETarget,
402                                         createARMLEMCCodeEmitter);
403   TargetRegistry::RegisterMCCodeEmitter(TheThumbBETarget,
404                                         createARMBEMCCodeEmitter);
405 
406   // Register the asm backend.
407   TargetRegistry::RegisterMCAsmBackend(TheARMLETarget, createARMLEAsmBackend);
408   TargetRegistry::RegisterMCAsmBackend(TheARMBETarget, createARMBEAsmBackend);
409   TargetRegistry::RegisterMCAsmBackend(TheThumbLETarget,
410                                        createThumbLEAsmBackend);
411   TargetRegistry::RegisterMCAsmBackend(TheThumbBETarget,
412                                        createThumbBEAsmBackend);
413 
414   // Register the object streamer.
415   TargetRegistry::RegisterMCObjectStreamer(TheARMLETarget, createMCStreamer);
416   TargetRegistry::RegisterMCObjectStreamer(TheARMBETarget, createMCStreamer);
417   TargetRegistry::RegisterMCObjectStreamer(TheThumbLETarget, createMCStreamer);
418   TargetRegistry::RegisterMCObjectStreamer(TheThumbBETarget, createMCStreamer);
419 
420   // Register the asm streamer.
421   TargetRegistry::RegisterAsmStreamer(TheARMLETarget, createMCAsmStreamer);
422   TargetRegistry::RegisterAsmStreamer(TheARMBETarget, createMCAsmStreamer);
423   TargetRegistry::RegisterAsmStreamer(TheThumbLETarget, createMCAsmStreamer);
424   TargetRegistry::RegisterAsmStreamer(TheThumbBETarget, createMCAsmStreamer);
425 
426   // Register the null streamer.
427   TargetRegistry::RegisterNullStreamer(TheARMLETarget, createARMNullStreamer);
428   TargetRegistry::RegisterNullStreamer(TheARMBETarget, createARMNullStreamer);
429   TargetRegistry::RegisterNullStreamer(TheThumbLETarget, createARMNullStreamer);
430   TargetRegistry::RegisterNullStreamer(TheThumbBETarget, createARMNullStreamer);
431 
432   // Register the MCInstPrinter.
433   TargetRegistry::RegisterMCInstPrinter(TheARMLETarget, createARMMCInstPrinter);
434   TargetRegistry::RegisterMCInstPrinter(TheARMBETarget, createARMMCInstPrinter);
435   TargetRegistry::RegisterMCInstPrinter(TheThumbLETarget,
436                                         createARMMCInstPrinter);
437   TargetRegistry::RegisterMCInstPrinter(TheThumbBETarget,
438                                         createARMMCInstPrinter);
439 
440   // Register the MC relocation info.
441   TargetRegistry::RegisterMCRelocationInfo(TheARMLETarget,
442                                            createARMMCRelocationInfo);
443   TargetRegistry::RegisterMCRelocationInfo(TheARMBETarget,
444                                            createARMMCRelocationInfo);
445   TargetRegistry::RegisterMCRelocationInfo(TheThumbLETarget,
446                                            createARMMCRelocationInfo);
447   TargetRegistry::RegisterMCRelocationInfo(TheThumbBETarget,
448                                            createARMMCRelocationInfo);
449 }
450