1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides ARM specific target descriptions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "ARMBaseInfo.h" 15 #include "ARMMCAsmInfo.h" 16 #include "ARMMCTargetDesc.h" 17 #include "InstPrinter/ARMInstPrinter.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/MC/MCCodeGenInfo.h" 20 #include "llvm/MC/MCELFStreamer.h" 21 #include "llvm/MC/MCInstrAnalysis.h" 22 #include "llvm/MC/MCInstrInfo.h" 23 #include "llvm/MC/MCRegisterInfo.h" 24 #include "llvm/MC/MCStreamer.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/TargetRegistry.h" 28 29 using namespace llvm; 30 31 #define GET_REGINFO_MC_DESC 32 #include "ARMGenRegisterInfo.inc" 33 34 static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, 35 std::string &Info) { 36 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && 37 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && 38 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && 39 // Checks for the deprecated CP15ISB encoding: 40 // mcr p15, #0, rX, c7, c5, #4 41 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { 42 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { 43 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) { 44 Info = "deprecated since v7, use 'isb'"; 45 return true; 46 } 47 48 // Checks for the deprecated CP15DSB encoding: 49 // mcr p15, #0, rX, c7, c10, #4 50 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) { 51 Info = "deprecated since v7, use 'dsb'"; 52 return true; 53 } 54 } 55 // Checks for the deprecated CP15DMB encoding: 56 // mcr p15, #0, rX, c7, c10, #5 57 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 && 58 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) { 59 Info = "deprecated since v7, use 'dmb'"; 60 return true; 61 } 62 } 63 return false; 64 } 65 66 static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, 67 std::string &Info) { 68 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() && 69 MI.getOperand(1).getImm() != 8) { 70 Info = "applying IT instruction to more than one subsequent instruction is " 71 "deprecated"; 72 return true; 73 } 74 75 return false; 76 } 77 78 static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, 79 std::string &Info) { 80 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] && 81 "cannot predicate thumb instructions"); 82 83 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments"); 84 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) { 85 assert(MI.getOperand(OI).isReg() && "expected register"); 86 if (MI.getOperand(OI).getReg() == ARM::SP || 87 MI.getOperand(OI).getReg() == ARM::PC) { 88 Info = "use of SP or PC in the list is deprecated"; 89 return true; 90 } 91 } 92 return false; 93 } 94 95 static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, 96 std::string &Info) { 97 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] && 98 "cannot predicate thumb instructions"); 99 100 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments"); 101 bool ListContainsPC = false, ListContainsLR = false; 102 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) { 103 assert(MI.getOperand(OI).isReg() && "expected register"); 104 switch (MI.getOperand(OI).getReg()) { 105 default: 106 break; 107 case ARM::LR: 108 ListContainsLR = true; 109 break; 110 case ARM::PC: 111 ListContainsPC = true; 112 break; 113 case ARM::SP: 114 Info = "use of SP in the list is deprecated"; 115 return true; 116 } 117 } 118 119 if (ListContainsPC && ListContainsLR) { 120 Info = "use of LR and PC simultaneously in the list is deprecated"; 121 return true; 122 } 123 124 return false; 125 } 126 127 #define GET_INSTRINFO_MC_DESC 128 #include "ARMGenInstrInfo.inc" 129 130 #define GET_SUBTARGETINFO_MC_DESC 131 #include "ARMGenSubtargetInfo.inc" 132 133 std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) { 134 bool isThumb = 135 TT.getArch() == Triple::thumb || TT.getArch() == Triple::thumbeb; 136 137 bool NoCPU = CPU == "generic" || CPU.empty(); 138 std::string ARMArchFeature; 139 switch (TT.getSubArch()) { 140 default: 141 llvm_unreachable("invalid sub-architecture for ARM"); 142 case Triple::ARMSubArch_v8: 143 if (NoCPU) 144 // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, 145 // FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone, 146 // FeatureT2XtPk, FeatureCrypto, FeatureCRC 147 ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+dsp,+mp,+hwdiv,+hwdiv-arm," 148 "+trustzone,+t2xtpk,+crypto,+crc"; 149 else 150 // Use CPU to figure out the exact features 151 ARMArchFeature = "+v8"; 152 break; 153 case Triple::ARMSubArch_v8_1a: 154 if (NoCPU) 155 // v8.1a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, 156 // FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone, 157 // FeatureT2XtPk, FeatureCrypto, FeatureCRC, FeatureV8_1a 158 ARMArchFeature = "+v8.1a,+db,+fp-armv8,+neon,+dsp,+mp,+hwdiv,+hwdiv-arm," 159 "+trustzone,+t2xtpk,+crypto,+crc"; 160 else 161 // Use CPU to figure out the exact features 162 ARMArchFeature = "+v8.1a"; 163 break; 164 case Triple::ARMSubArch_v7m: 165 isThumb = true; 166 if (NoCPU) 167 // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass 168 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass"; 169 else 170 // Use CPU to figure out the exact features. 171 ARMArchFeature = "+v7"; 172 break; 173 case Triple::ARMSubArch_v7em: 174 if (NoCPU) 175 // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSP, 176 // FeatureT2XtPk, FeatureMClass 177 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+dsp,+t2xtpk,+mclass"; 178 else 179 // Use CPU to figure out the exact features. 180 ARMArchFeature = "+v7"; 181 break; 182 case Triple::ARMSubArch_v7s: 183 if (NoCPU) 184 // v7s: FeatureNEON, FeatureDB, FeatureDSP, FeatureHasRAS 185 // Swift 186 ARMArchFeature = "+v7,+swift,+neon,+db,+dsp,+ras"; 187 else 188 // Use CPU to figure out the exact features. 189 ARMArchFeature = "+v7"; 190 break; 191 case Triple::ARMSubArch_v7k: 192 if (NoCPU) 193 // v7k: FeatureNEON, FeatureDB, FeatureDSP, FeatureHasRAS 194 // A7 195 ARMArchFeature = "+v7,+a7,+neon,+db,+dsp,+ras"; 196 else 197 // Use CPU to figure out the exact features. 198 ARMArchFeature = "+v7"; 199 break; 200 case Triple::ARMSubArch_v7: 201 // v7 CPUs have lots of different feature sets. If no CPU is specified, 202 // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return 203 // the "minimum" feature set and use CPU string to figure out the exact 204 // features. 205 if (NoCPU) 206 // v7a: FeatureNEON, FeatureDB, FeatureDSP, FeatureT2XtPk 207 ARMArchFeature = "+v7,+neon,+db,+dsp,+t2xtpk"; 208 else 209 // Use CPU to figure out the exact features. 210 ARMArchFeature = "+v7"; 211 break; 212 case Triple::ARMSubArch_v6t2: 213 ARMArchFeature = "+v6t2"; 214 break; 215 case Triple::ARMSubArch_v6k: 216 ARMArchFeature = "+v6k"; 217 break; 218 case Triple::ARMSubArch_v6m: 219 isThumb = true; 220 if (NoCPU) 221 // v6m: FeatureNoARM, FeatureMClass 222 ARMArchFeature = "+v6m,+noarm,+mclass"; 223 else 224 ARMArchFeature = "+v6"; 225 break; 226 case Triple::ARMSubArch_v6: 227 ARMArchFeature = "+v6"; 228 break; 229 case Triple::ARMSubArch_v5te: 230 ARMArchFeature = "+v5te"; 231 break; 232 case Triple::ARMSubArch_v5: 233 ARMArchFeature = "+v5t"; 234 break; 235 case Triple::ARMSubArch_v4t: 236 ARMArchFeature = "+v4t"; 237 break; 238 case Triple::NoSubArch: 239 break; 240 } 241 242 if (isThumb) { 243 if (ARMArchFeature.empty()) 244 ARMArchFeature = "+thumb-mode"; 245 else 246 ARMArchFeature += ",+thumb-mode"; 247 } 248 249 if (TT.isOSNaCl()) { 250 if (ARMArchFeature.empty()) 251 ARMArchFeature = "+nacl-trap"; 252 else 253 ARMArchFeature += ",+nacl-trap"; 254 } 255 256 return ARMArchFeature; 257 } 258 259 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT, 260 StringRef CPU, StringRef FS) { 261 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU); 262 if (!FS.empty()) { 263 if (!ArchFS.empty()) 264 ArchFS = (Twine(ArchFS) + "," + FS).str(); 265 else 266 ArchFS = FS; 267 } 268 269 return createARMMCSubtargetInfoImpl(TT, CPU, ArchFS); 270 } 271 272 static MCInstrInfo *createARMMCInstrInfo() { 273 MCInstrInfo *X = new MCInstrInfo(); 274 InitARMMCInstrInfo(X); 275 return X; 276 } 277 278 static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) { 279 MCRegisterInfo *X = new MCRegisterInfo(); 280 InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC); 281 return X; 282 } 283 284 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, 285 const Triple &TheTriple) { 286 MCAsmInfo *MAI; 287 if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO()) 288 MAI = new ARMMCAsmInfoDarwin(TheTriple); 289 else if (TheTriple.isWindowsMSVCEnvironment()) 290 MAI = new ARMCOFFMCAsmInfoMicrosoft(); 291 else if (TheTriple.isOSWindows()) 292 MAI = new ARMCOFFMCAsmInfoGNU(); 293 else 294 MAI = new ARMELFMCAsmInfo(TheTriple); 295 296 unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true); 297 MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0)); 298 299 return MAI; 300 } 301 302 static MCCodeGenInfo *createARMMCCodeGenInfo(const Triple &TT, Reloc::Model RM, 303 CodeModel::Model CM, 304 CodeGenOpt::Level OL) { 305 MCCodeGenInfo *X = new MCCodeGenInfo(); 306 if (RM == Reloc::Default) { 307 // Default relocation model on Darwin is PIC, not DynamicNoPIC. 308 RM = TT.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC; 309 } 310 X->initMCCodeGenInfo(RM, CM, OL); 311 return X; 312 } 313 314 static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx, 315 MCAsmBackend &MAB, raw_pwrite_stream &OS, 316 MCCodeEmitter *Emitter, bool RelaxAll) { 317 return createARMELFStreamer(Ctx, MAB, OS, Emitter, false, 318 T.getArch() == Triple::thumb); 319 } 320 321 static MCStreamer *createARMMachOStreamer(MCContext &Ctx, MCAsmBackend &MAB, 322 raw_pwrite_stream &OS, 323 MCCodeEmitter *Emitter, bool RelaxAll, 324 bool DWARFMustBeAtTheEnd) { 325 return createMachOStreamer(Ctx, MAB, OS, Emitter, false, DWARFMustBeAtTheEnd); 326 } 327 328 static MCInstPrinter *createARMMCInstPrinter(const Triple &T, 329 unsigned SyntaxVariant, 330 const MCAsmInfo &MAI, 331 const MCInstrInfo &MII, 332 const MCRegisterInfo &MRI) { 333 if (SyntaxVariant == 0) 334 return new ARMInstPrinter(MAI, MII, MRI); 335 return nullptr; 336 } 337 338 static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT, 339 MCContext &Ctx) { 340 if (TT.isOSBinFormatMachO()) 341 return createARMMachORelocationInfo(Ctx); 342 // Default to the stock relocation info. 343 return llvm::createMCRelocationInfo(TT, Ctx); 344 } 345 346 namespace { 347 348 class ARMMCInstrAnalysis : public MCInstrAnalysis { 349 public: 350 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {} 351 352 bool isUnconditionalBranch(const MCInst &Inst) const override { 353 // BCCs with the "always" predicate are unconditional branches. 354 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL) 355 return true; 356 return MCInstrAnalysis::isUnconditionalBranch(Inst); 357 } 358 359 bool isConditionalBranch(const MCInst &Inst) const override { 360 // BCCs with the "always" predicate are unconditional branches. 361 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL) 362 return false; 363 return MCInstrAnalysis::isConditionalBranch(Inst); 364 } 365 366 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, 367 uint64_t Size, uint64_t &Target) const override { 368 // We only handle PCRel branches for now. 369 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL) 370 return false; 371 372 int64_t Imm = Inst.getOperand(0).getImm(); 373 // FIXME: This is not right for thumb. 374 Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes. 375 return true; 376 } 377 }; 378 379 } 380 381 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) { 382 return new ARMMCInstrAnalysis(Info); 383 } 384 385 // Force static initialization. 386 extern "C" void LLVMInitializeARMTargetMC() { 387 for (Target *T : {&TheARMLETarget, &TheARMBETarget, &TheThumbLETarget, 388 &TheThumbBETarget}) { 389 // Register the MC asm info. 390 RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo); 391 392 // Register the MC codegen info. 393 TargetRegistry::RegisterMCCodeGenInfo(*T, createARMMCCodeGenInfo); 394 395 // Register the MC instruction info. 396 TargetRegistry::RegisterMCInstrInfo(*T, createARMMCInstrInfo); 397 398 // Register the MC register info. 399 TargetRegistry::RegisterMCRegInfo(*T, createARMMCRegisterInfo); 400 401 // Register the MC subtarget info. 402 TargetRegistry::RegisterMCSubtargetInfo(*T, 403 ARM_MC::createARMMCSubtargetInfo); 404 405 // Register the MC instruction analyzer. 406 TargetRegistry::RegisterMCInstrAnalysis(*T, createARMMCInstrAnalysis); 407 408 TargetRegistry::RegisterELFStreamer(*T, createELFStreamer); 409 TargetRegistry::RegisterCOFFStreamer(*T, createARMWinCOFFStreamer); 410 TargetRegistry::RegisterMachOStreamer(*T, createARMMachOStreamer); 411 412 // Register the obj target streamer. 413 TargetRegistry::RegisterObjectTargetStreamer(*T, 414 createARMObjectTargetStreamer); 415 416 // Register the asm streamer. 417 TargetRegistry::RegisterAsmTargetStreamer(*T, createARMTargetAsmStreamer); 418 419 // Register the null TargetStreamer. 420 TargetRegistry::RegisterNullTargetStreamer(*T, createARMNullTargetStreamer); 421 422 // Register the MCInstPrinter. 423 TargetRegistry::RegisterMCInstPrinter(*T, createARMMCInstPrinter); 424 425 // Register the MC relocation info. 426 TargetRegistry::RegisterMCRelocationInfo(*T, createARMMCRelocationInfo); 427 } 428 429 // Register the MC Code Emitter 430 for (Target *T : {&TheARMLETarget, &TheThumbLETarget}) 431 TargetRegistry::RegisterMCCodeEmitter(*T, createARMLEMCCodeEmitter); 432 for (Target *T : {&TheARMBETarget, &TheThumbBETarget}) 433 TargetRegistry::RegisterMCCodeEmitter(*T, createARMBEMCCodeEmitter); 434 435 // Register the asm backend. 436 TargetRegistry::RegisterMCAsmBackend(TheARMLETarget, createARMLEAsmBackend); 437 TargetRegistry::RegisterMCAsmBackend(TheARMBETarget, createARMBEAsmBackend); 438 TargetRegistry::RegisterMCAsmBackend(TheThumbLETarget, 439 createThumbLEAsmBackend); 440 TargetRegistry::RegisterMCAsmBackend(TheThumbBETarget, 441 createThumbBEAsmBackend); 442 } 443