1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions -----------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides ARM specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMMCTargetDesc.h"
15 #include "ARMMCAsmInfo.h"
16 #include "ARMBaseInfo.h"
17 #include "InstPrinter/ARMInstPrinter.h"
18 #include "llvm/MC/MCCodeGenInfo.h"
19 #include "llvm/MC/MCInstrAnalysis.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCStreamer.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/TargetRegistry.h"
26 
27 #define GET_REGINFO_MC_DESC
28 #include "ARMGenRegisterInfo.inc"
29 
30 #define GET_INSTRINFO_MC_DESC
31 #include "ARMGenInstrInfo.inc"
32 
33 #define GET_SUBTARGETINFO_MC_DESC
34 #include "ARMGenSubtargetInfo.inc"
35 
36 using namespace llvm;
37 
38 std::string ARM_MC::ParseARMTriple(StringRef TT) {
39   // Set the boolean corresponding to the current target triple, or the default
40   // if one cannot be determined, to true.
41   unsigned Len = TT.size();
42   unsigned Idx = 0;
43 
44   // FIXME: Enhance Triple helper class to extract ARM version.
45   bool isThumb = false;
46   if (Len >= 5 && TT.substr(0, 4) == "armv")
47     Idx = 4;
48   else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
49     isThumb = true;
50     if (Len >= 7 && TT[5] == 'v')
51       Idx = 6;
52   }
53 
54   std::string ARMArchFeature;
55   if (Idx) {
56     unsigned SubVer = TT[Idx];
57     if (SubVer >= '7' && SubVer <= '9') {
58       if (Len >= Idx+2 && TT[Idx+1] == 'm') {
59         // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
60         ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
61       } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
62         // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
63         //       FeatureT2XtPk, FeatureMClass
64         ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
65       } else
66         // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
67         ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
68     } else if (SubVer == '6') {
69       if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
70         ARMArchFeature = "+v6t2";
71       else if (Len >= Idx+2 && TT[Idx+1] == 'm')
72         // v6m: FeatureNoARM, FeatureMClass
73         ARMArchFeature = "+v6t2,+noarm,+mclass";
74       else
75         ARMArchFeature = "+v6";
76     } else if (SubVer == '5') {
77       if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
78         ARMArchFeature = "+v5te";
79       else
80         ARMArchFeature = "+v5t";
81     } else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
82       ARMArchFeature = "+v4t";
83   }
84 
85   if (isThumb) {
86     if (ARMArchFeature.empty())
87       ARMArchFeature = "+thumb-mode";
88     else
89       ARMArchFeature += ",+thumb-mode";
90   }
91 
92   return ARMArchFeature;
93 }
94 
95 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
96                                                   StringRef FS) {
97   std::string ArchFS = ARM_MC::ParseARMTriple(TT);
98   if (!FS.empty()) {
99     if (!ArchFS.empty())
100       ArchFS = ArchFS + "," + FS.str();
101     else
102       ArchFS = FS;
103   }
104 
105   MCSubtargetInfo *X = new MCSubtargetInfo();
106   InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
107   return X;
108 }
109 
110 static MCInstrInfo *createARMMCInstrInfo() {
111   MCInstrInfo *X = new MCInstrInfo();
112   InitARMMCInstrInfo(X);
113   return X;
114 }
115 
116 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
117   MCRegisterInfo *X = new MCRegisterInfo();
118   InitARMMCRegisterInfo(X, ARM::LR);
119   return X;
120 }
121 
122 static MCAsmInfo *createARMMCAsmInfo(const Target &T, StringRef TT) {
123   Triple TheTriple(TT);
124 
125   if (TheTriple.isOSDarwin())
126     return new ARMMCAsmInfoDarwin();
127 
128   return new ARMELFMCAsmInfo();
129 }
130 
131 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
132                                              CodeModel::Model CM,
133                                              CodeGenOpt::Level OL) {
134   MCCodeGenInfo *X = new MCCodeGenInfo();
135   if (RM == Reloc::Default) {
136     Triple TheTriple(TT);
137     // Default relocation model on Darwin is PIC, not DynamicNoPIC.
138     RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
139   }
140   X->InitMCCodeGenInfo(RM, CM, OL);
141   return X;
142 }
143 
144 // This is duplicated code. Refactor this.
145 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
146                                     MCContext &Ctx, MCAsmBackend &MAB,
147                                     raw_ostream &OS,
148                                     MCCodeEmitter *Emitter,
149                                     bool RelaxAll,
150                                     bool NoExecStack) {
151   Triple TheTriple(TT);
152 
153   if (TheTriple.isOSDarwin())
154     return createMachOStreamer(Ctx, MAB, OS, Emitter, RelaxAll);
155 
156   if (TheTriple.isOSWindows()) {
157     llvm_unreachable("ARM does not support Windows COFF format");
158     return NULL;
159   }
160 
161   return createELFStreamer(Ctx, MAB, OS, Emitter, RelaxAll, NoExecStack);
162 }
163 
164 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
165                                              unsigned SyntaxVariant,
166                                              const MCAsmInfo &MAI,
167                                              const MCSubtargetInfo &STI) {
168   if (SyntaxVariant == 0)
169     return new ARMInstPrinter(MAI, STI);
170   return 0;
171 }
172 
173 namespace {
174 
175 class ARMMCInstrAnalysis : public MCInstrAnalysis {
176 public:
177   ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
178 
179   virtual bool isUnconditionalBranch(const MCInst &Inst) const {
180     // BCCs with the "always" predicate are unconditional branches.
181     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
182       return true;
183     return MCInstrAnalysis::isUnconditionalBranch(Inst);
184   }
185 
186   virtual bool isConditionalBranch(const MCInst &Inst) const {
187     // BCCs with the "always" predicate are unconditional branches.
188     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
189       return false;
190     return MCInstrAnalysis::isConditionalBranch(Inst);
191   }
192 
193   uint64_t evaluateBranch(const MCInst &Inst, uint64_t Addr,
194                           uint64_t Size) const {
195     // We only handle PCRel branches for now.
196     if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
197       return -1ULL;
198 
199     int64_t Imm = Inst.getOperand(0).getImm();
200     // FIXME: This is not right for thumb.
201     return Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
202   }
203 };
204 
205 }
206 
207 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
208   return new ARMMCInstrAnalysis(Info);
209 }
210 
211 // Force static initialization.
212 extern "C" void LLVMInitializeARMTargetMC() {
213   // Register the MC asm info.
214   RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo);
215   RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
216 
217   // Register the MC codegen info.
218   TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo);
219   TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo);
220 
221   // Register the MC instruction info.
222   TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
223   TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
224 
225   // Register the MC register info.
226   TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
227   TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
228 
229   // Register the MC subtarget info.
230   TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
231                                           ARM_MC::createARMMCSubtargetInfo);
232   TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
233                                           ARM_MC::createARMMCSubtargetInfo);
234 
235   // Register the MC instruction analyzer.
236   TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget,
237                                           createARMMCInstrAnalysis);
238   TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget,
239                                           createARMMCInstrAnalysis);
240 
241   // Register the MC Code Emitter
242   TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
243   TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
244 
245   // Register the asm backend.
246   TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend);
247   TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend);
248 
249   // Register the object streamer.
250   TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer);
251   TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer);
252 
253   // Register the MCInstPrinter.
254   TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
255   TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
256 }
257