1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides ARM specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMMCTargetDesc.h"
14 #include "ARMBaseInfo.h"
15 #include "ARMInstPrinter.h"
16 #include "ARMMCAsmInfo.h"
17 #include "TargetInfo/ARMTargetInfo.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/DebugInfo/CodeView/CodeView.h"
20 #include "llvm/MC/MCAsmBackend.h"
21 #include "llvm/MC/MCCodeEmitter.h"
22 #include "llvm/MC/MCELFStreamer.h"
23 #include "llvm/MC/MCInstrAnalysis.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCObjectWriter.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCStreamer.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/TargetParser.h"
31 #include "llvm/Support/TargetRegistry.h"
32 
33 using namespace llvm;
34 
35 #define GET_REGINFO_MC_DESC
36 #include "ARMGenRegisterInfo.inc"
37 
38 static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
39                                   std::string &Info) {
40   if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
41       (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
42       (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
43       // Checks for the deprecated CP15ISB encoding:
44       // mcr p15, #0, rX, c7, c5, #4
45       (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
46     if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
47       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
48         Info = "deprecated since v7, use 'isb'";
49         return true;
50       }
51 
52       // Checks for the deprecated CP15DSB encoding:
53       // mcr p15, #0, rX, c7, c10, #4
54       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
55         Info = "deprecated since v7, use 'dsb'";
56         return true;
57       }
58     }
59     // Checks for the deprecated CP15DMB encoding:
60     // mcr p15, #0, rX, c7, c10, #5
61     if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
62         (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
63       Info = "deprecated since v7, use 'dmb'";
64       return true;
65     }
66   }
67   if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
68       ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) ||
69        (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) {
70     Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
71            "point instructions";
72     return true;
73   }
74   return false;
75 }
76 
77 static bool getMRCDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
78                                   std::string &Info) {
79   if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
80       ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) ||
81        (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) {
82     Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
83            "point instructions";
84     return true;
85   }
86   return false;
87 }
88 
89 static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
90                                  std::string &Info) {
91   if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() &&
92       MI.getOperand(1).getImm() != 8) {
93     Info = "applying IT instruction to more than one subsequent instruction is "
94            "deprecated";
95     return true;
96   }
97 
98   return false;
99 }
100 
101 static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
102                                        std::string &Info) {
103   assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
104          "cannot predicate thumb instructions");
105 
106   assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
107   for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
108     assert(MI.getOperand(OI).isReg() && "expected register");
109     if (MI.getOperand(OI).getReg() == ARM::SP ||
110         MI.getOperand(OI).getReg() == ARM::PC) {
111       Info = "use of SP or PC in the list is deprecated";
112       return true;
113     }
114   }
115   return false;
116 }
117 
118 static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
119                                       std::string &Info) {
120   assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
121          "cannot predicate thumb instructions");
122 
123   assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
124   bool ListContainsPC = false, ListContainsLR = false;
125   for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
126     assert(MI.getOperand(OI).isReg() && "expected register");
127     switch (MI.getOperand(OI).getReg()) {
128     default:
129       break;
130     case ARM::LR:
131       ListContainsLR = true;
132       break;
133     case ARM::PC:
134       ListContainsPC = true;
135       break;
136     case ARM::SP:
137       Info = "use of SP in the list is deprecated";
138       return true;
139     }
140   }
141 
142   if (ListContainsPC && ListContainsLR) {
143     Info = "use of LR and PC simultaneously in the list is deprecated";
144     return true;
145   }
146 
147   return false;
148 }
149 
150 #define GET_INSTRINFO_MC_DESC
151 #include "ARMGenInstrInfo.inc"
152 
153 #define GET_SUBTARGETINFO_MC_DESC
154 #include "ARMGenSubtargetInfo.inc"
155 
156 std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
157   std::string ARMArchFeature;
158 
159   ARM::ArchKind ArchID = ARM::parseArch(TT.getArchName());
160   if (ArchID != ARM::ArchKind::INVALID &&  (CPU.empty() || CPU == "generic"))
161     ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(ArchID)).str();
162 
163   if (TT.isThumb()) {
164     if (!ARMArchFeature.empty())
165       ARMArchFeature += ",";
166     ARMArchFeature += "+thumb-mode,+v4t";
167   }
168 
169   if (TT.isOSNaCl()) {
170     if (!ARMArchFeature.empty())
171       ARMArchFeature += ",";
172     ARMArchFeature += "+nacl-trap";
173   }
174 
175   if (TT.isOSWindows()) {
176     if (!ARMArchFeature.empty())
177       ARMArchFeature += ",";
178     ARMArchFeature += "+noarm";
179   }
180 
181   return ARMArchFeature;
182 }
183 
184 bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo *MCII) {
185   const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
186   int PredOpIdx = Desc.findFirstPredOperandIdx();
187   return PredOpIdx != -1 && MI.getOperand(PredOpIdx).getImm() != ARMCC::AL;
188 }
189 
190 bool ARM_MC::isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII) {
191   const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
192   for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
193     const MCOperand &MO = MI.getOperand(I);
194     if (MO.isReg() && MO.getReg() == ARM::CPSR &&
195         Desc.OpInfo[I].isOptionalDef())
196       return true;
197   }
198   return false;
199 }
200 
201 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
202                                                   StringRef CPU, StringRef FS) {
203   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
204   if (!FS.empty()) {
205     if (!ArchFS.empty())
206       ArchFS = (Twine(ArchFS) + "," + FS).str();
207     else
208       ArchFS = std::string(FS);
209   }
210 
211   return createARMMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS);
212 }
213 
214 static MCInstrInfo *createARMMCInstrInfo() {
215   MCInstrInfo *X = new MCInstrInfo();
216   InitARMMCInstrInfo(X);
217   return X;
218 }
219 
220 void ARM_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
221   // Mapping from CodeView to MC register id.
222   static const struct {
223     codeview::RegisterId CVReg;
224     MCPhysReg Reg;
225   } RegMap[] = {
226       {codeview::RegisterId::ARM_R0, ARM::R0},
227       {codeview::RegisterId::ARM_R1, ARM::R1},
228       {codeview::RegisterId::ARM_R2, ARM::R2},
229       {codeview::RegisterId::ARM_R3, ARM::R3},
230       {codeview::RegisterId::ARM_R4, ARM::R4},
231       {codeview::RegisterId::ARM_R5, ARM::R5},
232       {codeview::RegisterId::ARM_R6, ARM::R6},
233       {codeview::RegisterId::ARM_R7, ARM::R7},
234       {codeview::RegisterId::ARM_R8, ARM::R8},
235       {codeview::RegisterId::ARM_R9, ARM::R9},
236       {codeview::RegisterId::ARM_R10, ARM::R10},
237       {codeview::RegisterId::ARM_R11, ARM::R11},
238       {codeview::RegisterId::ARM_R12, ARM::R12},
239       {codeview::RegisterId::ARM_SP, ARM::SP},
240       {codeview::RegisterId::ARM_LR, ARM::LR},
241       {codeview::RegisterId::ARM_PC, ARM::PC},
242       {codeview::RegisterId::ARM_CPSR, ARM::CPSR},
243       {codeview::RegisterId::ARM_FPSCR, ARM::FPSCR},
244       {codeview::RegisterId::ARM_FPEXC, ARM::FPEXC},
245       {codeview::RegisterId::ARM_FS0, ARM::S0},
246       {codeview::RegisterId::ARM_FS1, ARM::S1},
247       {codeview::RegisterId::ARM_FS2, ARM::S2},
248       {codeview::RegisterId::ARM_FS3, ARM::S3},
249       {codeview::RegisterId::ARM_FS4, ARM::S4},
250       {codeview::RegisterId::ARM_FS5, ARM::S5},
251       {codeview::RegisterId::ARM_FS6, ARM::S6},
252       {codeview::RegisterId::ARM_FS7, ARM::S7},
253       {codeview::RegisterId::ARM_FS8, ARM::S8},
254       {codeview::RegisterId::ARM_FS9, ARM::S9},
255       {codeview::RegisterId::ARM_FS10, ARM::S10},
256       {codeview::RegisterId::ARM_FS11, ARM::S11},
257       {codeview::RegisterId::ARM_FS12, ARM::S12},
258       {codeview::RegisterId::ARM_FS13, ARM::S13},
259       {codeview::RegisterId::ARM_FS14, ARM::S14},
260       {codeview::RegisterId::ARM_FS15, ARM::S15},
261       {codeview::RegisterId::ARM_FS16, ARM::S16},
262       {codeview::RegisterId::ARM_FS17, ARM::S17},
263       {codeview::RegisterId::ARM_FS18, ARM::S18},
264       {codeview::RegisterId::ARM_FS19, ARM::S19},
265       {codeview::RegisterId::ARM_FS20, ARM::S20},
266       {codeview::RegisterId::ARM_FS21, ARM::S21},
267       {codeview::RegisterId::ARM_FS22, ARM::S22},
268       {codeview::RegisterId::ARM_FS23, ARM::S23},
269       {codeview::RegisterId::ARM_FS24, ARM::S24},
270       {codeview::RegisterId::ARM_FS25, ARM::S25},
271       {codeview::RegisterId::ARM_FS26, ARM::S26},
272       {codeview::RegisterId::ARM_FS27, ARM::S27},
273       {codeview::RegisterId::ARM_FS28, ARM::S28},
274       {codeview::RegisterId::ARM_FS29, ARM::S29},
275       {codeview::RegisterId::ARM_FS30, ARM::S30},
276       {codeview::RegisterId::ARM_FS31, ARM::S31},
277       {codeview::RegisterId::ARM_ND0, ARM::D0},
278       {codeview::RegisterId::ARM_ND1, ARM::D1},
279       {codeview::RegisterId::ARM_ND2, ARM::D2},
280       {codeview::RegisterId::ARM_ND3, ARM::D3},
281       {codeview::RegisterId::ARM_ND4, ARM::D4},
282       {codeview::RegisterId::ARM_ND5, ARM::D5},
283       {codeview::RegisterId::ARM_ND6, ARM::D6},
284       {codeview::RegisterId::ARM_ND7, ARM::D7},
285       {codeview::RegisterId::ARM_ND8, ARM::D8},
286       {codeview::RegisterId::ARM_ND9, ARM::D9},
287       {codeview::RegisterId::ARM_ND10, ARM::D10},
288       {codeview::RegisterId::ARM_ND11, ARM::D11},
289       {codeview::RegisterId::ARM_ND12, ARM::D12},
290       {codeview::RegisterId::ARM_ND13, ARM::D13},
291       {codeview::RegisterId::ARM_ND14, ARM::D14},
292       {codeview::RegisterId::ARM_ND15, ARM::D15},
293       {codeview::RegisterId::ARM_ND16, ARM::D16},
294       {codeview::RegisterId::ARM_ND17, ARM::D17},
295       {codeview::RegisterId::ARM_ND18, ARM::D18},
296       {codeview::RegisterId::ARM_ND19, ARM::D19},
297       {codeview::RegisterId::ARM_ND20, ARM::D20},
298       {codeview::RegisterId::ARM_ND21, ARM::D21},
299       {codeview::RegisterId::ARM_ND22, ARM::D22},
300       {codeview::RegisterId::ARM_ND23, ARM::D23},
301       {codeview::RegisterId::ARM_ND24, ARM::D24},
302       {codeview::RegisterId::ARM_ND25, ARM::D25},
303       {codeview::RegisterId::ARM_ND26, ARM::D26},
304       {codeview::RegisterId::ARM_ND27, ARM::D27},
305       {codeview::RegisterId::ARM_ND28, ARM::D28},
306       {codeview::RegisterId::ARM_ND29, ARM::D29},
307       {codeview::RegisterId::ARM_ND30, ARM::D30},
308       {codeview::RegisterId::ARM_ND31, ARM::D31},
309       {codeview::RegisterId::ARM_NQ0, ARM::Q0},
310       {codeview::RegisterId::ARM_NQ1, ARM::Q1},
311       {codeview::RegisterId::ARM_NQ2, ARM::Q2},
312       {codeview::RegisterId::ARM_NQ3, ARM::Q3},
313       {codeview::RegisterId::ARM_NQ4, ARM::Q4},
314       {codeview::RegisterId::ARM_NQ5, ARM::Q5},
315       {codeview::RegisterId::ARM_NQ6, ARM::Q6},
316       {codeview::RegisterId::ARM_NQ7, ARM::Q7},
317       {codeview::RegisterId::ARM_NQ8, ARM::Q8},
318       {codeview::RegisterId::ARM_NQ9, ARM::Q9},
319       {codeview::RegisterId::ARM_NQ10, ARM::Q10},
320       {codeview::RegisterId::ARM_NQ11, ARM::Q11},
321       {codeview::RegisterId::ARM_NQ12, ARM::Q12},
322       {codeview::RegisterId::ARM_NQ13, ARM::Q13},
323       {codeview::RegisterId::ARM_NQ14, ARM::Q14},
324       {codeview::RegisterId::ARM_NQ15, ARM::Q15},
325   };
326   for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
327     MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
328 }
329 
330 static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
331   MCRegisterInfo *X = new MCRegisterInfo();
332   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
333   ARM_MC::initLLVMToCVRegMapping(X);
334   return X;
335 }
336 
337 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI,
338                                      const Triple &TheTriple,
339                                      const MCTargetOptions &Options) {
340   MCAsmInfo *MAI;
341   if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
342     MAI = new ARMMCAsmInfoDarwin(TheTriple);
343   else if (TheTriple.isWindowsMSVCEnvironment())
344     MAI = new ARMCOFFMCAsmInfoMicrosoft();
345   else if (TheTriple.isOSWindows())
346     MAI = new ARMCOFFMCAsmInfoGNU();
347   else
348     MAI = new ARMELFMCAsmInfo(TheTriple);
349 
350   unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
351   MAI->addInitialFrameState(MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0));
352 
353   return MAI;
354 }
355 
356 static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
357                                      std::unique_ptr<MCAsmBackend> &&MAB,
358                                      std::unique_ptr<MCObjectWriter> &&OW,
359                                      std::unique_ptr<MCCodeEmitter> &&Emitter,
360                                      bool RelaxAll) {
361   return createARMELFStreamer(
362       Ctx, std::move(MAB), std::move(OW), std::move(Emitter), false,
363       (T.getArch() == Triple::thumb || T.getArch() == Triple::thumbeb),
364       T.isAndroid());
365 }
366 
367 static MCStreamer *
368 createARMMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&MAB,
369                        std::unique_ptr<MCObjectWriter> &&OW,
370                        std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
371                        bool DWARFMustBeAtTheEnd) {
372   return createMachOStreamer(Ctx, std::move(MAB), std::move(OW),
373                              std::move(Emitter), false, DWARFMustBeAtTheEnd);
374 }
375 
376 static MCInstPrinter *createARMMCInstPrinter(const Triple &T,
377                                              unsigned SyntaxVariant,
378                                              const MCAsmInfo &MAI,
379                                              const MCInstrInfo &MII,
380                                              const MCRegisterInfo &MRI) {
381   if (SyntaxVariant == 0)
382     return new ARMInstPrinter(MAI, MII, MRI);
383   return nullptr;
384 }
385 
386 static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT,
387                                                    MCContext &Ctx) {
388   if (TT.isOSBinFormatMachO())
389     return createARMMachORelocationInfo(Ctx);
390   // Default to the stock relocation info.
391   return llvm::createMCRelocationInfo(TT, Ctx);
392 }
393 
394 namespace {
395 
396 class ARMMCInstrAnalysis : public MCInstrAnalysis {
397 public:
398   ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
399 
400   bool isUnconditionalBranch(const MCInst &Inst) const override {
401     // BCCs with the "always" predicate are unconditional branches.
402     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
403       return true;
404     return MCInstrAnalysis::isUnconditionalBranch(Inst);
405   }
406 
407   bool isConditionalBranch(const MCInst &Inst) const override {
408     // BCCs with the "always" predicate are unconditional branches.
409     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
410       return false;
411     return MCInstrAnalysis::isConditionalBranch(Inst);
412   }
413 
414   bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
415                       uint64_t Size, uint64_t &Target) const override {
416     // We only handle PCRel branches for now.
417     if (Inst.getNumOperands() == 0 ||
418         Info->get(Inst.getOpcode()).OpInfo[0].OperandType !=
419             MCOI::OPERAND_PCREL)
420       return false;
421 
422     int64_t Imm = Inst.getOperand(0).getImm();
423     Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
424     return true;
425   }
426 };
427 
428 class ThumbMCInstrAnalysis : public ARMMCInstrAnalysis {
429 public:
430   ThumbMCInstrAnalysis(const MCInstrInfo *Info) : ARMMCInstrAnalysis(Info) {}
431 
432   bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
433                       uint64_t &Target) const override {
434     unsigned OpId;
435     switch (Inst.getOpcode()) {
436     default:
437       OpId = 0;
438       if (Inst.getNumOperands() == 0)
439         return false;
440       break;
441     case ARM::MVE_WLSTP_8:
442     case ARM::MVE_WLSTP_16:
443     case ARM::MVE_WLSTP_32:
444     case ARM::MVE_WLSTP_64:
445     case ARM::t2WLS:
446     case ARM::MVE_LETP:
447     case ARM::t2LEUpdate:
448       OpId = 2;
449       break;
450     case ARM::t2LE:
451       OpId = 1;
452       break;
453     }
454 
455     // We only handle PCRel branches for now.
456     if (Info->get(Inst.getOpcode()).OpInfo[OpId].OperandType !=
457         MCOI::OPERAND_PCREL)
458       return false;
459 
460     // In Thumb mode the PC is always off by 4 bytes.
461     Target = Addr + Inst.getOperand(OpId).getImm() + 4;
462     return true;
463   }
464 };
465 
466 }
467 
468 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
469   return new ARMMCInstrAnalysis(Info);
470 }
471 
472 static MCInstrAnalysis *createThumbMCInstrAnalysis(const MCInstrInfo *Info) {
473   return new ThumbMCInstrAnalysis(Info);
474 }
475 
476 bool ARM::isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI) {
477   // Unfortunately we don't have ARMTargetInfo in the disassembler, so we have
478   // to rely on feature bits.
479   if (Coproc >= 8)
480     return false;
481   return STI.getFeatureBits()[ARM::FeatureCoprocCDE0 + Coproc];
482 }
483 
484 // Force static initialization.
485 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTargetMC() {
486   for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(),
487                     &getTheThumbLETarget(), &getTheThumbBETarget()}) {
488     // Register the MC asm info.
489     RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo);
490 
491     // Register the MC instruction info.
492     TargetRegistry::RegisterMCInstrInfo(*T, createARMMCInstrInfo);
493 
494     // Register the MC register info.
495     TargetRegistry::RegisterMCRegInfo(*T, createARMMCRegisterInfo);
496 
497     // Register the MC subtarget info.
498     TargetRegistry::RegisterMCSubtargetInfo(*T,
499                                             ARM_MC::createARMMCSubtargetInfo);
500 
501     TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);
502     TargetRegistry::RegisterCOFFStreamer(*T, createARMWinCOFFStreamer);
503     TargetRegistry::RegisterMachOStreamer(*T, createARMMachOStreamer);
504 
505     // Register the obj target streamer.
506     TargetRegistry::RegisterObjectTargetStreamer(*T,
507                                                  createARMObjectTargetStreamer);
508 
509     // Register the asm streamer.
510     TargetRegistry::RegisterAsmTargetStreamer(*T, createARMTargetAsmStreamer);
511 
512     // Register the null TargetStreamer.
513     TargetRegistry::RegisterNullTargetStreamer(*T, createARMNullTargetStreamer);
514 
515     // Register the MCInstPrinter.
516     TargetRegistry::RegisterMCInstPrinter(*T, createARMMCInstPrinter);
517 
518     // Register the MC relocation info.
519     TargetRegistry::RegisterMCRelocationInfo(*T, createARMMCRelocationInfo);
520   }
521 
522   // Register the MC instruction analyzer.
523   for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget()})
524     TargetRegistry::RegisterMCInstrAnalysis(*T, createARMMCInstrAnalysis);
525   for (Target *T : {&getTheThumbLETarget(), &getTheThumbBETarget()})
526     TargetRegistry::RegisterMCInstrAnalysis(*T, createThumbMCInstrAnalysis);
527 
528   for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()}) {
529     TargetRegistry::RegisterMCCodeEmitter(*T, createARMLEMCCodeEmitter);
530     TargetRegistry::RegisterMCAsmBackend(*T, createARMLEAsmBackend);
531   }
532   for (Target *T : {&getTheARMBETarget(), &getTheThumbBETarget()}) {
533     TargetRegistry::RegisterMCCodeEmitter(*T, createARMBEMCCodeEmitter);
534     TargetRegistry::RegisterMCAsmBackend(*T, createARMBEAsmBackend);
535   }
536 }
537