1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides ARM specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMBaseInfo.h"
15 #include "ARMMCAsmInfo.h"
16 #include "ARMMCTargetDesc.h"
17 #include "InstPrinter/ARMInstPrinter.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCELFStreamer.h"
21 #include "llvm/MC/MCInstrAnalysis.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/TargetRegistry.h"
27 
28 using namespace llvm;
29 
30 #define GET_REGINFO_MC_DESC
31 #include "ARMGenRegisterInfo.inc"
32 
33 static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
34                                   std::string &Info) {
35   if (STI.getFeatureBits() & llvm::ARM::HasV7Ops &&
36       (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
37       (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
38       // Checks for the deprecated CP15ISB encoding:
39       // mcr p15, #0, rX, c7, c5, #4
40       (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
41     if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
42       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
43         Info = "deprecated since v7, use 'isb'";
44         return true;
45       }
46 
47       // Checks for the deprecated CP15DSB encoding:
48       // mcr p15, #0, rX, c7, c10, #4
49       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
50         Info = "deprecated since v7, use 'dsb'";
51         return true;
52       }
53     }
54     // Checks for the deprecated CP15DMB encoding:
55     // mcr p15, #0, rX, c7, c10, #5
56     if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
57         (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
58       Info = "deprecated since v7, use 'dmb'";
59       return true;
60     }
61   }
62   return false;
63 }
64 
65 static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
66                                   std::string &Info) {
67   if (STI.getFeatureBits() & llvm::ARM::HasV8Ops &&
68       MI.getOperand(1).isImm() && MI.getOperand(1).getImm() != 8) {
69     Info = "applying IT instruction to more than one subsequent instruction is deprecated";
70     return true;
71   }
72 
73   return false;
74 }
75 
76 #define GET_INSTRINFO_MC_DESC
77 #include "ARMGenInstrInfo.inc"
78 
79 #define GET_SUBTARGETINFO_MC_DESC
80 #include "ARMGenSubtargetInfo.inc"
81 
82 
83 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
84   Triple triple(TT);
85 
86   // Set the boolean corresponding to the current target triple, or the default
87   // if one cannot be determined, to true.
88   unsigned Len = TT.size();
89   unsigned Idx = 0;
90 
91   // FIXME: Enhance Triple helper class to extract ARM version.
92   bool isThumb = triple.getArch() == Triple::thumb;
93   if (Len >= 5 && TT.substr(0, 4) == "armv")
94     Idx = 4;
95   else if (Len >= 7 && TT.substr(0, 6) == "thumbv")
96     Idx = 6;
97 
98   bool NoCPU = CPU == "generic" || CPU.empty();
99   std::string ARMArchFeature;
100   if (Idx) {
101     unsigned SubVer = TT[Idx];
102     if (SubVer == '8') {
103       if (NoCPU)
104         // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2, FeatureMP,
105         //      FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone, FeatureT2XtPk, FeatureCrypto, FeatureCRC
106         ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,+trustzone,+t2xtpk,+crypto,+crc";
107       else
108         // Use CPU to figure out the exact features
109         ARMArchFeature = "+v8";
110     } else if (SubVer == '7') {
111       if (Len >= Idx+2 && TT[Idx+1] == 'm') {
112         isThumb = true;
113         if (NoCPU)
114           // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
115           ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
116         else
117           // Use CPU to figure out the exact features.
118           ARMArchFeature = "+v7";
119       } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
120         if (NoCPU)
121           // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
122           //       FeatureT2XtPk, FeatureMClass
123           ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
124         else
125           // Use CPU to figure out the exact features.
126           ARMArchFeature = "+v7";
127       } else if (Len >= Idx+2 && TT[Idx+1] == 's') {
128         if (NoCPU)
129           // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
130           //      Swift
131           ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
132         else
133           // Use CPU to figure out the exact features.
134           ARMArchFeature = "+v7";
135       } else {
136         // v7 CPUs have lots of different feature sets. If no CPU is specified,
137         // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
138         // the "minimum" feature set and use CPU string to figure out the exact
139         // features.
140         if (NoCPU)
141           // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
142           ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
143         else
144           // Use CPU to figure out the exact features.
145           ARMArchFeature = "+v7";
146       }
147     } else if (SubVer == '6') {
148       if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
149         ARMArchFeature = "+v6t2";
150       else if (Len >= Idx+2 && TT[Idx+1] == 'm') {
151         isThumb = true;
152         if (NoCPU)
153           // v6m: FeatureNoARM, FeatureMClass
154           ARMArchFeature = "+v6m,+noarm,+mclass";
155         else
156           ARMArchFeature = "+v6";
157       } else
158         ARMArchFeature = "+v6";
159     } else if (SubVer == '5') {
160       if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
161         ARMArchFeature = "+v5te";
162       else
163         ARMArchFeature = "+v5t";
164     } else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
165       ARMArchFeature = "+v4t";
166   }
167 
168   if (isThumb) {
169     if (ARMArchFeature.empty())
170       ARMArchFeature = "+thumb-mode";
171     else
172       ARMArchFeature += ",+thumb-mode";
173   }
174 
175   if (triple.isOSNaCl()) {
176     if (ARMArchFeature.empty())
177       ARMArchFeature = "+nacl-trap";
178     else
179       ARMArchFeature += ",+nacl-trap";
180   }
181 
182   return ARMArchFeature;
183 }
184 
185 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
186                                                   StringRef FS) {
187   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
188   if (!FS.empty()) {
189     if (!ArchFS.empty())
190       ArchFS = ArchFS + "," + FS.str();
191     else
192       ArchFS = FS;
193   }
194 
195   MCSubtargetInfo *X = new MCSubtargetInfo();
196   InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
197   return X;
198 }
199 
200 static MCInstrInfo *createARMMCInstrInfo() {
201   MCInstrInfo *X = new MCInstrInfo();
202   InitARMMCInstrInfo(X);
203   return X;
204 }
205 
206 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
207   MCRegisterInfo *X = new MCRegisterInfo();
208   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
209   return X;
210 }
211 
212 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
213   Triple TheTriple(TT);
214 
215   MCAsmInfo *MAI;
216   if (TheTriple.isOSBinFormatMachO())
217     MAI = new ARMMCAsmInfoDarwin();
218   else
219     MAI = new ARMELFMCAsmInfo();
220 
221   unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
222   MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(0, Reg, 0));
223 
224   return MAI;
225 }
226 
227 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
228                                              CodeModel::Model CM,
229                                              CodeGenOpt::Level OL) {
230   MCCodeGenInfo *X = new MCCodeGenInfo();
231   if (RM == Reloc::Default) {
232     Triple TheTriple(TT);
233     // Default relocation model on Darwin is PIC, not DynamicNoPIC.
234     RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
235   }
236   X->InitMCCodeGenInfo(RM, CM, OL);
237   return X;
238 }
239 
240 // This is duplicated code. Refactor this.
241 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
242                                     MCContext &Ctx, MCAsmBackend &MAB,
243                                     raw_ostream &OS,
244                                     MCCodeEmitter *Emitter,
245                                     const MCSubtargetInfo &STI,
246                                     bool RelaxAll,
247                                     bool NoExecStack) {
248   Triple TheTriple(TT);
249 
250   if (TheTriple.isOSBinFormatMachO()) {
251     MCStreamer *S = createMachOStreamer(Ctx, MAB, OS, Emitter, false);
252     new ARMTargetStreamer(*S);
253     return S;
254   }
255 
256   if (TheTriple.isOSWindows()) {
257     llvm_unreachable("ARM does not support Windows COFF format");
258   }
259 
260   return createARMELFStreamer(Ctx, MAB, OS, Emitter, false, NoExecStack,
261                               TheTriple.getArch() == Triple::thumb);
262 }
263 
264 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
265                                              unsigned SyntaxVariant,
266                                              const MCAsmInfo &MAI,
267                                              const MCInstrInfo &MII,
268                                              const MCRegisterInfo &MRI,
269                                              const MCSubtargetInfo &STI) {
270   if (SyntaxVariant == 0)
271     return new ARMInstPrinter(MAI, MII, MRI, STI);
272   return 0;
273 }
274 
275 static MCRelocationInfo *createARMMCRelocationInfo(StringRef TT,
276                                                    MCContext &Ctx) {
277   Triple TheTriple(TT);
278   if (TheTriple.isOSBinFormatMachO())
279     return createARMMachORelocationInfo(Ctx);
280   // Default to the stock relocation info.
281   return llvm::createMCRelocationInfo(TT, Ctx);
282 }
283 
284 namespace {
285 
286 class ARMMCInstrAnalysis : public MCInstrAnalysis {
287 public:
288   ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
289 
290   virtual bool isUnconditionalBranch(const MCInst &Inst) const {
291     // BCCs with the "always" predicate are unconditional branches.
292     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
293       return true;
294     return MCInstrAnalysis::isUnconditionalBranch(Inst);
295   }
296 
297   virtual bool isConditionalBranch(const MCInst &Inst) const {
298     // BCCs with the "always" predicate are unconditional branches.
299     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
300       return false;
301     return MCInstrAnalysis::isConditionalBranch(Inst);
302   }
303 
304   bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
305                       uint64_t Size, uint64_t &Target) const {
306     // We only handle PCRel branches for now.
307     if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
308       return false;
309 
310     int64_t Imm = Inst.getOperand(0).getImm();
311     // FIXME: This is not right for thumb.
312     Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
313     return true;
314   }
315 };
316 
317 }
318 
319 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
320   return new ARMMCInstrAnalysis(Info);
321 }
322 
323 // Force static initialization.
324 extern "C" void LLVMInitializeARMTargetMC() {
325   // Register the MC asm info.
326   RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo);
327   RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
328 
329   // Register the MC codegen info.
330   TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo);
331   TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo);
332 
333   // Register the MC instruction info.
334   TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
335   TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
336 
337   // Register the MC register info.
338   TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
339   TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
340 
341   // Register the MC subtarget info.
342   TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
343                                           ARM_MC::createARMMCSubtargetInfo);
344   TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
345                                           ARM_MC::createARMMCSubtargetInfo);
346 
347   // Register the MC instruction analyzer.
348   TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget,
349                                           createARMMCInstrAnalysis);
350   TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget,
351                                           createARMMCInstrAnalysis);
352 
353   // Register the MC Code Emitter
354   TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
355   TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
356 
357   // Register the asm backend.
358   TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend);
359   TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend);
360 
361   // Register the object streamer.
362   TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer);
363   TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer);
364 
365   // Register the asm streamer.
366   TargetRegistry::RegisterAsmStreamer(TheARMTarget, createMCAsmStreamer);
367   TargetRegistry::RegisterAsmStreamer(TheThumbTarget, createMCAsmStreamer);
368 
369   // Register the MCInstPrinter.
370   TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
371   TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
372 
373   // Register the MC relocation info.
374   TargetRegistry::RegisterMCRelocationInfo(TheARMTarget,
375                                            createARMMCRelocationInfo);
376   TargetRegistry::RegisterMCRelocationInfo(TheThumbTarget,
377                                            createARMMCRelocationInfo);
378 }
379