1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides ARM specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMBaseInfo.h"
15 #include "ARMMCAsmInfo.h"
16 #include "ARMMCTargetDesc.h"
17 #include "InstPrinter/ARMInstPrinter.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCELFStreamer.h"
21 #include "llvm/MC/MCInstrAnalysis.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/TargetRegistry.h"
27 
28 using namespace llvm;
29 
30 #define GET_REGINFO_MC_DESC
31 #include "ARMGenRegisterInfo.inc"
32 
33 static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
34                                   std::string &Info) {
35   if (STI.getFeatureBits() & llvm::ARM::HasV7Ops &&
36       (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
37       (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
38       // Checks for the deprecated CP15ISB encoding:
39       // mcr p15, #0, rX, c7, c5, #4
40       (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
41     if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
42       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
43         Info = "deprecated since v7, use 'isb'";
44         return true;
45       }
46 
47       // Checks for the deprecated CP15DSB encoding:
48       // mcr p15, #0, rX, c7, c10, #4
49       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
50         Info = "deprecated since v7, use 'dsb'";
51         return true;
52       }
53     }
54     // Checks for the deprecated CP15DMB encoding:
55     // mcr p15, #0, rX, c7, c10, #5
56     if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
57         (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
58       Info = "deprecated since v7, use 'dmb'";
59       return true;
60     }
61   }
62   return false;
63 }
64 
65 static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
66                                   std::string &Info) {
67   if (STI.getFeatureBits() & llvm::ARM::HasV8Ops &&
68       MI.getOperand(1).isImm() && MI.getOperand(1).getImm() != 8) {
69     Info = "applying IT instruction to more than one subsequent instruction is deprecated";
70     return true;
71   }
72 
73   return false;
74 }
75 
76 #define GET_INSTRINFO_MC_DESC
77 #include "ARMGenInstrInfo.inc"
78 
79 #define GET_SUBTARGETINFO_MC_DESC
80 #include "ARMGenSubtargetInfo.inc"
81 
82 
83 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
84   Triple triple(TT);
85 
86   // Set the boolean corresponding to the current target triple, or the default
87   // if one cannot be determined, to true.
88   unsigned Len = TT.size();
89   unsigned Idx = 0;
90 
91   // FIXME: Enhance Triple helper class to extract ARM version.
92   bool isThumb = false;
93   if (Len >= 5 && TT.substr(0, 4) == "armv")
94     Idx = 4;
95   else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
96     isThumb = true;
97     if (Len >= 7 && TT[5] == 'v')
98       Idx = 6;
99   }
100 
101   bool NoCPU = CPU == "generic" || CPU.empty();
102   std::string ARMArchFeature;
103   if (Idx) {
104     unsigned SubVer = TT[Idx];
105     if (SubVer == '8') {
106       // FIXME: Parse v8 features
107       ARMArchFeature = "+v8,+db";
108     } else if (SubVer == '7') {
109       if (Len >= Idx+2 && TT[Idx+1] == 'm') {
110         isThumb = true;
111         if (NoCPU)
112           // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
113           ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
114         else
115           // Use CPU to figure out the exact features.
116           ARMArchFeature = "+v7";
117       } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
118         if (NoCPU)
119           // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
120           //       FeatureT2XtPk, FeatureMClass
121           ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
122         else
123           // Use CPU to figure out the exact features.
124           ARMArchFeature = "+v7";
125       } else if (Len >= Idx+2 && TT[Idx+1] == 's') {
126         if (NoCPU)
127           // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
128           //      Swift
129           ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+t2xtpk";
130         else
131           // Use CPU to figure out the exact features.
132           ARMArchFeature = "+v7";
133       } else {
134         // v7 CPUs have lots of different feature sets. If no CPU is specified,
135         // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
136         // the "minimum" feature set and use CPU string to figure out the exact
137         // features.
138         if (NoCPU)
139           // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
140           ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
141         else
142           // Use CPU to figure out the exact features.
143           ARMArchFeature = "+v7";
144       }
145     } else if (SubVer == '6') {
146       if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
147         ARMArchFeature = "+v6t2";
148       else if (Len >= Idx+2 && TT[Idx+1] == 'm') {
149         isThumb = true;
150         if (NoCPU)
151           // v6m: FeatureNoARM, FeatureMClass
152           ARMArchFeature = "+v6m,+noarm,+mclass";
153         else
154           ARMArchFeature = "+v6";
155       } else
156         ARMArchFeature = "+v6";
157     } else if (SubVer == '5') {
158       if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
159         ARMArchFeature = "+v5te";
160       else
161         ARMArchFeature = "+v5t";
162     } else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
163       ARMArchFeature = "+v4t";
164   }
165 
166   if (isThumb) {
167     if (ARMArchFeature.empty())
168       ARMArchFeature = "+thumb-mode";
169     else
170       ARMArchFeature += ",+thumb-mode";
171   }
172 
173   if (triple.isOSNaCl()) {
174     if (ARMArchFeature.empty())
175       ARMArchFeature = "+nacl-trap";
176     else
177       ARMArchFeature += ",+nacl-trap";
178   }
179 
180   return ARMArchFeature;
181 }
182 
183 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
184                                                   StringRef FS) {
185   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
186   if (!FS.empty()) {
187     if (!ArchFS.empty())
188       ArchFS = ArchFS + "," + FS.str();
189     else
190       ArchFS = FS;
191   }
192 
193   MCSubtargetInfo *X = new MCSubtargetInfo();
194   InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
195   return X;
196 }
197 
198 static MCInstrInfo *createARMMCInstrInfo() {
199   MCInstrInfo *X = new MCInstrInfo();
200   InitARMMCInstrInfo(X);
201   return X;
202 }
203 
204 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
205   MCRegisterInfo *X = new MCRegisterInfo();
206   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
207   return X;
208 }
209 
210 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
211   Triple TheTriple(TT);
212 
213   if (TheTriple.isOSDarwin())
214     return new ARMMCAsmInfoDarwin();
215 
216   return new ARMELFMCAsmInfo();
217 }
218 
219 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
220                                              CodeModel::Model CM,
221                                              CodeGenOpt::Level OL) {
222   MCCodeGenInfo *X = new MCCodeGenInfo();
223   if (RM == Reloc::Default) {
224     Triple TheTriple(TT);
225     // Default relocation model on Darwin is PIC, not DynamicNoPIC.
226     RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
227   }
228   X->InitMCCodeGenInfo(RM, CM, OL);
229   return X;
230 }
231 
232 // This is duplicated code. Refactor this.
233 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
234                                     MCContext &Ctx, MCAsmBackend &MAB,
235                                     raw_ostream &OS,
236                                     MCCodeEmitter *Emitter,
237                                     bool RelaxAll,
238                                     bool NoExecStack) {
239   Triple TheTriple(TT);
240 
241   if (TheTriple.isOSDarwin())
242     return createMachOStreamer(Ctx, MAB, OS, Emitter, false);
243 
244   if (TheTriple.isOSWindows()) {
245     llvm_unreachable("ARM does not support Windows COFF format");
246   }
247 
248   return createARMELFStreamer(Ctx, MAB, OS, Emitter, false, NoExecStack,
249                               TheTriple.getArch() == Triple::thumb);
250 }
251 
252 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
253                                              unsigned SyntaxVariant,
254                                              const MCAsmInfo &MAI,
255                                              const MCInstrInfo &MII,
256                                              const MCRegisterInfo &MRI,
257                                              const MCSubtargetInfo &STI) {
258   if (SyntaxVariant == 0)
259     return new ARMInstPrinter(MAI, MII, MRI, STI);
260   return 0;
261 }
262 
263 static MCRelocationInfo *createARMMCRelocationInfo(StringRef TT,
264                                                    MCContext &Ctx) {
265   Triple TheTriple(TT);
266   if (TheTriple.isEnvironmentMachO())
267     return createARMMachORelocationInfo(Ctx);
268   // Default to the stock relocation info.
269   return llvm::createMCRelocationInfo(TT, Ctx);
270 }
271 
272 namespace {
273 
274 class ARMMCInstrAnalysis : public MCInstrAnalysis {
275 public:
276   ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
277 
278   virtual bool isUnconditionalBranch(const MCInst &Inst) const {
279     // BCCs with the "always" predicate are unconditional branches.
280     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
281       return true;
282     return MCInstrAnalysis::isUnconditionalBranch(Inst);
283   }
284 
285   virtual bool isConditionalBranch(const MCInst &Inst) const {
286     // BCCs with the "always" predicate are unconditional branches.
287     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
288       return false;
289     return MCInstrAnalysis::isConditionalBranch(Inst);
290   }
291 
292   bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
293                       uint64_t Size, uint64_t &Target) const {
294     // We only handle PCRel branches for now.
295     if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
296       return false;
297 
298     int64_t Imm = Inst.getOperand(0).getImm();
299     // FIXME: This is not right for thumb.
300     Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
301     return true;
302   }
303 };
304 
305 }
306 
307 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
308   return new ARMMCInstrAnalysis(Info);
309 }
310 
311 // Force static initialization.
312 extern "C" void LLVMInitializeARMTargetMC() {
313   // Register the MC asm info.
314   RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo);
315   RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
316 
317   // Register the MC codegen info.
318   TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo);
319   TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo);
320 
321   // Register the MC instruction info.
322   TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
323   TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
324 
325   // Register the MC register info.
326   TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
327   TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
328 
329   // Register the MC subtarget info.
330   TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
331                                           ARM_MC::createARMMCSubtargetInfo);
332   TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
333                                           ARM_MC::createARMMCSubtargetInfo);
334 
335   // Register the MC instruction analyzer.
336   TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget,
337                                           createARMMCInstrAnalysis);
338   TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget,
339                                           createARMMCInstrAnalysis);
340 
341   // Register the MC Code Emitter
342   TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
343   TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
344 
345   // Register the asm backend.
346   TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend);
347   TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend);
348 
349   // Register the object streamer.
350   TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer);
351   TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer);
352 
353   // Register the asm streamer.
354   TargetRegistry::RegisterAsmStreamer(TheARMTarget, createMCAsmStreamer);
355   TargetRegistry::RegisterAsmStreamer(TheThumbTarget, createMCAsmStreamer);
356 
357   // Register the MCInstPrinter.
358   TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
359   TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
360 
361   // Register the MC relocation info.
362   TargetRegistry::RegisterMCRelocationInfo(TheARMTarget,
363                                            createARMMCRelocationInfo);
364   TargetRegistry::RegisterMCRelocationInfo(TheThumbTarget,
365                                            createARMMCRelocationInfo);
366 }
367