1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides ARM specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMBaseInfo.h"
15 #include "ARMMCAsmInfo.h"
16 #include "ARMMCTargetDesc.h"
17 #include "InstPrinter/ARMInstPrinter.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCELFStreamer.h"
21 #include "llvm/MC/MCInstrAnalysis.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/TargetRegistry.h"
28 
29 using namespace llvm;
30 
31 #define GET_REGINFO_MC_DESC
32 #include "ARMGenRegisterInfo.inc"
33 
34 static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
35                                   std::string &Info) {
36   if (STI.getFeatureBits() & llvm::ARM::HasV7Ops &&
37       (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
38       (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
39       // Checks for the deprecated CP15ISB encoding:
40       // mcr p15, #0, rX, c7, c5, #4
41       (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
42     if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
43       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
44         Info = "deprecated since v7, use 'isb'";
45         return true;
46       }
47 
48       // Checks for the deprecated CP15DSB encoding:
49       // mcr p15, #0, rX, c7, c10, #4
50       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
51         Info = "deprecated since v7, use 'dsb'";
52         return true;
53       }
54     }
55     // Checks for the deprecated CP15DMB encoding:
56     // mcr p15, #0, rX, c7, c10, #5
57     if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
58         (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
59       Info = "deprecated since v7, use 'dmb'";
60       return true;
61     }
62   }
63   return false;
64 }
65 
66 static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
67                                   std::string &Info) {
68   if (STI.getFeatureBits() & llvm::ARM::HasV8Ops &&
69       MI.getOperand(1).isImm() && MI.getOperand(1).getImm() != 8) {
70     Info = "applying IT instruction to more than one subsequent instruction is deprecated";
71     return true;
72   }
73 
74   return false;
75 }
76 
77 #define GET_INSTRINFO_MC_DESC
78 #include "ARMGenInstrInfo.inc"
79 
80 #define GET_SUBTARGETINFO_MC_DESC
81 #include "ARMGenSubtargetInfo.inc"
82 
83 
84 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
85   Triple triple(TT);
86 
87   bool isThumb = triple.getArch() == Triple::thumb ||
88                  triple.getArch() == Triple::thumbeb;
89 
90   bool NoCPU = CPU == "generic" || CPU.empty();
91   std::string ARMArchFeature;
92   switch (triple.getSubArch()) {
93   default:
94     llvm_unreachable("invalid sub-architecture for ARM");
95   case Triple::ARMSubArch_v8:
96     if (NoCPU)
97       // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
98       //      FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
99       //      FeatureT2XtPk, FeatureCrypto, FeatureCRC
100       ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
101                        "+trustzone,+t2xtpk,+crypto,+crc";
102     else
103       // Use CPU to figure out the exact features
104       ARMArchFeature = "+v8";
105     break;
106   case Triple::ARMSubArch_v7m:
107     isThumb = true;
108     if (NoCPU)
109       // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
110       ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
111     else
112       // Use CPU to figure out the exact features.
113       ARMArchFeature = "+v7";
114     break;
115   case Triple::ARMSubArch_v7em:
116     if (NoCPU)
117       // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
118       //       FeatureT2XtPk, FeatureMClass
119       ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
120     else
121       // Use CPU to figure out the exact features.
122       ARMArchFeature = "+v7";
123     break;
124   case Triple::ARMSubArch_v7s:
125     if (NoCPU)
126       // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
127       //      Swift
128       ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
129     else
130       // Use CPU to figure out the exact features.
131       ARMArchFeature = "+v7";
132     break;
133   case Triple::ARMSubArch_v7:
134     // v7 CPUs have lots of different feature sets. If no CPU is specified,
135     // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
136     // the "minimum" feature set and use CPU string to figure out the exact
137     // features.
138     if (NoCPU)
139       // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
140       ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
141     else
142       // Use CPU to figure out the exact features.
143       ARMArchFeature = "+v7";
144     break;
145   case Triple::ARMSubArch_v6t2:
146     ARMArchFeature = "+v6t2";
147     break;
148   case Triple::ARMSubArch_v6m:
149     isThumb = true;
150     if (NoCPU)
151       // v6m: FeatureNoARM, FeatureMClass
152       ARMArchFeature = "+v6m,+noarm,+mclass";
153     else
154       ARMArchFeature = "+v6";
155     break;
156   case Triple::ARMSubArch_v6:
157     ARMArchFeature = "+v6";
158     break;
159   case Triple::ARMSubArch_v5te:
160     ARMArchFeature = "+v5te";
161     break;
162   case Triple::ARMSubArch_v5:
163     ARMArchFeature = "+v5t";
164     break;
165   case Triple::ARMSubArch_v4t:
166     ARMArchFeature = "+v4t";
167     break;
168   case Triple::NoSubArch:
169     break;
170   }
171 
172   if (isThumb) {
173     if (ARMArchFeature.empty())
174       ARMArchFeature = "+thumb-mode";
175     else
176       ARMArchFeature += ",+thumb-mode";
177   }
178 
179   if (triple.isOSNaCl()) {
180     if (ARMArchFeature.empty())
181       ARMArchFeature = "+nacl-trap";
182     else
183       ARMArchFeature += ",+nacl-trap";
184   }
185 
186   return ARMArchFeature;
187 }
188 
189 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
190                                                   StringRef FS) {
191   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
192   if (!FS.empty()) {
193     if (!ArchFS.empty())
194       ArchFS = ArchFS + "," + FS.str();
195     else
196       ArchFS = FS;
197   }
198 
199   MCSubtargetInfo *X = new MCSubtargetInfo();
200   InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
201   return X;
202 }
203 
204 static MCInstrInfo *createARMMCInstrInfo() {
205   MCInstrInfo *X = new MCInstrInfo();
206   InitARMMCInstrInfo(X);
207   return X;
208 }
209 
210 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
211   MCRegisterInfo *X = new MCRegisterInfo();
212   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
213   return X;
214 }
215 
216 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
217   Triple TheTriple(TT);
218 
219   MCAsmInfo *MAI;
220   if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
221     MAI = new ARMMCAsmInfoDarwin(TT);
222   else if (TheTriple.isWindowsItaniumEnvironment())
223     MAI = new ARMCOFFMCAsmInfoGNU();
224   else if (TheTriple.isWindowsMSVCEnvironment())
225     MAI = new ARMCOFFMCAsmInfoMicrosoft();
226   else
227     MAI = new ARMELFMCAsmInfo(TT);
228 
229   unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
230   MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
231 
232   return MAI;
233 }
234 
235 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
236                                              CodeModel::Model CM,
237                                              CodeGenOpt::Level OL) {
238   MCCodeGenInfo *X = new MCCodeGenInfo();
239   if (RM == Reloc::Default) {
240     Triple TheTriple(TT);
241     // Default relocation model on Darwin is PIC, not DynamicNoPIC.
242     RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
243   }
244   X->InitMCCodeGenInfo(RM, CM, OL);
245   return X;
246 }
247 
248 // This is duplicated code. Refactor this.
249 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
250                                     MCContext &Ctx, MCAsmBackend &MAB,
251                                     raw_ostream &OS, MCCodeEmitter *Emitter,
252                                     const MCSubtargetInfo &STI, bool RelaxAll) {
253   Triple TheTriple(TT);
254 
255   switch (TheTriple.getObjectFormat()) {
256   default: llvm_unreachable("unsupported object format");
257   case Triple::MachO: {
258     MCStreamer *S = createMachOStreamer(Ctx, MAB, OS, Emitter, false);
259     new ARMTargetStreamer(*S);
260     return S;
261   }
262   case Triple::COFF:
263     assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
264     return createARMWinCOFFStreamer(Ctx, MAB, *Emitter, OS);
265   case Triple::ELF:
266     return createARMELFStreamer(Ctx, MAB, OS, Emitter, false,
267                                 TheTriple.getArch() == Triple::thumb);
268   }
269 }
270 
271 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
272                                              unsigned SyntaxVariant,
273                                              const MCAsmInfo &MAI,
274                                              const MCInstrInfo &MII,
275                                              const MCRegisterInfo &MRI,
276                                              const MCSubtargetInfo &STI) {
277   if (SyntaxVariant == 0)
278     return new ARMInstPrinter(MAI, MII, MRI, STI);
279   return nullptr;
280 }
281 
282 static MCRelocationInfo *createARMMCRelocationInfo(StringRef TT,
283                                                    MCContext &Ctx) {
284   Triple TheTriple(TT);
285   if (TheTriple.isOSBinFormatMachO())
286     return createARMMachORelocationInfo(Ctx);
287   // Default to the stock relocation info.
288   return llvm::createMCRelocationInfo(TT, Ctx);
289 }
290 
291 namespace {
292 
293 class ARMMCInstrAnalysis : public MCInstrAnalysis {
294 public:
295   ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
296 
297   bool isUnconditionalBranch(const MCInst &Inst) const override {
298     // BCCs with the "always" predicate are unconditional branches.
299     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
300       return true;
301     return MCInstrAnalysis::isUnconditionalBranch(Inst);
302   }
303 
304   bool isConditionalBranch(const MCInst &Inst) const override {
305     // BCCs with the "always" predicate are unconditional branches.
306     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
307       return false;
308     return MCInstrAnalysis::isConditionalBranch(Inst);
309   }
310 
311   bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
312                       uint64_t Size, uint64_t &Target) const override {
313     // We only handle PCRel branches for now.
314     if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
315       return false;
316 
317     int64_t Imm = Inst.getOperand(0).getImm();
318     // FIXME: This is not right for thumb.
319     Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
320     return true;
321   }
322 };
323 
324 }
325 
326 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
327   return new ARMMCInstrAnalysis(Info);
328 }
329 
330 // Force static initialization.
331 extern "C" void LLVMInitializeARMTargetMC() {
332   // Register the MC asm info.
333   RegisterMCAsmInfoFn X(TheARMLETarget, createARMMCAsmInfo);
334   RegisterMCAsmInfoFn Y(TheARMBETarget, createARMMCAsmInfo);
335   RegisterMCAsmInfoFn A(TheThumbLETarget, createARMMCAsmInfo);
336   RegisterMCAsmInfoFn B(TheThumbBETarget, createARMMCAsmInfo);
337 
338   // Register the MC codegen info.
339   TargetRegistry::RegisterMCCodeGenInfo(TheARMLETarget, createARMMCCodeGenInfo);
340   TargetRegistry::RegisterMCCodeGenInfo(TheARMBETarget, createARMMCCodeGenInfo);
341   TargetRegistry::RegisterMCCodeGenInfo(TheThumbLETarget,
342                                         createARMMCCodeGenInfo);
343   TargetRegistry::RegisterMCCodeGenInfo(TheThumbBETarget,
344                                         createARMMCCodeGenInfo);
345 
346   // Register the MC instruction info.
347   TargetRegistry::RegisterMCInstrInfo(TheARMLETarget, createARMMCInstrInfo);
348   TargetRegistry::RegisterMCInstrInfo(TheARMBETarget, createARMMCInstrInfo);
349   TargetRegistry::RegisterMCInstrInfo(TheThumbLETarget, createARMMCInstrInfo);
350   TargetRegistry::RegisterMCInstrInfo(TheThumbBETarget, createARMMCInstrInfo);
351 
352   // Register the MC register info.
353   TargetRegistry::RegisterMCRegInfo(TheARMLETarget, createARMMCRegisterInfo);
354   TargetRegistry::RegisterMCRegInfo(TheARMBETarget, createARMMCRegisterInfo);
355   TargetRegistry::RegisterMCRegInfo(TheThumbLETarget, createARMMCRegisterInfo);
356   TargetRegistry::RegisterMCRegInfo(TheThumbBETarget, createARMMCRegisterInfo);
357 
358   // Register the MC subtarget info.
359   TargetRegistry::RegisterMCSubtargetInfo(TheARMLETarget,
360                                           ARM_MC::createARMMCSubtargetInfo);
361   TargetRegistry::RegisterMCSubtargetInfo(TheARMBETarget,
362                                           ARM_MC::createARMMCSubtargetInfo);
363   TargetRegistry::RegisterMCSubtargetInfo(TheThumbLETarget,
364                                           ARM_MC::createARMMCSubtargetInfo);
365   TargetRegistry::RegisterMCSubtargetInfo(TheThumbBETarget,
366                                           ARM_MC::createARMMCSubtargetInfo);
367 
368   // Register the MC instruction analyzer.
369   TargetRegistry::RegisterMCInstrAnalysis(TheARMLETarget,
370                                           createARMMCInstrAnalysis);
371   TargetRegistry::RegisterMCInstrAnalysis(TheARMBETarget,
372                                           createARMMCInstrAnalysis);
373   TargetRegistry::RegisterMCInstrAnalysis(TheThumbLETarget,
374                                           createARMMCInstrAnalysis);
375   TargetRegistry::RegisterMCInstrAnalysis(TheThumbBETarget,
376                                           createARMMCInstrAnalysis);
377 
378   // Register the MC Code Emitter
379   TargetRegistry::RegisterMCCodeEmitter(TheARMLETarget,
380                                         createARMLEMCCodeEmitter);
381   TargetRegistry::RegisterMCCodeEmitter(TheARMBETarget,
382                                         createARMBEMCCodeEmitter);
383   TargetRegistry::RegisterMCCodeEmitter(TheThumbLETarget,
384                                         createARMLEMCCodeEmitter);
385   TargetRegistry::RegisterMCCodeEmitter(TheThumbBETarget,
386                                         createARMBEMCCodeEmitter);
387 
388   // Register the asm backend.
389   TargetRegistry::RegisterMCAsmBackend(TheARMLETarget, createARMLEAsmBackend);
390   TargetRegistry::RegisterMCAsmBackend(TheARMBETarget, createARMBEAsmBackend);
391   TargetRegistry::RegisterMCAsmBackend(TheThumbLETarget,
392                                        createThumbLEAsmBackend);
393   TargetRegistry::RegisterMCAsmBackend(TheThumbBETarget,
394                                        createThumbBEAsmBackend);
395 
396   // Register the object streamer.
397   TargetRegistry::RegisterMCObjectStreamer(TheARMLETarget, createMCStreamer);
398   TargetRegistry::RegisterMCObjectStreamer(TheARMBETarget, createMCStreamer);
399   TargetRegistry::RegisterMCObjectStreamer(TheThumbLETarget, createMCStreamer);
400   TargetRegistry::RegisterMCObjectStreamer(TheThumbBETarget, createMCStreamer);
401 
402   // Register the asm streamer.
403   TargetRegistry::RegisterAsmStreamer(TheARMLETarget, createMCAsmStreamer);
404   TargetRegistry::RegisterAsmStreamer(TheARMBETarget, createMCAsmStreamer);
405   TargetRegistry::RegisterAsmStreamer(TheThumbLETarget, createMCAsmStreamer);
406   TargetRegistry::RegisterAsmStreamer(TheThumbBETarget, createMCAsmStreamer);
407 
408   // Register the null streamer.
409   TargetRegistry::RegisterNullStreamer(TheARMLETarget, createARMNullStreamer);
410   TargetRegistry::RegisterNullStreamer(TheARMBETarget, createARMNullStreamer);
411   TargetRegistry::RegisterNullStreamer(TheThumbLETarget, createARMNullStreamer);
412   TargetRegistry::RegisterNullStreamer(TheThumbBETarget, createARMNullStreamer);
413 
414   // Register the MCInstPrinter.
415   TargetRegistry::RegisterMCInstPrinter(TheARMLETarget, createARMMCInstPrinter);
416   TargetRegistry::RegisterMCInstPrinter(TheARMBETarget, createARMMCInstPrinter);
417   TargetRegistry::RegisterMCInstPrinter(TheThumbLETarget,
418                                         createARMMCInstPrinter);
419   TargetRegistry::RegisterMCInstPrinter(TheThumbBETarget,
420                                         createARMMCInstPrinter);
421 
422   // Register the MC relocation info.
423   TargetRegistry::RegisterMCRelocationInfo(TheARMLETarget,
424                                            createARMMCRelocationInfo);
425   TargetRegistry::RegisterMCRelocationInfo(TheARMBETarget,
426                                            createARMMCRelocationInfo);
427   TargetRegistry::RegisterMCRelocationInfo(TheThumbLETarget,
428                                            createARMMCRelocationInfo);
429   TargetRegistry::RegisterMCRelocationInfo(TheThumbBETarget,
430                                            createARMMCRelocationInfo);
431 }
432