1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides ARM specific target descriptions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "ARMMCTargetDesc.h" 15 #include "ARMBaseInfo.h" 16 #include "ARMMCAsmInfo.h" 17 #include "InstPrinter/ARMInstPrinter.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/MC/MCELFStreamer.h" 20 #include "llvm/MC/MCInstrAnalysis.h" 21 #include "llvm/MC/MCInstrInfo.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCStreamer.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/TargetParser.h" 27 #include "llvm/Support/TargetRegistry.h" 28 29 using namespace llvm; 30 31 #define GET_REGINFO_MC_DESC 32 #include "ARMGenRegisterInfo.inc" 33 34 static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, 35 std::string &Info) { 36 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && 37 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && 38 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && 39 // Checks for the deprecated CP15ISB encoding: 40 // mcr p15, #0, rX, c7, c5, #4 41 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { 42 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { 43 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) { 44 Info = "deprecated since v7, use 'isb'"; 45 return true; 46 } 47 48 // Checks for the deprecated CP15DSB encoding: 49 // mcr p15, #0, rX, c7, c10, #4 50 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) { 51 Info = "deprecated since v7, use 'dsb'"; 52 return true; 53 } 54 } 55 // Checks for the deprecated CP15DMB encoding: 56 // mcr p15, #0, rX, c7, c10, #5 57 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 && 58 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) { 59 Info = "deprecated since v7, use 'dmb'"; 60 return true; 61 } 62 } 63 return false; 64 } 65 66 static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, 67 std::string &Info) { 68 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() && 69 MI.getOperand(1).getImm() != 8) { 70 Info = "applying IT instruction to more than one subsequent instruction is " 71 "deprecated"; 72 return true; 73 } 74 75 return false; 76 } 77 78 static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, 79 std::string &Info) { 80 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] && 81 "cannot predicate thumb instructions"); 82 83 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments"); 84 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) { 85 assert(MI.getOperand(OI).isReg() && "expected register"); 86 if (MI.getOperand(OI).getReg() == ARM::SP || 87 MI.getOperand(OI).getReg() == ARM::PC) { 88 Info = "use of SP or PC in the list is deprecated"; 89 return true; 90 } 91 } 92 return false; 93 } 94 95 static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, 96 std::string &Info) { 97 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] && 98 "cannot predicate thumb instructions"); 99 100 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments"); 101 bool ListContainsPC = false, ListContainsLR = false; 102 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) { 103 assert(MI.getOperand(OI).isReg() && "expected register"); 104 switch (MI.getOperand(OI).getReg()) { 105 default: 106 break; 107 case ARM::LR: 108 ListContainsLR = true; 109 break; 110 case ARM::PC: 111 ListContainsPC = true; 112 break; 113 case ARM::SP: 114 Info = "use of SP in the list is deprecated"; 115 return true; 116 } 117 } 118 119 if (ListContainsPC && ListContainsLR) { 120 Info = "use of LR and PC simultaneously in the list is deprecated"; 121 return true; 122 } 123 124 return false; 125 } 126 127 #define GET_INSTRINFO_MC_DESC 128 #include "ARMGenInstrInfo.inc" 129 130 #define GET_SUBTARGETINFO_MC_DESC 131 #include "ARMGenSubtargetInfo.inc" 132 133 std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) { 134 std::string ARMArchFeature; 135 136 ARM::ArchKind ArchID = ARM::parseArch(TT.getArchName()); 137 if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic")) 138 ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(ArchID)).str(); 139 140 if (TT.isThumb()) { 141 if (ARMArchFeature.empty()) 142 ARMArchFeature = "+thumb-mode,+v4t"; 143 else 144 ARMArchFeature += ",+thumb-mode,+v4t"; 145 } 146 147 if (TT.isOSNaCl()) { 148 if (ARMArchFeature.empty()) 149 ARMArchFeature = "+nacl-trap"; 150 else 151 ARMArchFeature += ",+nacl-trap"; 152 } 153 154 return ARMArchFeature; 155 } 156 157 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT, 158 StringRef CPU, StringRef FS) { 159 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU); 160 if (!FS.empty()) { 161 if (!ArchFS.empty()) 162 ArchFS = (Twine(ArchFS) + "," + FS).str(); 163 else 164 ArchFS = FS; 165 } 166 167 return createARMMCSubtargetInfoImpl(TT, CPU, ArchFS); 168 } 169 170 static MCInstrInfo *createARMMCInstrInfo() { 171 MCInstrInfo *X = new MCInstrInfo(); 172 InitARMMCInstrInfo(X); 173 return X; 174 } 175 176 static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) { 177 MCRegisterInfo *X = new MCRegisterInfo(); 178 InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC); 179 return X; 180 } 181 182 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, 183 const Triple &TheTriple) { 184 MCAsmInfo *MAI; 185 if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO()) 186 MAI = new ARMMCAsmInfoDarwin(TheTriple); 187 else if (TheTriple.isWindowsMSVCEnvironment()) 188 MAI = new ARMCOFFMCAsmInfoMicrosoft(); 189 else if (TheTriple.isOSWindows()) 190 MAI = new ARMCOFFMCAsmInfoGNU(); 191 else 192 MAI = new ARMELFMCAsmInfo(TheTriple); 193 194 unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true); 195 MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0)); 196 197 return MAI; 198 } 199 200 static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx, 201 MCAsmBackend &MAB, raw_pwrite_stream &OS, 202 MCCodeEmitter *Emitter, bool RelaxAll) { 203 return createARMELFStreamer(Ctx, MAB, OS, Emitter, false, 204 (T.getArch() == Triple::thumb || 205 T.getArch() == Triple::thumbeb)); 206 } 207 208 static MCStreamer *createARMMachOStreamer(MCContext &Ctx, MCAsmBackend &MAB, 209 raw_pwrite_stream &OS, 210 MCCodeEmitter *Emitter, bool RelaxAll, 211 bool DWARFMustBeAtTheEnd) { 212 return createMachOStreamer(Ctx, MAB, OS, Emitter, false, DWARFMustBeAtTheEnd); 213 } 214 215 static MCInstPrinter *createARMMCInstPrinter(const Triple &T, 216 unsigned SyntaxVariant, 217 const MCAsmInfo &MAI, 218 const MCInstrInfo &MII, 219 const MCRegisterInfo &MRI) { 220 if (SyntaxVariant == 0) 221 return new ARMInstPrinter(MAI, MII, MRI); 222 return nullptr; 223 } 224 225 static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT, 226 MCContext &Ctx) { 227 if (TT.isOSBinFormatMachO()) 228 return createARMMachORelocationInfo(Ctx); 229 // Default to the stock relocation info. 230 return llvm::createMCRelocationInfo(TT, Ctx); 231 } 232 233 namespace { 234 235 class ARMMCInstrAnalysis : public MCInstrAnalysis { 236 public: 237 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {} 238 239 bool isUnconditionalBranch(const MCInst &Inst) const override { 240 // BCCs with the "always" predicate are unconditional branches. 241 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL) 242 return true; 243 return MCInstrAnalysis::isUnconditionalBranch(Inst); 244 } 245 246 bool isConditionalBranch(const MCInst &Inst) const override { 247 // BCCs with the "always" predicate are unconditional branches. 248 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL) 249 return false; 250 return MCInstrAnalysis::isConditionalBranch(Inst); 251 } 252 253 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, 254 uint64_t Size, uint64_t &Target) const override { 255 // We only handle PCRel branches for now. 256 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL) 257 return false; 258 259 int64_t Imm = Inst.getOperand(0).getImm(); 260 Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes. 261 return true; 262 } 263 }; 264 265 class ThumbMCInstrAnalysis : public ARMMCInstrAnalysis { 266 public: 267 ThumbMCInstrAnalysis(const MCInstrInfo *Info) : ARMMCInstrAnalysis(Info) {} 268 269 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, 270 uint64_t Size, uint64_t &Target) const override { 271 // We only handle PCRel branches for now. 272 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL) 273 return false; 274 275 int64_t Imm = Inst.getOperand(0).getImm(); 276 Target = Addr+Imm+4; // In Thumb mode the PC is always off by 4 bytes. 277 return true; 278 } 279 }; 280 281 } 282 283 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) { 284 return new ARMMCInstrAnalysis(Info); 285 } 286 287 static MCInstrAnalysis *createThumbMCInstrAnalysis(const MCInstrInfo *Info) { 288 return new ThumbMCInstrAnalysis(Info); 289 } 290 291 // Force static initialization. 292 extern "C" void LLVMInitializeARMTargetMC() { 293 for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(), 294 &getTheThumbLETarget(), &getTheThumbBETarget()}) { 295 // Register the MC asm info. 296 RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo); 297 298 // Register the MC instruction info. 299 TargetRegistry::RegisterMCInstrInfo(*T, createARMMCInstrInfo); 300 301 // Register the MC register info. 302 TargetRegistry::RegisterMCRegInfo(*T, createARMMCRegisterInfo); 303 304 // Register the MC subtarget info. 305 TargetRegistry::RegisterMCSubtargetInfo(*T, 306 ARM_MC::createARMMCSubtargetInfo); 307 308 TargetRegistry::RegisterELFStreamer(*T, createELFStreamer); 309 TargetRegistry::RegisterCOFFStreamer(*T, createARMWinCOFFStreamer); 310 TargetRegistry::RegisterMachOStreamer(*T, createARMMachOStreamer); 311 312 // Register the obj target streamer. 313 TargetRegistry::RegisterObjectTargetStreamer(*T, 314 createARMObjectTargetStreamer); 315 316 // Register the asm streamer. 317 TargetRegistry::RegisterAsmTargetStreamer(*T, createARMTargetAsmStreamer); 318 319 // Register the null TargetStreamer. 320 TargetRegistry::RegisterNullTargetStreamer(*T, createARMNullTargetStreamer); 321 322 // Register the MCInstPrinter. 323 TargetRegistry::RegisterMCInstPrinter(*T, createARMMCInstPrinter); 324 325 // Register the MC relocation info. 326 TargetRegistry::RegisterMCRelocationInfo(*T, createARMMCRelocationInfo); 327 } 328 329 // Register the MC instruction analyzer. 330 for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget()}) 331 TargetRegistry::RegisterMCInstrAnalysis(*T, createARMMCInstrAnalysis); 332 for (Target *T : {&getTheThumbLETarget(), &getTheThumbBETarget()}) 333 TargetRegistry::RegisterMCInstrAnalysis(*T, createThumbMCInstrAnalysis); 334 335 // Register the MC Code Emitter 336 for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()}) 337 TargetRegistry::RegisterMCCodeEmitter(*T, createARMLEMCCodeEmitter); 338 for (Target *T : {&getTheARMBETarget(), &getTheThumbBETarget()}) 339 TargetRegistry::RegisterMCCodeEmitter(*T, createARMBEMCCodeEmitter); 340 341 // Register the asm backend. 342 TargetRegistry::RegisterMCAsmBackend(getTheARMLETarget(), 343 createARMLEAsmBackend); 344 TargetRegistry::RegisterMCAsmBackend(getTheARMBETarget(), 345 createARMBEAsmBackend); 346 TargetRegistry::RegisterMCAsmBackend(getTheThumbLETarget(), 347 createThumbLEAsmBackend); 348 TargetRegistry::RegisterMCAsmBackend(getTheThumbBETarget(), 349 createThumbBEAsmBackend); 350 } 351