1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides ARM specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMMCTargetDesc.h"
14 #include "ARMAddressingModes.h"
15 #include "ARMBaseInfo.h"
16 #include "ARMInstPrinter.h"
17 #include "ARMMCAsmInfo.h"
18 #include "TargetInfo/ARMTargetInfo.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/DebugInfo/CodeView/CodeView.h"
21 #include "llvm/MC/MCAsmBackend.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCELFStreamer.h"
24 #include "llvm/MC/MCInstrAnalysis.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCObjectWriter.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCStreamer.h"
29 #include "llvm/MC/MCSubtargetInfo.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/TargetParser.h"
32 #include "llvm/Support/TargetRegistry.h"
33 
34 using namespace llvm;
35 
36 #define GET_REGINFO_MC_DESC
37 #include "ARMGenRegisterInfo.inc"
38 
39 static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
40                                   std::string &Info) {
41   if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
42       (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
43       (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
44       // Checks for the deprecated CP15ISB encoding:
45       // mcr p15, #0, rX, c7, c5, #4
46       (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
47     if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
48       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
49         Info = "deprecated since v7, use 'isb'";
50         return true;
51       }
52 
53       // Checks for the deprecated CP15DSB encoding:
54       // mcr p15, #0, rX, c7, c10, #4
55       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
56         Info = "deprecated since v7, use 'dsb'";
57         return true;
58       }
59     }
60     // Checks for the deprecated CP15DMB encoding:
61     // mcr p15, #0, rX, c7, c10, #5
62     if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
63         (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
64       Info = "deprecated since v7, use 'dmb'";
65       return true;
66     }
67   }
68   if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
69       ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) ||
70        (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) {
71     Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
72            "point instructions";
73     return true;
74   }
75   return false;
76 }
77 
78 static bool getMRCDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
79                                   std::string &Info) {
80   if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
81       ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) ||
82        (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) {
83     Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
84            "point instructions";
85     return true;
86   }
87   return false;
88 }
89 
90 static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
91                                  std::string &Info) {
92   if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() &&
93       MI.getOperand(1).getImm() != 8) {
94     Info = "applying IT instruction to more than one subsequent instruction is "
95            "deprecated";
96     return true;
97   }
98 
99   return false;
100 }
101 
102 static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
103                                        std::string &Info) {
104   assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
105          "cannot predicate thumb instructions");
106 
107   assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
108   for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
109     assert(MI.getOperand(OI).isReg() && "expected register");
110     if (MI.getOperand(OI).getReg() == ARM::PC) {
111       Info = "use of PC in the list is deprecated";
112       return true;
113     }
114   }
115   return false;
116 }
117 
118 static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
119                                       std::string &Info) {
120   assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
121          "cannot predicate thumb instructions");
122 
123   assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
124   bool ListContainsPC = false, ListContainsLR = false;
125   for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
126     assert(MI.getOperand(OI).isReg() && "expected register");
127     switch (MI.getOperand(OI).getReg()) {
128     default:
129       break;
130     case ARM::LR:
131       ListContainsLR = true;
132       break;
133     case ARM::PC:
134       ListContainsPC = true;
135       break;
136     }
137   }
138 
139   if (ListContainsPC && ListContainsLR) {
140     Info = "use of LR and PC simultaneously in the list is deprecated";
141     return true;
142   }
143 
144   return false;
145 }
146 
147 #define GET_INSTRINFO_MC_DESC
148 #include "ARMGenInstrInfo.inc"
149 
150 #define GET_SUBTARGETINFO_MC_DESC
151 #include "ARMGenSubtargetInfo.inc"
152 
153 std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
154   std::string ARMArchFeature;
155 
156   ARM::ArchKind ArchID = ARM::parseArch(TT.getArchName());
157   if (ArchID != ARM::ArchKind::INVALID &&  (CPU.empty() || CPU == "generic"))
158     ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(ArchID)).str();
159 
160   if (TT.isThumb()) {
161     if (!ARMArchFeature.empty())
162       ARMArchFeature += ",";
163     ARMArchFeature += "+thumb-mode,+v4t";
164   }
165 
166   if (TT.isOSNaCl()) {
167     if (!ARMArchFeature.empty())
168       ARMArchFeature += ",";
169     ARMArchFeature += "+nacl-trap";
170   }
171 
172   if (TT.isOSWindows()) {
173     if (!ARMArchFeature.empty())
174       ARMArchFeature += ",";
175     ARMArchFeature += "+noarm";
176   }
177 
178   return ARMArchFeature;
179 }
180 
181 bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo *MCII) {
182   const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
183   int PredOpIdx = Desc.findFirstPredOperandIdx();
184   return PredOpIdx != -1 && MI.getOperand(PredOpIdx).getImm() != ARMCC::AL;
185 }
186 
187 bool ARM_MC::isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII) {
188   const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
189   for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
190     const MCOperand &MO = MI.getOperand(I);
191     if (MO.isReg() && MO.getReg() == ARM::CPSR &&
192         Desc.OpInfo[I].isOptionalDef())
193       return true;
194   }
195   return false;
196 }
197 
198 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
199                                                   StringRef CPU, StringRef FS) {
200   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
201   if (!FS.empty()) {
202     if (!ArchFS.empty())
203       ArchFS = (Twine(ArchFS) + "," + FS).str();
204     else
205       ArchFS = std::string(FS);
206   }
207 
208   return createARMMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS);
209 }
210 
211 static MCInstrInfo *createARMMCInstrInfo() {
212   MCInstrInfo *X = new MCInstrInfo();
213   InitARMMCInstrInfo(X);
214   return X;
215 }
216 
217 void ARM_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
218   // Mapping from CodeView to MC register id.
219   static const struct {
220     codeview::RegisterId CVReg;
221     MCPhysReg Reg;
222   } RegMap[] = {
223       {codeview::RegisterId::ARM_R0, ARM::R0},
224       {codeview::RegisterId::ARM_R1, ARM::R1},
225       {codeview::RegisterId::ARM_R2, ARM::R2},
226       {codeview::RegisterId::ARM_R3, ARM::R3},
227       {codeview::RegisterId::ARM_R4, ARM::R4},
228       {codeview::RegisterId::ARM_R5, ARM::R5},
229       {codeview::RegisterId::ARM_R6, ARM::R6},
230       {codeview::RegisterId::ARM_R7, ARM::R7},
231       {codeview::RegisterId::ARM_R8, ARM::R8},
232       {codeview::RegisterId::ARM_R9, ARM::R9},
233       {codeview::RegisterId::ARM_R10, ARM::R10},
234       {codeview::RegisterId::ARM_R11, ARM::R11},
235       {codeview::RegisterId::ARM_R12, ARM::R12},
236       {codeview::RegisterId::ARM_SP, ARM::SP},
237       {codeview::RegisterId::ARM_LR, ARM::LR},
238       {codeview::RegisterId::ARM_PC, ARM::PC},
239       {codeview::RegisterId::ARM_CPSR, ARM::CPSR},
240       {codeview::RegisterId::ARM_FPSCR, ARM::FPSCR},
241       {codeview::RegisterId::ARM_FPEXC, ARM::FPEXC},
242       {codeview::RegisterId::ARM_FS0, ARM::S0},
243       {codeview::RegisterId::ARM_FS1, ARM::S1},
244       {codeview::RegisterId::ARM_FS2, ARM::S2},
245       {codeview::RegisterId::ARM_FS3, ARM::S3},
246       {codeview::RegisterId::ARM_FS4, ARM::S4},
247       {codeview::RegisterId::ARM_FS5, ARM::S5},
248       {codeview::RegisterId::ARM_FS6, ARM::S6},
249       {codeview::RegisterId::ARM_FS7, ARM::S7},
250       {codeview::RegisterId::ARM_FS8, ARM::S8},
251       {codeview::RegisterId::ARM_FS9, ARM::S9},
252       {codeview::RegisterId::ARM_FS10, ARM::S10},
253       {codeview::RegisterId::ARM_FS11, ARM::S11},
254       {codeview::RegisterId::ARM_FS12, ARM::S12},
255       {codeview::RegisterId::ARM_FS13, ARM::S13},
256       {codeview::RegisterId::ARM_FS14, ARM::S14},
257       {codeview::RegisterId::ARM_FS15, ARM::S15},
258       {codeview::RegisterId::ARM_FS16, ARM::S16},
259       {codeview::RegisterId::ARM_FS17, ARM::S17},
260       {codeview::RegisterId::ARM_FS18, ARM::S18},
261       {codeview::RegisterId::ARM_FS19, ARM::S19},
262       {codeview::RegisterId::ARM_FS20, ARM::S20},
263       {codeview::RegisterId::ARM_FS21, ARM::S21},
264       {codeview::RegisterId::ARM_FS22, ARM::S22},
265       {codeview::RegisterId::ARM_FS23, ARM::S23},
266       {codeview::RegisterId::ARM_FS24, ARM::S24},
267       {codeview::RegisterId::ARM_FS25, ARM::S25},
268       {codeview::RegisterId::ARM_FS26, ARM::S26},
269       {codeview::RegisterId::ARM_FS27, ARM::S27},
270       {codeview::RegisterId::ARM_FS28, ARM::S28},
271       {codeview::RegisterId::ARM_FS29, ARM::S29},
272       {codeview::RegisterId::ARM_FS30, ARM::S30},
273       {codeview::RegisterId::ARM_FS31, ARM::S31},
274       {codeview::RegisterId::ARM_ND0, ARM::D0},
275       {codeview::RegisterId::ARM_ND1, ARM::D1},
276       {codeview::RegisterId::ARM_ND2, ARM::D2},
277       {codeview::RegisterId::ARM_ND3, ARM::D3},
278       {codeview::RegisterId::ARM_ND4, ARM::D4},
279       {codeview::RegisterId::ARM_ND5, ARM::D5},
280       {codeview::RegisterId::ARM_ND6, ARM::D6},
281       {codeview::RegisterId::ARM_ND7, ARM::D7},
282       {codeview::RegisterId::ARM_ND8, ARM::D8},
283       {codeview::RegisterId::ARM_ND9, ARM::D9},
284       {codeview::RegisterId::ARM_ND10, ARM::D10},
285       {codeview::RegisterId::ARM_ND11, ARM::D11},
286       {codeview::RegisterId::ARM_ND12, ARM::D12},
287       {codeview::RegisterId::ARM_ND13, ARM::D13},
288       {codeview::RegisterId::ARM_ND14, ARM::D14},
289       {codeview::RegisterId::ARM_ND15, ARM::D15},
290       {codeview::RegisterId::ARM_ND16, ARM::D16},
291       {codeview::RegisterId::ARM_ND17, ARM::D17},
292       {codeview::RegisterId::ARM_ND18, ARM::D18},
293       {codeview::RegisterId::ARM_ND19, ARM::D19},
294       {codeview::RegisterId::ARM_ND20, ARM::D20},
295       {codeview::RegisterId::ARM_ND21, ARM::D21},
296       {codeview::RegisterId::ARM_ND22, ARM::D22},
297       {codeview::RegisterId::ARM_ND23, ARM::D23},
298       {codeview::RegisterId::ARM_ND24, ARM::D24},
299       {codeview::RegisterId::ARM_ND25, ARM::D25},
300       {codeview::RegisterId::ARM_ND26, ARM::D26},
301       {codeview::RegisterId::ARM_ND27, ARM::D27},
302       {codeview::RegisterId::ARM_ND28, ARM::D28},
303       {codeview::RegisterId::ARM_ND29, ARM::D29},
304       {codeview::RegisterId::ARM_ND30, ARM::D30},
305       {codeview::RegisterId::ARM_ND31, ARM::D31},
306       {codeview::RegisterId::ARM_NQ0, ARM::Q0},
307       {codeview::RegisterId::ARM_NQ1, ARM::Q1},
308       {codeview::RegisterId::ARM_NQ2, ARM::Q2},
309       {codeview::RegisterId::ARM_NQ3, ARM::Q3},
310       {codeview::RegisterId::ARM_NQ4, ARM::Q4},
311       {codeview::RegisterId::ARM_NQ5, ARM::Q5},
312       {codeview::RegisterId::ARM_NQ6, ARM::Q6},
313       {codeview::RegisterId::ARM_NQ7, ARM::Q7},
314       {codeview::RegisterId::ARM_NQ8, ARM::Q8},
315       {codeview::RegisterId::ARM_NQ9, ARM::Q9},
316       {codeview::RegisterId::ARM_NQ10, ARM::Q10},
317       {codeview::RegisterId::ARM_NQ11, ARM::Q11},
318       {codeview::RegisterId::ARM_NQ12, ARM::Q12},
319       {codeview::RegisterId::ARM_NQ13, ARM::Q13},
320       {codeview::RegisterId::ARM_NQ14, ARM::Q14},
321       {codeview::RegisterId::ARM_NQ15, ARM::Q15},
322   };
323   for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
324     MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
325 }
326 
327 static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
328   MCRegisterInfo *X = new MCRegisterInfo();
329   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
330   ARM_MC::initLLVMToCVRegMapping(X);
331   return X;
332 }
333 
334 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI,
335                                      const Triple &TheTriple,
336                                      const MCTargetOptions &Options) {
337   MCAsmInfo *MAI;
338   if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
339     MAI = new ARMMCAsmInfoDarwin(TheTriple);
340   else if (TheTriple.isWindowsMSVCEnvironment())
341     MAI = new ARMCOFFMCAsmInfoMicrosoft();
342   else if (TheTriple.isOSWindows())
343     MAI = new ARMCOFFMCAsmInfoGNU();
344   else
345     MAI = new ARMELFMCAsmInfo(TheTriple);
346 
347   unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
348   MAI->addInitialFrameState(MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0));
349 
350   return MAI;
351 }
352 
353 static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
354                                      std::unique_ptr<MCAsmBackend> &&MAB,
355                                      std::unique_ptr<MCObjectWriter> &&OW,
356                                      std::unique_ptr<MCCodeEmitter> &&Emitter,
357                                      bool RelaxAll) {
358   return createARMELFStreamer(
359       Ctx, std::move(MAB), std::move(OW), std::move(Emitter), false,
360       (T.getArch() == Triple::thumb || T.getArch() == Triple::thumbeb),
361       T.isAndroid());
362 }
363 
364 static MCStreamer *
365 createARMMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&MAB,
366                        std::unique_ptr<MCObjectWriter> &&OW,
367                        std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
368                        bool DWARFMustBeAtTheEnd) {
369   return createMachOStreamer(Ctx, std::move(MAB), std::move(OW),
370                              std::move(Emitter), false, DWARFMustBeAtTheEnd);
371 }
372 
373 static MCInstPrinter *createARMMCInstPrinter(const Triple &T,
374                                              unsigned SyntaxVariant,
375                                              const MCAsmInfo &MAI,
376                                              const MCInstrInfo &MII,
377                                              const MCRegisterInfo &MRI) {
378   if (SyntaxVariant == 0)
379     return new ARMInstPrinter(MAI, MII, MRI);
380   return nullptr;
381 }
382 
383 static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT,
384                                                    MCContext &Ctx) {
385   if (TT.isOSBinFormatMachO())
386     return createARMMachORelocationInfo(Ctx);
387   // Default to the stock relocation info.
388   return llvm::createMCRelocationInfo(TT, Ctx);
389 }
390 
391 namespace {
392 
393 class ARMMCInstrAnalysis : public MCInstrAnalysis {
394 public:
395   ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
396 
397   bool isUnconditionalBranch(const MCInst &Inst) const override {
398     // BCCs with the "always" predicate are unconditional branches.
399     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
400       return true;
401     return MCInstrAnalysis::isUnconditionalBranch(Inst);
402   }
403 
404   bool isConditionalBranch(const MCInst &Inst) const override {
405     // BCCs with the "always" predicate are unconditional branches.
406     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
407       return false;
408     return MCInstrAnalysis::isConditionalBranch(Inst);
409   }
410 
411   bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
412                       uint64_t Size, uint64_t &Target) const override {
413     // We only handle PCRel branches for now.
414     if (Inst.getNumOperands() == 0 ||
415         Info->get(Inst.getOpcode()).OpInfo[0].OperandType !=
416             MCOI::OPERAND_PCREL)
417       return false;
418 
419     int64_t Imm = Inst.getOperand(0).getImm();
420     Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
421     return true;
422   }
423 };
424 
425 class ThumbMCInstrAnalysis : public ARMMCInstrAnalysis {
426 public:
427   ThumbMCInstrAnalysis(const MCInstrInfo *Info) : ARMMCInstrAnalysis(Info) {}
428 
429   bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
430                       uint64_t &Target) const override {
431     unsigned OpId;
432     switch (Inst.getOpcode()) {
433     default:
434       OpId = 0;
435       if (Inst.getNumOperands() == 0)
436         return false;
437       break;
438     case ARM::MVE_WLSTP_8:
439     case ARM::MVE_WLSTP_16:
440     case ARM::MVE_WLSTP_32:
441     case ARM::MVE_WLSTP_64:
442     case ARM::t2WLS:
443     case ARM::MVE_LETP:
444     case ARM::t2LEUpdate:
445       OpId = 2;
446       break;
447     case ARM::t2LE:
448       OpId = 1;
449       break;
450     }
451 
452     // We only handle PCRel branches for now.
453     if (Info->get(Inst.getOpcode()).OpInfo[OpId].OperandType !=
454         MCOI::OPERAND_PCREL)
455       return false;
456 
457     // In Thumb mode the PC is always off by 4 bytes.
458     Target = Addr + Inst.getOperand(OpId).getImm() + 4;
459     return true;
460   }
461 };
462 
463 }
464 
465 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
466   return new ARMMCInstrAnalysis(Info);
467 }
468 
469 static MCInstrAnalysis *createThumbMCInstrAnalysis(const MCInstrInfo *Info) {
470   return new ThumbMCInstrAnalysis(Info);
471 }
472 
473 bool ARM::isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI) {
474   // Unfortunately we don't have ARMTargetInfo in the disassembler, so we have
475   // to rely on feature bits.
476   if (Coproc >= 8)
477     return false;
478   return STI.getFeatureBits()[ARM::FeatureCoprocCDE0 + Coproc];
479 }
480 
481 // Force static initialization.
482 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTargetMC() {
483   for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(),
484                     &getTheThumbLETarget(), &getTheThumbBETarget()}) {
485     // Register the MC asm info.
486     RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo);
487 
488     // Register the MC instruction info.
489     TargetRegistry::RegisterMCInstrInfo(*T, createARMMCInstrInfo);
490 
491     // Register the MC register info.
492     TargetRegistry::RegisterMCRegInfo(*T, createARMMCRegisterInfo);
493 
494     // Register the MC subtarget info.
495     TargetRegistry::RegisterMCSubtargetInfo(*T,
496                                             ARM_MC::createARMMCSubtargetInfo);
497 
498     TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);
499     TargetRegistry::RegisterCOFFStreamer(*T, createARMWinCOFFStreamer);
500     TargetRegistry::RegisterMachOStreamer(*T, createARMMachOStreamer);
501 
502     // Register the obj target streamer.
503     TargetRegistry::RegisterObjectTargetStreamer(*T,
504                                                  createARMObjectTargetStreamer);
505 
506     // Register the asm streamer.
507     TargetRegistry::RegisterAsmTargetStreamer(*T, createARMTargetAsmStreamer);
508 
509     // Register the null TargetStreamer.
510     TargetRegistry::RegisterNullTargetStreamer(*T, createARMNullTargetStreamer);
511 
512     // Register the MCInstPrinter.
513     TargetRegistry::RegisterMCInstPrinter(*T, createARMMCInstPrinter);
514 
515     // Register the MC relocation info.
516     TargetRegistry::RegisterMCRelocationInfo(*T, createARMMCRelocationInfo);
517   }
518 
519   // Register the MC instruction analyzer.
520   for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget()})
521     TargetRegistry::RegisterMCInstrAnalysis(*T, createARMMCInstrAnalysis);
522   for (Target *T : {&getTheThumbLETarget(), &getTheThumbBETarget()})
523     TargetRegistry::RegisterMCInstrAnalysis(*T, createThumbMCInstrAnalysis);
524 
525   for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()}) {
526     TargetRegistry::RegisterMCCodeEmitter(*T, createARMLEMCCodeEmitter);
527     TargetRegistry::RegisterMCAsmBackend(*T, createARMLEAsmBackend);
528   }
529   for (Target *T : {&getTheARMBETarget(), &getTheThumbBETarget()}) {
530     TargetRegistry::RegisterMCCodeEmitter(*T, createARMBEMCCodeEmitter);
531     TargetRegistry::RegisterMCAsmBackend(*T, createARMBEAsmBackend);
532   }
533 }
534