1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARMMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMFixupKinds.h"
18 #include "MCTargetDesc/ARMMCExpr.h"
19 #include "MCTargetDesc/ARMMCTargetDesc.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/ADT/APFloat.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/raw_ostream.h"
29 
30 using namespace llvm;
31 
32 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
33 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
34 
35 namespace {
36 class ARMMCCodeEmitter : public MCCodeEmitter {
37   ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
38   void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
39   const MCInstrInfo &MCII;
40   const MCSubtargetInfo &STI;
41 
42 public:
43   ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
44                    MCContext &ctx)
45     : MCII(mcii), STI(sti) {
46   }
47 
48   ~ARMMCCodeEmitter() {}
49 
50   bool isThumb() const {
51     // FIXME: Can tablegen auto-generate this?
52     return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
53   }
54   bool isThumb2() const {
55     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
56   }
57   bool isTargetDarwin() const {
58     Triple TT(STI.getTargetTriple());
59     Triple::OSType OS = TT.getOS();
60     return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS;
61   }
62 
63   unsigned getMachineSoImmOpValue(unsigned SoImm) const;
64 
65   // getBinaryCodeForInstr - TableGen'erated function for getting the
66   // binary encoding for an instruction.
67   uint64_t getBinaryCodeForInstr(const MCInst &MI,
68                                  SmallVectorImpl<MCFixup> &Fixups) const;
69 
70   /// getMachineOpValue - Return binary encoding of operand. If the machine
71   /// operand requires relocation, record the relocation and return zero.
72   unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
73                              SmallVectorImpl<MCFixup> &Fixups) const;
74 
75   /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
76   /// the specified operand. This is used for operands with :lower16: and
77   /// :upper16: prefixes.
78   uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
79                                SmallVectorImpl<MCFixup> &Fixups) const;
80 
81   bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
82                               unsigned &Reg, unsigned &Imm,
83                               SmallVectorImpl<MCFixup> &Fixups) const;
84 
85   /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
86   /// BL branch target.
87   uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
88                                    SmallVectorImpl<MCFixup> &Fixups) const;
89 
90   /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
91   /// BLX branch target.
92   uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
93                                     SmallVectorImpl<MCFixup> &Fixups) const;
94 
95   /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
96   uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
97                                    SmallVectorImpl<MCFixup> &Fixups) const;
98 
99   /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
100   uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
101                                     SmallVectorImpl<MCFixup> &Fixups) const;
102 
103   /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
104   uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
105                                    SmallVectorImpl<MCFixup> &Fixups) const;
106 
107   /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
108   /// branch target.
109   uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
110                                   SmallVectorImpl<MCFixup> &Fixups) const;
111 
112   /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
113   /// immediate Thumb2 direct branch target.
114   uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
115                                   SmallVectorImpl<MCFixup> &Fixups) const;
116 
117   /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
118   /// branch target.
119   uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
120                                      SmallVectorImpl<MCFixup> &Fixups) const;
121   uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
122                                      SmallVectorImpl<MCFixup> &Fixups) const;
123 
124   /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
125   /// ADR label target.
126   uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
127                               SmallVectorImpl<MCFixup> &Fixups) const;
128   uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
129                               SmallVectorImpl<MCFixup> &Fixups) const;
130   uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
131                               SmallVectorImpl<MCFixup> &Fixups) const;
132 
133 
134   /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
135   /// operand.
136   uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
137                                    SmallVectorImpl<MCFixup> &Fixups) const;
138 
139   /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
140   uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
141                                          SmallVectorImpl<MCFixup> &Fixups)const;
142 
143   /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
144   /// operand.
145   uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
146                                    SmallVectorImpl<MCFixup> &Fixups) const;
147 
148   /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
149   /// operand.
150   uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
151                                    SmallVectorImpl<MCFixup> &Fixups) const;
152 
153   /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
154   /// operand.
155   uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
156                               SmallVectorImpl<MCFixup> &Fixups) const;
157 
158 
159   /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
160   /// operand as needed by load/store instructions.
161   uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
162                                SmallVectorImpl<MCFixup> &Fixups) const;
163 
164   /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
165   uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
166                                SmallVectorImpl<MCFixup> &Fixups) const {
167     ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
168     switch (Mode) {
169     default: llvm_unreachable("Unknown addressing sub-mode!");
170     case ARM_AM::da: return 0;
171     case ARM_AM::ia: return 1;
172     case ARM_AM::db: return 2;
173     case ARM_AM::ib: return 3;
174     }
175   }
176   /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
177   ///
178   unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
179     switch (ShOpc) {
180     case ARM_AM::no_shift:
181     case ARM_AM::lsl: return 0;
182     case ARM_AM::lsr: return 1;
183     case ARM_AM::asr: return 2;
184     case ARM_AM::ror:
185     case ARM_AM::rrx: return 3;
186     }
187     llvm_unreachable("Invalid ShiftOpc!");
188   }
189 
190   /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
191   uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
192                                SmallVectorImpl<MCFixup> &Fixups) const;
193 
194   /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
195   uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
196                                      SmallVectorImpl<MCFixup> &Fixups) const;
197 
198   /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
199   uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
200                                 SmallVectorImpl<MCFixup> &Fixups) const;
201 
202   /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
203   uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
204                                      SmallVectorImpl<MCFixup> &Fixups) const;
205 
206   /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
207   uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
208                                SmallVectorImpl<MCFixup> &Fixups) const;
209 
210   /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
211   /// operand.
212   uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
213                                      SmallVectorImpl<MCFixup> &Fixups) const;
214 
215   /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
216   uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
217                                 SmallVectorImpl<MCFixup> &Fixups) const;
218 
219   /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
220   uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
221                                 SmallVectorImpl<MCFixup> &Fixups) const;
222 
223   /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
224   uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
225                                SmallVectorImpl<MCFixup> &Fixups) const;
226 
227   /// getCCOutOpValue - Return encoding of the 's' bit.
228   unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
229                            SmallVectorImpl<MCFixup> &Fixups) const {
230     // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
231     // '1' respectively.
232     return MI.getOperand(Op).getReg() == ARM::CPSR;
233   }
234 
235   /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
236   unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
237                            SmallVectorImpl<MCFixup> &Fixups) const {
238     unsigned SoImm = MI.getOperand(Op).getImm();
239     int SoImmVal = ARM_AM::getSOImmVal(SoImm);
240     assert(SoImmVal != -1 && "Not a valid so_imm value!");
241 
242     // Encode rotate_imm.
243     unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
244       << ARMII::SoRotImmShift;
245 
246     // Encode immed_8.
247     Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
248     return Binary;
249   }
250 
251   /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
252   unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
253                            SmallVectorImpl<MCFixup> &Fixups) const {
254     unsigned SoImm = MI.getOperand(Op).getImm();
255     unsigned Encoded =  ARM_AM::getT2SOImmVal(SoImm);
256     assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
257     return Encoded;
258   }
259 
260   unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
261     SmallVectorImpl<MCFixup> &Fixups) const;
262   unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
263     SmallVectorImpl<MCFixup> &Fixups) const;
264   unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
265     SmallVectorImpl<MCFixup> &Fixups) const;
266   unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
267     SmallVectorImpl<MCFixup> &Fixups) const;
268 
269   /// getSORegOpValue - Return an encoded so_reg shifted register value.
270   unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
271                            SmallVectorImpl<MCFixup> &Fixups) const;
272   unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
273                            SmallVectorImpl<MCFixup> &Fixups) const;
274   unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
275                              SmallVectorImpl<MCFixup> &Fixups) const;
276 
277   unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
278                                    SmallVectorImpl<MCFixup> &Fixups) const {
279     return 64 - MI.getOperand(Op).getImm();
280   }
281 
282   unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
283                                       SmallVectorImpl<MCFixup> &Fixups) const;
284 
285   unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
286                                   SmallVectorImpl<MCFixup> &Fixups) const;
287   unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
288                                       SmallVectorImpl<MCFixup> &Fixups) const;
289   unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
290                                         SmallVectorImpl<MCFixup> &Fixups) const;
291   unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
292                                         SmallVectorImpl<MCFixup> &Fixups) const;
293   unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
294                                      SmallVectorImpl<MCFixup> &Fixups) const;
295 
296   unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
297                              SmallVectorImpl<MCFixup> &Fixups) const;
298   unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
299                               SmallVectorImpl<MCFixup> &Fixups) const;
300   unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
301                               SmallVectorImpl<MCFixup> &Fixups) const;
302   unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
303                               SmallVectorImpl<MCFixup> &Fixups) const;
304 
305   unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
306                                  SmallVectorImpl<MCFixup> &Fixups) const;
307 
308   unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
309                                       unsigned EncodedValue) const;
310   unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
311                                           unsigned EncodedValue) const;
312   unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
313                                     unsigned EncodedValue) const;
314 
315   unsigned VFPThumb2PostEncoder(const MCInst &MI,
316                                 unsigned EncodedValue) const;
317 
318   void EmitByte(unsigned char C, raw_ostream &OS) const {
319     OS << (char)C;
320   }
321 
322   void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
323     // Output the constant in little endian byte order.
324     for (unsigned i = 0; i != Size; ++i) {
325       EmitByte(Val & 255, OS);
326       Val >>= 8;
327     }
328   }
329 
330   void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
331                          SmallVectorImpl<MCFixup> &Fixups) const;
332 };
333 
334 } // end anonymous namespace
335 
336 MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
337                                             const MCSubtargetInfo &STI,
338                                             MCContext &Ctx) {
339   return new ARMMCCodeEmitter(MCII, STI, Ctx);
340 }
341 
342 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
343 /// instructions, and rewrite them to their Thumb2 form if we are currently in
344 /// Thumb2 mode.
345 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
346                                                  unsigned EncodedValue) const {
347   if (isThumb2()) {
348     // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
349     // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
350     // set to 1111.
351     unsigned Bit24 = EncodedValue & 0x01000000;
352     unsigned Bit28 = Bit24 << 4;
353     EncodedValue &= 0xEFFFFFFF;
354     EncodedValue |= Bit28;
355     EncodedValue |= 0x0F000000;
356   }
357 
358   return EncodedValue;
359 }
360 
361 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
362 /// instructions, and rewrite them to their Thumb2 form if we are currently in
363 /// Thumb2 mode.
364 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
365                                                  unsigned EncodedValue) const {
366   if (isThumb2()) {
367     EncodedValue &= 0xF0FFFFFF;
368     EncodedValue |= 0x09000000;
369   }
370 
371   return EncodedValue;
372 }
373 
374 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
375 /// instructions, and rewrite them to their Thumb2 form if we are currently in
376 /// Thumb2 mode.
377 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
378                                                  unsigned EncodedValue) const {
379   if (isThumb2()) {
380     EncodedValue &= 0x00FFFFFF;
381     EncodedValue |= 0xEE000000;
382   }
383 
384   return EncodedValue;
385 }
386 
387 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
388 /// them to their Thumb2 form if we are currently in Thumb2 mode.
389 unsigned ARMMCCodeEmitter::
390 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
391   if (isThumb2()) {
392     EncodedValue &= 0x0FFFFFFF;
393     EncodedValue |= 0xE0000000;
394   }
395   return EncodedValue;
396 }
397 
398 /// getMachineOpValue - Return binary encoding of operand. If the machine
399 /// operand requires relocation, record the relocation and return zero.
400 unsigned ARMMCCodeEmitter::
401 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
402                   SmallVectorImpl<MCFixup> &Fixups) const {
403   if (MO.isReg()) {
404     unsigned Reg = MO.getReg();
405     unsigned RegNo = getARMRegisterNumbering(Reg);
406 
407     // Q registers are encoded as 2x their register number.
408     switch (Reg) {
409     default:
410       return RegNo;
411     case ARM::Q0:  case ARM::Q1:  case ARM::Q2:  case ARM::Q3:
412     case ARM::Q4:  case ARM::Q5:  case ARM::Q6:  case ARM::Q7:
413     case ARM::Q8:  case ARM::Q9:  case ARM::Q10: case ARM::Q11:
414     case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
415       return 2 * RegNo;
416     }
417   } else if (MO.isImm()) {
418     return static_cast<unsigned>(MO.getImm());
419   } else if (MO.isFPImm()) {
420     return static_cast<unsigned>(APFloat(MO.getFPImm())
421                      .bitcastToAPInt().getHiBits(32).getLimitedValue());
422   }
423 
424   llvm_unreachable("Unable to encode MCOperand!");
425 }
426 
427 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
428 bool ARMMCCodeEmitter::
429 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
430                        unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
431   const MCOperand &MO  = MI.getOperand(OpIdx);
432   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
433 
434   Reg = getARMRegisterNumbering(MO.getReg());
435 
436   int32_t SImm = MO1.getImm();
437   bool isAdd = true;
438 
439   // Special value for #-0
440   if (SImm == INT32_MIN) {
441     SImm = 0;
442     isAdd = false;
443   }
444 
445   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
446   if (SImm < 0) {
447     SImm = -SImm;
448     isAdd = false;
449   }
450 
451   Imm = SImm;
452   return isAdd;
453 }
454 
455 /// getBranchTargetOpValue - Helper function to get the branch target operand,
456 /// which is either an immediate or requires a fixup.
457 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
458                                        unsigned FixupKind,
459                                        SmallVectorImpl<MCFixup> &Fixups) {
460   const MCOperand &MO = MI.getOperand(OpIdx);
461 
462   // If the destination is an immediate, we have nothing to do.
463   if (MO.isImm()) return MO.getImm();
464   assert(MO.isExpr() && "Unexpected branch target type!");
465   const MCExpr *Expr = MO.getExpr();
466   MCFixupKind Kind = MCFixupKind(FixupKind);
467   Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
468 
469   // All of the information is in the fixup.
470   return 0;
471 }
472 
473 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
474 // determined by negating them and XOR'ing them with bit 23.
475 static int32_t encodeThumbBLOffset(int32_t offset) {
476   offset >>= 1;
477   uint32_t S  = (offset & 0x800000) >> 23;
478   uint32_t J1 = (offset & 0x400000) >> 22;
479   uint32_t J2 = (offset & 0x200000) >> 21;
480   J1 = (~J1 & 0x1);
481   J2 = (~J2 & 0x1);
482   J1 ^= S;
483   J2 ^= S;
484 
485   offset &= ~0x600000;
486   offset |= J1 << 22;
487   offset |= J2 << 21;
488 
489   return offset;
490 }
491 
492 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
493 uint32_t ARMMCCodeEmitter::
494 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
495                         SmallVectorImpl<MCFixup> &Fixups) const {
496   const MCOperand MO = MI.getOperand(OpIdx);
497   if (MO.isExpr())
498     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
499                                     Fixups);
500   return encodeThumbBLOffset(MO.getImm());
501 }
502 
503 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
504 /// BLX branch target.
505 uint32_t ARMMCCodeEmitter::
506 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
507                          SmallVectorImpl<MCFixup> &Fixups) const {
508   const MCOperand MO = MI.getOperand(OpIdx);
509   if (MO.isExpr())
510     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
511                                     Fixups);
512   return encodeThumbBLOffset(MO.getImm());
513 }
514 
515 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
516 uint32_t ARMMCCodeEmitter::
517 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
518                         SmallVectorImpl<MCFixup> &Fixups) const {
519   const MCOperand MO = MI.getOperand(OpIdx);
520   if (MO.isExpr())
521     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
522                                     Fixups);
523   return (MO.getImm() >> 1);
524 }
525 
526 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
527 uint32_t ARMMCCodeEmitter::
528 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
529                          SmallVectorImpl<MCFixup> &Fixups) const {
530   const MCOperand MO = MI.getOperand(OpIdx);
531   if (MO.isExpr())
532     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
533                                     Fixups);
534   return (MO.getImm() >> 1);
535 }
536 
537 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
538 uint32_t ARMMCCodeEmitter::
539 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
540                         SmallVectorImpl<MCFixup> &Fixups) const {
541   const MCOperand MO = MI.getOperand(OpIdx);
542   if (MO.isExpr())
543     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
544   return (MO.getImm() >> 1);
545 }
546 
547 /// Return true if this branch has a non-always predication
548 static bool HasConditionalBranch(const MCInst &MI) {
549   int NumOp = MI.getNumOperands();
550   if (NumOp >= 2) {
551     for (int i = 0; i < NumOp-1; ++i) {
552       const MCOperand &MCOp1 = MI.getOperand(i);
553       const MCOperand &MCOp2 = MI.getOperand(i + 1);
554       if (MCOp1.isImm() && MCOp2.isReg() &&
555           (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
556         if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
557           return true;
558       }
559     }
560   }
561   return false;
562 }
563 
564 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
565 /// target.
566 uint32_t ARMMCCodeEmitter::
567 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
568                        SmallVectorImpl<MCFixup> &Fixups) const {
569   // FIXME: This really, really shouldn't use TargetMachine. We don't want
570   // coupling between MC and TM anywhere we can help it.
571   if (isThumb2())
572     return
573       ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
574   return getARMBranchTargetOpValue(MI, OpIdx, Fixups);
575 }
576 
577 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
578 /// target.
579 uint32_t ARMMCCodeEmitter::
580 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
581                           SmallVectorImpl<MCFixup> &Fixups) const {
582   const MCOperand MO = MI.getOperand(OpIdx);
583   if (MO.isExpr()) {
584     if (HasConditionalBranch(MI))
585       return ::getBranchTargetOpValue(MI, OpIdx,
586                                       ARM::fixup_arm_condbranch, Fixups);
587     return ::getBranchTargetOpValue(MI, OpIdx,
588                                     ARM::fixup_arm_uncondbranch, Fixups);
589   }
590 
591   return MO.getImm() >> 2;
592 }
593 
594 uint32_t ARMMCCodeEmitter::
595 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
596                           SmallVectorImpl<MCFixup> &Fixups) const {
597   const MCOperand MO = MI.getOperand(OpIdx);
598   if (MO.isExpr()) {
599     if (HasConditionalBranch(MI))
600       return ::getBranchTargetOpValue(MI, OpIdx,
601                                       ARM::fixup_arm_condbranch, Fixups);
602     return ::getBranchTargetOpValue(MI, OpIdx,
603                                     ARM::fixup_arm_uncondbranch, Fixups);
604   }
605 
606   return MO.getImm() >> 1;
607 }
608 
609 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
610 /// immediate branch target.
611 uint32_t ARMMCCodeEmitter::
612 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
613                        SmallVectorImpl<MCFixup> &Fixups) const {
614   unsigned Val =
615     ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
616   bool I  = (Val & 0x800000);
617   bool J1 = (Val & 0x400000);
618   bool J2 = (Val & 0x200000);
619   if (I ^ J1)
620     Val &= ~0x400000;
621   else
622     Val |= 0x400000;
623 
624   if (I ^ J2)
625     Val &= ~0x200000;
626   else
627     Val |= 0x200000;
628 
629   return Val;
630 }
631 
632 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
633 /// target.
634 uint32_t ARMMCCodeEmitter::
635 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
636                    SmallVectorImpl<MCFixup> &Fixups) const {
637   const MCOperand MO = MI.getOperand(OpIdx);
638   if (MO.isExpr())
639     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
640                                     Fixups);
641   int32_t offset = MO.getImm();
642   uint32_t Val = 0x2000;
643   if (offset < 0) {
644     Val = 0x1000;
645     offset *= -1;
646   }
647   Val |= offset;
648   return Val;
649 }
650 
651 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
652 /// target.
653 uint32_t ARMMCCodeEmitter::
654 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
655                    SmallVectorImpl<MCFixup> &Fixups) const {
656   const MCOperand MO = MI.getOperand(OpIdx);
657   if (MO.isExpr())
658     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
659                                     Fixups);
660   int32_t Val = MO.getImm();
661   if (Val < 0) {
662     Val *= -1;
663     Val |= 0x1000;
664   }
665   return Val;
666 }
667 
668 /// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
669 /// target.
670 uint32_t ARMMCCodeEmitter::
671 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
672                    SmallVectorImpl<MCFixup> &Fixups) const {
673   const MCOperand MO = MI.getOperand(OpIdx);
674   if (MO.isExpr())
675     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
676                                     Fixups);
677   return MO.getImm();
678 }
679 
680 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
681 /// operand.
682 uint32_t ARMMCCodeEmitter::
683 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
684                               SmallVectorImpl<MCFixup> &) const {
685   // [Rn, Rm]
686   //   {5-3} = Rm
687   //   {2-0} = Rn
688   const MCOperand &MO1 = MI.getOperand(OpIdx);
689   const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
690   unsigned Rn = getARMRegisterNumbering(MO1.getReg());
691   unsigned Rm = getARMRegisterNumbering(MO2.getReg());
692   return (Rm << 3) | Rn;
693 }
694 
695 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
696 uint32_t ARMMCCodeEmitter::
697 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
698                         SmallVectorImpl<MCFixup> &Fixups) const {
699   // {17-13} = reg
700   // {12}    = (U)nsigned (add == '1', sub == '0')
701   // {11-0}  = imm12
702   unsigned Reg, Imm12;
703   bool isAdd = true;
704   // If The first operand isn't a register, we have a label reference.
705   const MCOperand &MO = MI.getOperand(OpIdx);
706   if (!MO.isReg()) {
707     Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
708     Imm12 = 0;
709     isAdd = false ; // 'U' bit is set as part of the fixup.
710 
711     if (MO.isExpr()) {
712       const MCExpr *Expr = MO.getExpr();
713 
714       MCFixupKind Kind;
715       if (isThumb2())
716         Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
717       else
718         Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
719       Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
720 
721       ++MCNumCPRelocations;
722     } else {
723       Reg = ARM::PC;
724       int32_t Offset = MO.getImm();
725       // FIXME: Handle #-0.
726       if (Offset < 0) {
727         Offset *= -1;
728         isAdd = false;
729       }
730       Imm12 = Offset;
731     }
732   } else
733     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
734 
735   uint32_t Binary = Imm12 & 0xfff;
736   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
737   if (isAdd)
738     Binary |= (1 << 12);
739   Binary |= (Reg << 13);
740   return Binary;
741 }
742 
743 /// getT2Imm8s4OpValue - Return encoding info for
744 /// '+/- imm8<<2' operand.
745 uint32_t ARMMCCodeEmitter::
746 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
747                    SmallVectorImpl<MCFixup> &Fixups) const {
748   // FIXME: The immediate operand should have already been encoded like this
749   // before ever getting here. The encoder method should just need to combine
750   // the MI operands for the register and the offset into a single
751   // representation for the complex operand in the .td file. This isn't just
752   // style, unfortunately. As-is, we can't represent the distinct encoding
753   // for #-0.
754 
755   // {8}    = (U)nsigned (add == '1', sub == '0')
756   // {7-0}  = imm8
757   int32_t Imm8 = MI.getOperand(OpIdx).getImm();
758   bool isAdd = Imm8 >= 0;
759 
760   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
761   if (Imm8 < 0)
762     Imm8 = -Imm8;
763 
764   // Scaled by 4.
765   Imm8 /= 4;
766 
767   uint32_t Binary = Imm8 & 0xff;
768   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
769   if (isAdd)
770     Binary |= (1 << 8);
771   return Binary;
772 }
773 
774 /// getT2AddrModeImm8s4OpValue - Return encoding info for
775 /// 'reg +/- imm8<<2' operand.
776 uint32_t ARMMCCodeEmitter::
777 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
778                         SmallVectorImpl<MCFixup> &Fixups) const {
779   // {12-9} = reg
780   // {8}    = (U)nsigned (add == '1', sub == '0')
781   // {7-0}  = imm8
782   unsigned Reg, Imm8;
783   bool isAdd = true;
784   // If The first operand isn't a register, we have a label reference.
785   const MCOperand &MO = MI.getOperand(OpIdx);
786   if (!MO.isReg()) {
787     Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
788     Imm8 = 0;
789     isAdd = false ; // 'U' bit is set as part of the fixup.
790 
791     assert(MO.isExpr() && "Unexpected machine operand type!");
792     const MCExpr *Expr = MO.getExpr();
793     MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
794     Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
795 
796     ++MCNumCPRelocations;
797   } else
798     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
799 
800   // FIXME: The immediate operand should have already been encoded like this
801   // before ever getting here. The encoder method should just need to combine
802   // the MI operands for the register and the offset into a single
803   // representation for the complex operand in the .td file. This isn't just
804   // style, unfortunately. As-is, we can't represent the distinct encoding
805   // for #-0.
806   uint32_t Binary = (Imm8 >> 2) & 0xff;
807   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
808   if (isAdd)
809     Binary |= (1 << 8);
810   Binary |= (Reg << 9);
811   return Binary;
812 }
813 
814 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
815 /// 'reg + imm8<<2' operand.
816 uint32_t ARMMCCodeEmitter::
817 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
818                         SmallVectorImpl<MCFixup> &Fixups) const {
819   // {11-8} = reg
820   // {7-0}  = imm8
821   const MCOperand &MO = MI.getOperand(OpIdx);
822   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
823   unsigned Reg = getARMRegisterNumbering(MO.getReg());
824   unsigned Imm8 = MO1.getImm();
825   return (Reg << 8) | Imm8;
826 }
827 
828 // FIXME: This routine assumes that a binary
829 // expression will always result in a PCRel expression
830 // In reality, its only true if one or more subexpressions
831 // is itself a PCRel (i.e. "." in asm or some other pcrel construct)
832 // but this is good enough for now.
833 static bool EvaluateAsPCRel(const MCExpr *Expr) {
834   switch (Expr->getKind()) {
835   default: llvm_unreachable("Unexpected expression type");
836   case MCExpr::SymbolRef: return false;
837   case MCExpr::Binary: return true;
838   }
839 }
840 
841 uint32_t
842 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
843                                       SmallVectorImpl<MCFixup> &Fixups) const {
844   // {20-16} = imm{15-12}
845   // {11-0}  = imm{11-0}
846   const MCOperand &MO = MI.getOperand(OpIdx);
847   if (MO.isImm())
848     // Hi / lo 16 bits already extracted during earlier passes.
849     return static_cast<unsigned>(MO.getImm());
850 
851   // Handle :upper16: and :lower16: assembly prefixes.
852   const MCExpr *E = MO.getExpr();
853   if (E->getKind() == MCExpr::Target) {
854     const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
855     E = ARM16Expr->getSubExpr();
856 
857     MCFixupKind Kind;
858     switch (ARM16Expr->getKind()) {
859     default: llvm_unreachable("Unsupported ARMFixup");
860     case ARMMCExpr::VK_ARM_HI16:
861       if (!isTargetDarwin() && EvaluateAsPCRel(E))
862         Kind = MCFixupKind(isThumb2()
863                            ? ARM::fixup_t2_movt_hi16_pcrel
864                            : ARM::fixup_arm_movt_hi16_pcrel);
865       else
866         Kind = MCFixupKind(isThumb2()
867                            ? ARM::fixup_t2_movt_hi16
868                            : ARM::fixup_arm_movt_hi16);
869       break;
870     case ARMMCExpr::VK_ARM_LO16:
871       if (!isTargetDarwin() && EvaluateAsPCRel(E))
872         Kind = MCFixupKind(isThumb2()
873                            ? ARM::fixup_t2_movw_lo16_pcrel
874                            : ARM::fixup_arm_movw_lo16_pcrel);
875       else
876         Kind = MCFixupKind(isThumb2()
877                            ? ARM::fixup_t2_movw_lo16
878                            : ARM::fixup_arm_movw_lo16);
879       break;
880     }
881     Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
882     return 0;
883   };
884 
885   llvm_unreachable("Unsupported MCExpr type in MCOperand!");
886 }
887 
888 uint32_t ARMMCCodeEmitter::
889 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
890                     SmallVectorImpl<MCFixup> &Fixups) const {
891   const MCOperand &MO = MI.getOperand(OpIdx);
892   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
893   const MCOperand &MO2 = MI.getOperand(OpIdx+2);
894   unsigned Rn = getARMRegisterNumbering(MO.getReg());
895   unsigned Rm = getARMRegisterNumbering(MO1.getReg());
896   unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
897   bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
898   ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
899   unsigned SBits = getShiftOp(ShOp);
900 
901   // {16-13} = Rn
902   // {12}    = isAdd
903   // {11-0}  = shifter
904   //  {3-0}  = Rm
905   //  {4}    = 0
906   //  {6-5}  = type
907   //  {11-7} = imm
908   uint32_t Binary = Rm;
909   Binary |= Rn << 13;
910   Binary |= SBits << 5;
911   Binary |= ShImm << 7;
912   if (isAdd)
913     Binary |= 1 << 12;
914   return Binary;
915 }
916 
917 uint32_t ARMMCCodeEmitter::
918 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
919                     SmallVectorImpl<MCFixup> &Fixups) const {
920   // {17-14}  Rn
921   // {13}     1 == imm12, 0 == Rm
922   // {12}     isAdd
923   // {11-0}   imm12/Rm
924   const MCOperand &MO = MI.getOperand(OpIdx);
925   unsigned Rn = getARMRegisterNumbering(MO.getReg());
926   uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
927   Binary |= Rn << 14;
928   return Binary;
929 }
930 
931 uint32_t ARMMCCodeEmitter::
932 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
933                           SmallVectorImpl<MCFixup> &Fixups) const {
934   // {13}     1 == imm12, 0 == Rm
935   // {12}     isAdd
936   // {11-0}   imm12/Rm
937   const MCOperand &MO = MI.getOperand(OpIdx);
938   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
939   unsigned Imm = MO1.getImm();
940   bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
941   bool isReg = MO.getReg() != 0;
942   uint32_t Binary = ARM_AM::getAM2Offset(Imm);
943   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
944   if (isReg) {
945     ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
946     Binary <<= 7;                    // Shift amount is bits [11:7]
947     Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
948     Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
949   }
950   return Binary | (isAdd << 12) | (isReg << 13);
951 }
952 
953 uint32_t ARMMCCodeEmitter::
954 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
955                      SmallVectorImpl<MCFixup> &Fixups) const {
956   // {4}      isAdd
957   // {3-0}    Rm
958   const MCOperand &MO = MI.getOperand(OpIdx);
959   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
960   bool isAdd = MO1.getImm() != 0;
961   return getARMRegisterNumbering(MO.getReg()) | (isAdd << 4);
962 }
963 
964 uint32_t ARMMCCodeEmitter::
965 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
966                           SmallVectorImpl<MCFixup> &Fixups) const {
967   // {9}      1 == imm8, 0 == Rm
968   // {8}      isAdd
969   // {7-4}    imm7_4/zero
970   // {3-0}    imm3_0/Rm
971   const MCOperand &MO = MI.getOperand(OpIdx);
972   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
973   unsigned Imm = MO1.getImm();
974   bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
975   bool isImm = MO.getReg() == 0;
976   uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
977   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
978   if (!isImm)
979     Imm8 = getARMRegisterNumbering(MO.getReg());
980   return Imm8 | (isAdd << 8) | (isImm << 9);
981 }
982 
983 uint32_t ARMMCCodeEmitter::
984 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
985                     SmallVectorImpl<MCFixup> &Fixups) const {
986   // {13}     1 == imm8, 0 == Rm
987   // {12-9}   Rn
988   // {8}      isAdd
989   // {7-4}    imm7_4/zero
990   // {3-0}    imm3_0/Rm
991   const MCOperand &MO = MI.getOperand(OpIdx);
992   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
993   const MCOperand &MO2 = MI.getOperand(OpIdx+2);
994 
995   // If The first operand isn't a register, we have a label reference.
996   if (!MO.isReg()) {
997     unsigned Rn = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
998 
999     assert(MO.isExpr() && "Unexpected machine operand type!");
1000     const MCExpr *Expr = MO.getExpr();
1001     MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1002     Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1003 
1004     ++MCNumCPRelocations;
1005     return (Rn << 9) | (1 << 13);
1006   }
1007   unsigned Rn = getARMRegisterNumbering(MO.getReg());
1008   unsigned Imm = MO2.getImm();
1009   bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1010   bool isImm = MO1.getReg() == 0;
1011   uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1012   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1013   if (!isImm)
1014     Imm8 = getARMRegisterNumbering(MO1.getReg());
1015   return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1016 }
1017 
1018 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1019 uint32_t ARMMCCodeEmitter::
1020 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1021                           SmallVectorImpl<MCFixup> &Fixups) const {
1022   // [SP, #imm]
1023   //   {7-0} = imm8
1024   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1025   assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1026          "Unexpected base register!");
1027 
1028   // The immediate is already shifted for the implicit zeroes, so no change
1029   // here.
1030   return MO1.getImm() & 0xff;
1031 }
1032 
1033 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1034 uint32_t ARMMCCodeEmitter::
1035 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1036                      SmallVectorImpl<MCFixup> &Fixups) const {
1037   // [Rn, #imm]
1038   //   {7-3} = imm5
1039   //   {2-0} = Rn
1040   const MCOperand &MO = MI.getOperand(OpIdx);
1041   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1042   unsigned Rn = getARMRegisterNumbering(MO.getReg());
1043   unsigned Imm5 = MO1.getImm();
1044   return ((Imm5 & 0x1f) << 3) | Rn;
1045 }
1046 
1047 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1048 uint32_t ARMMCCodeEmitter::
1049 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1050                      SmallVectorImpl<MCFixup> &Fixups) const {
1051   const MCOperand MO = MI.getOperand(OpIdx);
1052   if (MO.isExpr())
1053     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
1054   return (MO.getImm() >> 2);
1055 }
1056 
1057 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
1058 uint32_t ARMMCCodeEmitter::
1059 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1060                     SmallVectorImpl<MCFixup> &Fixups) const {
1061   // {12-9} = reg
1062   // {8}    = (U)nsigned (add == '1', sub == '0')
1063   // {7-0}  = imm8
1064   unsigned Reg, Imm8;
1065   bool isAdd;
1066   // If The first operand isn't a register, we have a label reference.
1067   const MCOperand &MO = MI.getOperand(OpIdx);
1068   if (!MO.isReg()) {
1069     Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
1070     Imm8 = 0;
1071     isAdd = false; // 'U' bit is handled as part of the fixup.
1072 
1073     assert(MO.isExpr() && "Unexpected machine operand type!");
1074     const MCExpr *Expr = MO.getExpr();
1075     MCFixupKind Kind;
1076     if (isThumb2())
1077       Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1078     else
1079       Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1080     Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1081 
1082     ++MCNumCPRelocations;
1083   } else {
1084     EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
1085     isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1086   }
1087 
1088   uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1089   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1090   if (isAdd)
1091     Binary |= (1 << 8);
1092   Binary |= (Reg << 9);
1093   return Binary;
1094 }
1095 
1096 unsigned ARMMCCodeEmitter::
1097 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1098                 SmallVectorImpl<MCFixup> &Fixups) const {
1099   // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1100   // shifted. The second is Rs, the amount to shift by, and the third specifies
1101   // the type of the shift.
1102   //
1103   // {3-0} = Rm.
1104   // {4}   = 1
1105   // {6-5} = type
1106   // {11-8} = Rs
1107   // {7}    = 0
1108 
1109   const MCOperand &MO  = MI.getOperand(OpIdx);
1110   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1111   const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1112   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1113 
1114   // Encode Rm.
1115   unsigned Binary = getARMRegisterNumbering(MO.getReg());
1116 
1117   // Encode the shift opcode.
1118   unsigned SBits = 0;
1119   unsigned Rs = MO1.getReg();
1120   if (Rs) {
1121     // Set shift operand (bit[7:4]).
1122     // LSL - 0001
1123     // LSR - 0011
1124     // ASR - 0101
1125     // ROR - 0111
1126     switch (SOpc) {
1127     default: llvm_unreachable("Unknown shift opc!");
1128     case ARM_AM::lsl: SBits = 0x1; break;
1129     case ARM_AM::lsr: SBits = 0x3; break;
1130     case ARM_AM::asr: SBits = 0x5; break;
1131     case ARM_AM::ror: SBits = 0x7; break;
1132     }
1133   }
1134 
1135   Binary |= SBits << 4;
1136 
1137   // Encode the shift operation Rs.
1138   // Encode Rs bit[11:8].
1139   assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1140   return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
1141 }
1142 
1143 unsigned ARMMCCodeEmitter::
1144 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1145                 SmallVectorImpl<MCFixup> &Fixups) const {
1146   // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1147   // shifted. The second is the amount to shift by.
1148   //
1149   // {3-0} = Rm.
1150   // {4}   = 0
1151   // {6-5} = type
1152   // {11-7} = imm
1153 
1154   const MCOperand &MO  = MI.getOperand(OpIdx);
1155   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1156   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1157 
1158   // Encode Rm.
1159   unsigned Binary = getARMRegisterNumbering(MO.getReg());
1160 
1161   // Encode the shift opcode.
1162   unsigned SBits = 0;
1163 
1164   // Set shift operand (bit[6:4]).
1165   // LSL - 000
1166   // LSR - 010
1167   // ASR - 100
1168   // ROR - 110
1169   // RRX - 110 and bit[11:8] clear.
1170   switch (SOpc) {
1171   default: llvm_unreachable("Unknown shift opc!");
1172   case ARM_AM::lsl: SBits = 0x0; break;
1173   case ARM_AM::lsr: SBits = 0x2; break;
1174   case ARM_AM::asr: SBits = 0x4; break;
1175   case ARM_AM::ror: SBits = 0x6; break;
1176   case ARM_AM::rrx:
1177     Binary |= 0x60;
1178     return Binary;
1179   }
1180 
1181   // Encode shift_imm bit[11:7].
1182   Binary |= SBits << 4;
1183   unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1184   assert(Offset && "Offset must be in range 1-32!");
1185   if (Offset == 32) Offset = 0;
1186   return Binary | (Offset << 7);
1187 }
1188 
1189 
1190 unsigned ARMMCCodeEmitter::
1191 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1192                 SmallVectorImpl<MCFixup> &Fixups) const {
1193   const MCOperand &MO1 = MI.getOperand(OpNum);
1194   const MCOperand &MO2 = MI.getOperand(OpNum+1);
1195   const MCOperand &MO3 = MI.getOperand(OpNum+2);
1196 
1197   // Encoded as [Rn, Rm, imm].
1198   // FIXME: Needs fixup support.
1199   unsigned Value = getARMRegisterNumbering(MO1.getReg());
1200   Value <<= 4;
1201   Value |= getARMRegisterNumbering(MO2.getReg());
1202   Value <<= 2;
1203   Value |= MO3.getImm();
1204 
1205   return Value;
1206 }
1207 
1208 unsigned ARMMCCodeEmitter::
1209 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1210                          SmallVectorImpl<MCFixup> &Fixups) const {
1211   const MCOperand &MO1 = MI.getOperand(OpNum);
1212   const MCOperand &MO2 = MI.getOperand(OpNum+1);
1213 
1214   // FIXME: Needs fixup support.
1215   unsigned Value = getARMRegisterNumbering(MO1.getReg());
1216 
1217   // Even though the immediate is 8 bits long, we need 9 bits in order
1218   // to represent the (inverse of the) sign bit.
1219   Value <<= 9;
1220   int32_t tmp = (int32_t)MO2.getImm();
1221   if (tmp < 0)
1222     tmp = abs(tmp);
1223   else
1224     Value |= 256; // Set the ADD bit
1225   Value |= tmp & 255;
1226   return Value;
1227 }
1228 
1229 unsigned ARMMCCodeEmitter::
1230 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1231                          SmallVectorImpl<MCFixup> &Fixups) const {
1232   const MCOperand &MO1 = MI.getOperand(OpNum);
1233 
1234   // FIXME: Needs fixup support.
1235   unsigned Value = 0;
1236   int32_t tmp = (int32_t)MO1.getImm();
1237   if (tmp < 0)
1238     tmp = abs(tmp);
1239   else
1240     Value |= 256; // Set the ADD bit
1241   Value |= tmp & 255;
1242   return Value;
1243 }
1244 
1245 unsigned ARMMCCodeEmitter::
1246 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1247                          SmallVectorImpl<MCFixup> &Fixups) const {
1248   const MCOperand &MO1 = MI.getOperand(OpNum);
1249 
1250   // FIXME: Needs fixup support.
1251   unsigned Value = 0;
1252   int32_t tmp = (int32_t)MO1.getImm();
1253   if (tmp < 0)
1254     tmp = abs(tmp);
1255   else
1256     Value |= 4096; // Set the ADD bit
1257   Value |= tmp & 4095;
1258   return Value;
1259 }
1260 
1261 unsigned ARMMCCodeEmitter::
1262 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1263                 SmallVectorImpl<MCFixup> &Fixups) const {
1264   // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1265   // shifted. The second is the amount to shift by.
1266   //
1267   // {3-0} = Rm.
1268   // {4}   = 0
1269   // {6-5} = type
1270   // {11-7} = imm
1271 
1272   const MCOperand &MO  = MI.getOperand(OpIdx);
1273   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1274   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1275 
1276   // Encode Rm.
1277   unsigned Binary = getARMRegisterNumbering(MO.getReg());
1278 
1279   // Encode the shift opcode.
1280   unsigned SBits = 0;
1281   // Set shift operand (bit[6:4]).
1282   // LSL - 000
1283   // LSR - 010
1284   // ASR - 100
1285   // ROR - 110
1286   switch (SOpc) {
1287   default: llvm_unreachable("Unknown shift opc!");
1288   case ARM_AM::lsl: SBits = 0x0; break;
1289   case ARM_AM::lsr: SBits = 0x2; break;
1290   case ARM_AM::asr: SBits = 0x4; break;
1291   case ARM_AM::rrx: // FALLTHROUGH
1292   case ARM_AM::ror: SBits = 0x6; break;
1293   }
1294 
1295   Binary |= SBits << 4;
1296   if (SOpc == ARM_AM::rrx)
1297     return Binary;
1298 
1299   // Encode shift_imm bit[11:7].
1300   return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1301 }
1302 
1303 unsigned ARMMCCodeEmitter::
1304 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1305                                SmallVectorImpl<MCFixup> &Fixups) const {
1306   // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1307   // msb of the mask.
1308   const MCOperand &MO = MI.getOperand(Op);
1309   uint32_t v = ~MO.getImm();
1310   uint32_t lsb = CountTrailingZeros_32(v);
1311   uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
1312   assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1313   return lsb | (msb << 5);
1314 }
1315 
1316 unsigned ARMMCCodeEmitter::
1317 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1318                        SmallVectorImpl<MCFixup> &Fixups) const {
1319   // VLDM/VSTM:
1320   //   {12-8} = Vd
1321   //   {7-0}  = Number of registers
1322   //
1323   // LDM/STM:
1324   //   {15-0}  = Bitfield of GPRs.
1325   unsigned Reg = MI.getOperand(Op).getReg();
1326   bool SPRRegs = llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1327   bool DPRRegs = llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1328 
1329   unsigned Binary = 0;
1330 
1331   if (SPRRegs || DPRRegs) {
1332     // VLDM/VSTM
1333     unsigned RegNo = getARMRegisterNumbering(Reg);
1334     unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1335     Binary |= (RegNo & 0x1f) << 8;
1336     if (SPRRegs)
1337       Binary |= NumRegs;
1338     else
1339       Binary |= NumRegs * 2;
1340   } else {
1341     for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1342       unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1343       Binary |= 1 << RegNo;
1344     }
1345   }
1346 
1347   return Binary;
1348 }
1349 
1350 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1351 /// with the alignment operand.
1352 unsigned ARMMCCodeEmitter::
1353 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1354                            SmallVectorImpl<MCFixup> &Fixups) const {
1355   const MCOperand &Reg = MI.getOperand(Op);
1356   const MCOperand &Imm = MI.getOperand(Op + 1);
1357 
1358   unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1359   unsigned Align = 0;
1360 
1361   switch (Imm.getImm()) {
1362   default: break;
1363   case 2:
1364   case 4:
1365   case 8:  Align = 0x01; break;
1366   case 16: Align = 0x02; break;
1367   case 32: Align = 0x03; break;
1368   }
1369 
1370   return RegNo | (Align << 4);
1371 }
1372 
1373 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1374 /// along  with the alignment operand for use in VST1 and VLD1 with size 32.
1375 unsigned ARMMCCodeEmitter::
1376 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1377                                     SmallVectorImpl<MCFixup> &Fixups) const {
1378   const MCOperand &Reg = MI.getOperand(Op);
1379   const MCOperand &Imm = MI.getOperand(Op + 1);
1380 
1381   unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1382   unsigned Align = 0;
1383 
1384   switch (Imm.getImm()) {
1385   default: break;
1386   case 8:
1387   case 16:
1388   case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1389   case 2: Align = 0x00; break;
1390   case 4: Align = 0x03; break;
1391   }
1392 
1393   return RegNo | (Align << 4);
1394 }
1395 
1396 
1397 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1398 /// alignment operand for use in VLD-dup instructions.  This is the same as
1399 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1400 /// different for VLD4-dup.
1401 unsigned ARMMCCodeEmitter::
1402 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1403                               SmallVectorImpl<MCFixup> &Fixups) const {
1404   const MCOperand &Reg = MI.getOperand(Op);
1405   const MCOperand &Imm = MI.getOperand(Op + 1);
1406 
1407   unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1408   unsigned Align = 0;
1409 
1410   switch (Imm.getImm()) {
1411   default: break;
1412   case 2:
1413   case 4:
1414   case 8:  Align = 0x01; break;
1415   case 16: Align = 0x03; break;
1416   }
1417 
1418   return RegNo | (Align << 4);
1419 }
1420 
1421 unsigned ARMMCCodeEmitter::
1422 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1423                           SmallVectorImpl<MCFixup> &Fixups) const {
1424   const MCOperand &MO = MI.getOperand(Op);
1425   if (MO.getReg() == 0) return 0x0D;
1426   return getARMRegisterNumbering(MO.getReg());
1427 }
1428 
1429 unsigned ARMMCCodeEmitter::
1430 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1431                   SmallVectorImpl<MCFixup> &Fixups) const {
1432   return 8 - MI.getOperand(Op).getImm();
1433 }
1434 
1435 unsigned ARMMCCodeEmitter::
1436 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1437                    SmallVectorImpl<MCFixup> &Fixups) const {
1438   return 16 - MI.getOperand(Op).getImm();
1439 }
1440 
1441 unsigned ARMMCCodeEmitter::
1442 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1443                    SmallVectorImpl<MCFixup> &Fixups) const {
1444   return 32 - MI.getOperand(Op).getImm();
1445 }
1446 
1447 unsigned ARMMCCodeEmitter::
1448 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1449                    SmallVectorImpl<MCFixup> &Fixups) const {
1450   return 64 - MI.getOperand(Op).getImm();
1451 }
1452 
1453 void ARMMCCodeEmitter::
1454 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1455                   SmallVectorImpl<MCFixup> &Fixups) const {
1456   // Pseudo instructions don't get encoded.
1457   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1458   uint64_t TSFlags = Desc.TSFlags;
1459   if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1460     return;
1461 
1462   int Size;
1463   if (Desc.getSize() == 2 || Desc.getSize() == 4)
1464     Size = Desc.getSize();
1465   else
1466     llvm_unreachable("Unexpected instruction size!");
1467 
1468   uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1469   // Thumb 32-bit wide instructions need to emit the high order halfword
1470   // first.
1471   if (isThumb() && Size == 4) {
1472     EmitConstant(Binary >> 16, 2, OS);
1473     EmitConstant(Binary & 0xffff, 2, OS);
1474   } else
1475     EmitConstant(Binary, Size, OS);
1476   ++MCNumEmitted;  // Keep track of the # of mi's emitted.
1477 }
1478 
1479 #include "ARMGenMCCodeEmitter.inc"
1480