1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the ARMMCCodeEmitter class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/ARMMCTargetDesc.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "MCTargetDesc/ARMFixupKinds.h" 18 #include "MCTargetDesc/ARMMCExpr.h" 19 #include "llvm/ADT/APFloat.h" 20 #include "llvm/ADT/Statistic.h" 21 #include "llvm/MC/MCCodeEmitter.h" 22 #include "llvm/MC/MCContext.h" 23 #include "llvm/MC/MCExpr.h" 24 #include "llvm/MC/MCInst.h" 25 #include "llvm/MC/MCInstrInfo.h" 26 #include "llvm/MC/MCRegisterInfo.h" 27 #include "llvm/MC/MCSubtargetInfo.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/raw_ostream.h" 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "mccodeemitter" 34 35 STATISTIC(MCNumEmitted, "Number of MC instructions emitted."); 36 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created."); 37 38 namespace { 39 class ARMMCCodeEmitter : public MCCodeEmitter { 40 ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete; 41 void operator=(const ARMMCCodeEmitter &) = delete; 42 const MCInstrInfo &MCII; 43 const MCContext &CTX; 44 bool IsLittleEndian; 45 46 public: 47 ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle) 48 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) { 49 } 50 51 ~ARMMCCodeEmitter() override {} 52 53 bool isThumb(const MCSubtargetInfo &STI) const { 54 return STI.getFeatureBits()[ARM::ModeThumb]; 55 } 56 bool isThumb2(const MCSubtargetInfo &STI) const { 57 return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2]; 58 } 59 bool isTargetMachO(const MCSubtargetInfo &STI) const { 60 const Triple &TT = STI.getTargetTriple(); 61 return TT.isOSBinFormatMachO(); 62 } 63 64 unsigned getMachineSoImmOpValue(unsigned SoImm) const; 65 66 // getBinaryCodeForInstr - TableGen'erated function for getting the 67 // binary encoding for an instruction. 68 uint64_t getBinaryCodeForInstr(const MCInst &MI, 69 SmallVectorImpl<MCFixup> &Fixups, 70 const MCSubtargetInfo &STI) const; 71 72 /// getMachineOpValue - Return binary encoding of operand. If the machine 73 /// operand requires relocation, record the relocation and return zero. 74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 75 SmallVectorImpl<MCFixup> &Fixups, 76 const MCSubtargetInfo &STI) const; 77 78 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of 79 /// the specified operand. This is used for operands with :lower16: and 80 /// :upper16: prefixes. 81 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 82 SmallVectorImpl<MCFixup> &Fixups, 83 const MCSubtargetInfo &STI) const; 84 85 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, 86 unsigned &Reg, unsigned &Imm, 87 SmallVectorImpl<MCFixup> &Fixups, 88 const MCSubtargetInfo &STI) const; 89 90 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate 91 /// BL branch target. 92 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 93 SmallVectorImpl<MCFixup> &Fixups, 94 const MCSubtargetInfo &STI) const; 95 96 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 97 /// BLX branch target. 98 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 99 SmallVectorImpl<MCFixup> &Fixups, 100 const MCSubtargetInfo &STI) const; 101 102 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 103 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 104 SmallVectorImpl<MCFixup> &Fixups, 105 const MCSubtargetInfo &STI) const; 106 107 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 108 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 109 SmallVectorImpl<MCFixup> &Fixups, 110 const MCSubtargetInfo &STI) const; 111 112 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 113 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 114 SmallVectorImpl<MCFixup> &Fixups, 115 const MCSubtargetInfo &STI) const; 116 117 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate 118 /// branch target. 119 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 120 SmallVectorImpl<MCFixup> &Fixups, 121 const MCSubtargetInfo &STI) const; 122 123 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit 124 /// immediate Thumb2 direct branch target. 125 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 126 SmallVectorImpl<MCFixup> &Fixups, 127 const MCSubtargetInfo &STI) const; 128 129 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate 130 /// branch target. 131 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 132 SmallVectorImpl<MCFixup> &Fixups, 133 const MCSubtargetInfo &STI) const; 134 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 135 SmallVectorImpl<MCFixup> &Fixups, 136 const MCSubtargetInfo &STI) const; 137 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 138 SmallVectorImpl<MCFixup> &Fixups, 139 const MCSubtargetInfo &STI) const; 140 141 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate 142 /// ADR label target. 143 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 144 SmallVectorImpl<MCFixup> &Fixups, 145 const MCSubtargetInfo &STI) const; 146 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 147 SmallVectorImpl<MCFixup> &Fixups, 148 const MCSubtargetInfo &STI) const; 149 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 150 SmallVectorImpl<MCFixup> &Fixups, 151 const MCSubtargetInfo &STI) const; 152 153 154 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' 155 /// operand. 156 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 157 SmallVectorImpl<MCFixup> &Fixups, 158 const MCSubtargetInfo &STI) const; 159 160 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand. 161 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 162 SmallVectorImpl<MCFixup> &Fixups, 163 const MCSubtargetInfo &STI) const; 164 165 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2' 166 /// operand. 167 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 168 SmallVectorImpl<MCFixup> &Fixups, 169 const MCSubtargetInfo &STI) const; 170 171 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2' 172 /// operand. 173 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, 174 SmallVectorImpl<MCFixup> &Fixups, 175 const MCSubtargetInfo &STI) const; 176 177 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2' 178 /// operand. 179 uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, 180 SmallVectorImpl<MCFixup> &Fixups, 181 const MCSubtargetInfo &STI) const; 182 183 184 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm' 185 /// operand as needed by load/store instructions. 186 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 187 SmallVectorImpl<MCFixup> &Fixups, 188 const MCSubtargetInfo &STI) const; 189 190 /// getLdStmModeOpValue - Return encoding for load/store multiple mode. 191 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, 192 SmallVectorImpl<MCFixup> &Fixups, 193 const MCSubtargetInfo &STI) const { 194 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); 195 switch (Mode) { 196 default: llvm_unreachable("Unknown addressing sub-mode!"); 197 case ARM_AM::da: return 0; 198 case ARM_AM::ia: return 1; 199 case ARM_AM::db: return 2; 200 case ARM_AM::ib: return 3; 201 } 202 } 203 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 204 /// 205 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { 206 switch (ShOpc) { 207 case ARM_AM::no_shift: 208 case ARM_AM::lsl: return 0; 209 case ARM_AM::lsr: return 1; 210 case ARM_AM::asr: return 2; 211 case ARM_AM::ror: 212 case ARM_AM::rrx: return 3; 213 } 214 llvm_unreachable("Invalid ShiftOpc!"); 215 } 216 217 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands. 218 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 219 SmallVectorImpl<MCFixup> &Fixups, 220 const MCSubtargetInfo &STI) const; 221 222 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands. 223 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 224 SmallVectorImpl<MCFixup> &Fixups, 225 const MCSubtargetInfo &STI) const; 226 227 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands. 228 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 229 SmallVectorImpl<MCFixup> &Fixups, 230 const MCSubtargetInfo &STI) const; 231 232 /// getAddrMode3OpValue - Return encoding for addrmode3 operands. 233 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 234 SmallVectorImpl<MCFixup> &Fixups, 235 const MCSubtargetInfo &STI) const; 236 237 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12' 238 /// operand. 239 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 240 SmallVectorImpl<MCFixup> &Fixups, 241 const MCSubtargetInfo &STI) const; 242 243 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 244 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 245 SmallVectorImpl<MCFixup> &Fixups, 246 const MCSubtargetInfo &STI) const; 247 248 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 249 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 250 SmallVectorImpl<MCFixup> &Fixups, 251 const MCSubtargetInfo &STI) const; 252 253 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand. 254 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 255 SmallVectorImpl<MCFixup> &Fixups, 256 const MCSubtargetInfo &STI) const; 257 258 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand. 259 uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx, 260 SmallVectorImpl<MCFixup> &Fixups, 261 const MCSubtargetInfo &STI) const; 262 263 /// getCCOutOpValue - Return encoding of the 's' bit. 264 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op, 265 SmallVectorImpl<MCFixup> &Fixups, 266 const MCSubtargetInfo &STI) const { 267 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or 268 // '1' respectively. 269 return MI.getOperand(Op).getReg() == ARM::CPSR; 270 } 271 272 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value. 273 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op, 274 SmallVectorImpl<MCFixup> &Fixups, 275 const MCSubtargetInfo &STI) const { 276 277 const MCOperand &MO = MI.getOperand(Op); 278 279 // We expect MO to be an immediate or an expression, 280 // if it is an immediate - that's fine, just encode the value. 281 // Otherwise - create a Fixup. 282 if (MO.isExpr()) { 283 const MCExpr *Expr = MO.getExpr(); 284 // In instruction code this value always encoded as lowest 12 bits, 285 // so we don't have to perform any specific adjustments. 286 // Due to requirements of relocatable records we have to use FK_Data_4. 287 // See ARMELFObjectWriter::ExplicitRelSym and 288 // ARMELFObjectWriter::GetRelocTypeInner for more details. 289 MCFixupKind Kind = MCFixupKind(FK_Data_4); 290 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 291 return 0; 292 } 293 294 unsigned SoImm = MO.getImm(); 295 int SoImmVal = ARM_AM::getSOImmVal(SoImm); 296 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 297 298 // Encode rotate_imm. 299 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 300 << ARMII::SoRotImmShift; 301 302 // Encode immed_8. 303 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 304 return Binary; 305 } 306 307 unsigned getModImmOpValue(const MCInst &MI, unsigned Op, 308 SmallVectorImpl<MCFixup> &Fixups, 309 const MCSubtargetInfo &ST) const { 310 const MCOperand &MO = MI.getOperand(Op); 311 312 // Support for fixups (MCFixup) 313 if (MO.isExpr()) { 314 const MCExpr *Expr = MO.getExpr(); 315 // Fixups resolve to plain values that need to be encoded. 316 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_mod_imm); 317 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 318 return 0; 319 } 320 321 // Immediate is already in its encoded format 322 return MO.getImm(); 323 } 324 325 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value. 326 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op, 327 SmallVectorImpl<MCFixup> &Fixups, 328 const MCSubtargetInfo &STI) const { 329 unsigned SoImm = MI.getOperand(Op).getImm(); 330 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm); 331 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?"); 332 return Encoded; 333 } 334 335 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 336 SmallVectorImpl<MCFixup> &Fixups, 337 const MCSubtargetInfo &STI) const; 338 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, 339 SmallVectorImpl<MCFixup> &Fixups, 340 const MCSubtargetInfo &STI) const; 341 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 342 SmallVectorImpl<MCFixup> &Fixups, 343 const MCSubtargetInfo &STI) const; 344 345 /// getSORegOpValue - Return an encoded so_reg shifted register value. 346 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op, 347 SmallVectorImpl<MCFixup> &Fixups, 348 const MCSubtargetInfo &STI) const; 349 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op, 350 SmallVectorImpl<MCFixup> &Fixups, 351 const MCSubtargetInfo &STI) const; 352 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op, 353 SmallVectorImpl<MCFixup> &Fixups, 354 const MCSubtargetInfo &STI) const; 355 356 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op, 357 SmallVectorImpl<MCFixup> &Fixups, 358 const MCSubtargetInfo &STI) const { 359 return 64 - MI.getOperand(Op).getImm(); 360 } 361 362 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 363 SmallVectorImpl<MCFixup> &Fixups, 364 const MCSubtargetInfo &STI) const; 365 366 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op, 367 SmallVectorImpl<MCFixup> &Fixups, 368 const MCSubtargetInfo &STI) const; 369 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 370 SmallVectorImpl<MCFixup> &Fixups, 371 const MCSubtargetInfo &STI) const; 372 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 373 SmallVectorImpl<MCFixup> &Fixups, 374 const MCSubtargetInfo &STI) const; 375 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 376 SmallVectorImpl<MCFixup> &Fixups, 377 const MCSubtargetInfo &STI) const; 378 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 379 SmallVectorImpl<MCFixup> &Fixups, 380 const MCSubtargetInfo &STI) const; 381 382 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op, 383 SmallVectorImpl<MCFixup> &Fixups, 384 const MCSubtargetInfo &STI) const; 385 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op, 386 SmallVectorImpl<MCFixup> &Fixups, 387 const MCSubtargetInfo &STI) const; 388 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op, 389 SmallVectorImpl<MCFixup> &Fixups, 390 const MCSubtargetInfo &STI) const; 391 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op, 392 SmallVectorImpl<MCFixup> &Fixups, 393 const MCSubtargetInfo &STI) const; 394 395 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op, 396 SmallVectorImpl<MCFixup> &Fixups, 397 const MCSubtargetInfo &STI) const; 398 399 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, 400 unsigned EncodedValue, 401 const MCSubtargetInfo &STI) const; 402 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI, 403 unsigned EncodedValue, 404 const MCSubtargetInfo &STI) const; 405 unsigned NEONThumb2DupPostEncoder(const MCInst &MI, 406 unsigned EncodedValue, 407 const MCSubtargetInfo &STI) const; 408 unsigned NEONThumb2V8PostEncoder(const MCInst &MI, 409 unsigned EncodedValue, 410 const MCSubtargetInfo &STI) const; 411 412 unsigned VFPThumb2PostEncoder(const MCInst &MI, 413 unsigned EncodedValue, 414 const MCSubtargetInfo &STI) const; 415 416 void EmitByte(unsigned char C, raw_ostream &OS) const { 417 OS << (char)C; 418 } 419 420 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const { 421 // Output the constant in little endian byte order. 422 for (unsigned i = 0; i != Size; ++i) { 423 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8; 424 EmitByte((Val >> Shift) & 0xff, OS); 425 } 426 } 427 428 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 429 SmallVectorImpl<MCFixup> &Fixups, 430 const MCSubtargetInfo &STI) const override; 431 }; 432 433 } // end anonymous namespace 434 435 MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII, 436 const MCRegisterInfo &MRI, 437 MCContext &Ctx) { 438 return new ARMMCCodeEmitter(MCII, Ctx, true); 439 } 440 441 MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII, 442 const MCRegisterInfo &MRI, 443 MCContext &Ctx) { 444 return new ARMMCCodeEmitter(MCII, Ctx, false); 445 } 446 447 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing 448 /// instructions, and rewrite them to their Thumb2 form if we are currently in 449 /// Thumb2 mode. 450 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI, 451 unsigned EncodedValue, 452 const MCSubtargetInfo &STI) const { 453 if (isThumb2(STI)) { 454 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved 455 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are 456 // set to 1111. 457 unsigned Bit24 = EncodedValue & 0x01000000; 458 unsigned Bit28 = Bit24 << 4; 459 EncodedValue &= 0xEFFFFFFF; 460 EncodedValue |= Bit28; 461 EncodedValue |= 0x0F000000; 462 } 463 464 return EncodedValue; 465 } 466 467 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store 468 /// instructions, and rewrite them to their Thumb2 form if we are currently in 469 /// Thumb2 mode. 470 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI, 471 unsigned EncodedValue, 472 const MCSubtargetInfo &STI) const { 473 if (isThumb2(STI)) { 474 EncodedValue &= 0xF0FFFFFF; 475 EncodedValue |= 0x09000000; 476 } 477 478 return EncodedValue; 479 } 480 481 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup 482 /// instructions, and rewrite them to their Thumb2 form if we are currently in 483 /// Thumb2 mode. 484 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI, 485 unsigned EncodedValue, 486 const MCSubtargetInfo &STI) const { 487 if (isThumb2(STI)) { 488 EncodedValue &= 0x00FFFFFF; 489 EncodedValue |= 0xEE000000; 490 } 491 492 return EncodedValue; 493 } 494 495 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form 496 /// if we are in Thumb2. 497 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI, 498 unsigned EncodedValue, 499 const MCSubtargetInfo &STI) const { 500 if (isThumb2(STI)) { 501 EncodedValue |= 0xC000000; // Set bits 27-26 502 } 503 504 return EncodedValue; 505 } 506 507 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite 508 /// them to their Thumb2 form if we are currently in Thumb2 mode. 509 unsigned ARMMCCodeEmitter:: 510 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue, 511 const MCSubtargetInfo &STI) const { 512 if (isThumb2(STI)) { 513 EncodedValue &= 0x0FFFFFFF; 514 EncodedValue |= 0xE0000000; 515 } 516 return EncodedValue; 517 } 518 519 /// getMachineOpValue - Return binary encoding of operand. If the machine 520 /// operand requires relocation, record the relocation and return zero. 521 unsigned ARMMCCodeEmitter:: 522 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 523 SmallVectorImpl<MCFixup> &Fixups, 524 const MCSubtargetInfo &STI) const { 525 if (MO.isReg()) { 526 unsigned Reg = MO.getReg(); 527 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); 528 529 // Q registers are encoded as 2x their register number. 530 switch (Reg) { 531 default: 532 return RegNo; 533 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3: 534 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: 535 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11: 536 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15: 537 return 2 * RegNo; 538 } 539 } else if (MO.isImm()) { 540 return static_cast<unsigned>(MO.getImm()); 541 } else if (MO.isFPImm()) { 542 return static_cast<unsigned>(APFloat(MO.getFPImm()) 543 .bitcastToAPInt().getHiBits(32).getLimitedValue()); 544 } 545 546 llvm_unreachable("Unable to encode MCOperand!"); 547 } 548 549 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. 550 bool ARMMCCodeEmitter:: 551 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, 552 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups, 553 const MCSubtargetInfo &STI) const { 554 const MCOperand &MO = MI.getOperand(OpIdx); 555 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 556 557 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 558 559 int32_t SImm = MO1.getImm(); 560 bool isAdd = true; 561 562 // Special value for #-0 563 if (SImm == INT32_MIN) { 564 SImm = 0; 565 isAdd = false; 566 } 567 568 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 569 if (SImm < 0) { 570 SImm = -SImm; 571 isAdd = false; 572 } 573 574 Imm = SImm; 575 return isAdd; 576 } 577 578 /// getBranchTargetOpValue - Helper function to get the branch target operand, 579 /// which is either an immediate or requires a fixup. 580 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 581 unsigned FixupKind, 582 SmallVectorImpl<MCFixup> &Fixups, 583 const MCSubtargetInfo &STI) { 584 const MCOperand &MO = MI.getOperand(OpIdx); 585 586 // If the destination is an immediate, we have nothing to do. 587 if (MO.isImm()) return MO.getImm(); 588 assert(MO.isExpr() && "Unexpected branch target type!"); 589 const MCExpr *Expr = MO.getExpr(); 590 MCFixupKind Kind = MCFixupKind(FixupKind); 591 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 592 593 // All of the information is in the fixup. 594 return 0; 595 } 596 597 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are 598 // determined by negating them and XOR'ing them with bit 23. 599 static int32_t encodeThumbBLOffset(int32_t offset) { 600 offset >>= 1; 601 uint32_t S = (offset & 0x800000) >> 23; 602 uint32_t J1 = (offset & 0x400000) >> 22; 603 uint32_t J2 = (offset & 0x200000) >> 21; 604 J1 = (~J1 & 0x1); 605 J2 = (~J2 & 0x1); 606 J1 ^= S; 607 J2 ^= S; 608 609 offset &= ~0x600000; 610 offset |= J1 << 22; 611 offset |= J2 << 21; 612 613 return offset; 614 } 615 616 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target. 617 uint32_t ARMMCCodeEmitter:: 618 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 619 SmallVectorImpl<MCFixup> &Fixups, 620 const MCSubtargetInfo &STI) const { 621 const MCOperand MO = MI.getOperand(OpIdx); 622 if (MO.isExpr()) 623 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, 624 Fixups, STI); 625 return encodeThumbBLOffset(MO.getImm()); 626 } 627 628 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 629 /// BLX branch target. 630 uint32_t ARMMCCodeEmitter:: 631 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 632 SmallVectorImpl<MCFixup> &Fixups, 633 const MCSubtargetInfo &STI) const { 634 const MCOperand MO = MI.getOperand(OpIdx); 635 if (MO.isExpr()) 636 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, 637 Fixups, STI); 638 return encodeThumbBLOffset(MO.getImm()); 639 } 640 641 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 642 uint32_t ARMMCCodeEmitter:: 643 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 644 SmallVectorImpl<MCFixup> &Fixups, 645 const MCSubtargetInfo &STI) const { 646 const MCOperand MO = MI.getOperand(OpIdx); 647 if (MO.isExpr()) 648 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, 649 Fixups, STI); 650 return (MO.getImm() >> 1); 651 } 652 653 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 654 uint32_t ARMMCCodeEmitter:: 655 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 656 SmallVectorImpl<MCFixup> &Fixups, 657 const MCSubtargetInfo &STI) const { 658 const MCOperand MO = MI.getOperand(OpIdx); 659 if (MO.isExpr()) 660 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, 661 Fixups, STI); 662 return (MO.getImm() >> 1); 663 } 664 665 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 666 uint32_t ARMMCCodeEmitter:: 667 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 668 SmallVectorImpl<MCFixup> &Fixups, 669 const MCSubtargetInfo &STI) const { 670 const MCOperand MO = MI.getOperand(OpIdx); 671 if (MO.isExpr()) 672 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI); 673 return (MO.getImm() >> 1); 674 } 675 676 /// Return true if this branch has a non-always predication 677 static bool HasConditionalBranch(const MCInst &MI) { 678 int NumOp = MI.getNumOperands(); 679 if (NumOp >= 2) { 680 for (int i = 0; i < NumOp-1; ++i) { 681 const MCOperand &MCOp1 = MI.getOperand(i); 682 const MCOperand &MCOp2 = MI.getOperand(i + 1); 683 if (MCOp1.isImm() && MCOp2.isReg() && 684 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) { 685 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL) 686 return true; 687 } 688 } 689 } 690 return false; 691 } 692 693 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 694 /// target. 695 uint32_t ARMMCCodeEmitter:: 696 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 697 SmallVectorImpl<MCFixup> &Fixups, 698 const MCSubtargetInfo &STI) const { 699 // FIXME: This really, really shouldn't use TargetMachine. We don't want 700 // coupling between MC and TM anywhere we can help it. 701 if (isThumb2(STI)) 702 return 703 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI); 704 return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI); 705 } 706 707 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 708 /// target. 709 uint32_t ARMMCCodeEmitter:: 710 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 711 SmallVectorImpl<MCFixup> &Fixups, 712 const MCSubtargetInfo &STI) const { 713 const MCOperand MO = MI.getOperand(OpIdx); 714 if (MO.isExpr()) { 715 if (HasConditionalBranch(MI)) 716 return ::getBranchTargetOpValue(MI, OpIdx, 717 ARM::fixup_arm_condbranch, Fixups, STI); 718 return ::getBranchTargetOpValue(MI, OpIdx, 719 ARM::fixup_arm_uncondbranch, Fixups, STI); 720 } 721 722 return MO.getImm() >> 2; 723 } 724 725 uint32_t ARMMCCodeEmitter:: 726 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 727 SmallVectorImpl<MCFixup> &Fixups, 728 const MCSubtargetInfo &STI) const { 729 const MCOperand MO = MI.getOperand(OpIdx); 730 if (MO.isExpr()) { 731 if (HasConditionalBranch(MI)) 732 return ::getBranchTargetOpValue(MI, OpIdx, 733 ARM::fixup_arm_condbl, Fixups, STI); 734 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI); 735 } 736 737 return MO.getImm() >> 2; 738 } 739 740 uint32_t ARMMCCodeEmitter:: 741 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 742 SmallVectorImpl<MCFixup> &Fixups, 743 const MCSubtargetInfo &STI) const { 744 const MCOperand MO = MI.getOperand(OpIdx); 745 if (MO.isExpr()) 746 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI); 747 748 return MO.getImm() >> 1; 749 } 750 751 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit 752 /// immediate branch target. 753 uint32_t ARMMCCodeEmitter:: 754 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 755 SmallVectorImpl<MCFixup> &Fixups, 756 const MCSubtargetInfo &STI) const { 757 unsigned Val = 0; 758 const MCOperand MO = MI.getOperand(OpIdx); 759 760 if(MO.isExpr()) 761 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI); 762 else 763 Val = MO.getImm() >> 1; 764 765 bool I = (Val & 0x800000); 766 bool J1 = (Val & 0x400000); 767 bool J2 = (Val & 0x200000); 768 if (I ^ J1) 769 Val &= ~0x400000; 770 else 771 Val |= 0x400000; 772 773 if (I ^ J2) 774 Val &= ~0x200000; 775 else 776 Val |= 0x200000; 777 778 return Val; 779 } 780 781 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate 782 /// ADR label target. 783 uint32_t ARMMCCodeEmitter:: 784 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 785 SmallVectorImpl<MCFixup> &Fixups, 786 const MCSubtargetInfo &STI) const { 787 const MCOperand MO = MI.getOperand(OpIdx); 788 if (MO.isExpr()) 789 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12, 790 Fixups, STI); 791 int64_t offset = MO.getImm(); 792 uint32_t Val = 0x2000; 793 794 int SoImmVal; 795 if (offset == INT32_MIN) { 796 Val = 0x1000; 797 SoImmVal = 0; 798 } else if (offset < 0) { 799 Val = 0x1000; 800 offset *= -1; 801 SoImmVal = ARM_AM::getSOImmVal(offset); 802 if(SoImmVal == -1) { 803 Val = 0x2000; 804 offset *= -1; 805 SoImmVal = ARM_AM::getSOImmVal(offset); 806 } 807 } else { 808 SoImmVal = ARM_AM::getSOImmVal(offset); 809 if(SoImmVal == -1) { 810 Val = 0x1000; 811 offset *= -1; 812 SoImmVal = ARM_AM::getSOImmVal(offset); 813 } 814 } 815 816 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 817 818 Val |= SoImmVal; 819 return Val; 820 } 821 822 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label 823 /// target. 824 uint32_t ARMMCCodeEmitter:: 825 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 826 SmallVectorImpl<MCFixup> &Fixups, 827 const MCSubtargetInfo &STI) const { 828 const MCOperand MO = MI.getOperand(OpIdx); 829 if (MO.isExpr()) 830 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12, 831 Fixups, STI); 832 int32_t Val = MO.getImm(); 833 if (Val == INT32_MIN) 834 Val = 0x1000; 835 else if (Val < 0) { 836 Val *= -1; 837 Val |= 0x1000; 838 } 839 return Val; 840 } 841 842 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label 843 /// target. 844 uint32_t ARMMCCodeEmitter:: 845 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 846 SmallVectorImpl<MCFixup> &Fixups, 847 const MCSubtargetInfo &STI) const { 848 const MCOperand MO = MI.getOperand(OpIdx); 849 if (MO.isExpr()) 850 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10, 851 Fixups, STI); 852 return MO.getImm(); 853 } 854 855 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg' 856 /// operand. 857 uint32_t ARMMCCodeEmitter:: 858 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 859 SmallVectorImpl<MCFixup> &, 860 const MCSubtargetInfo &STI) const { 861 // [Rn, Rm] 862 // {5-3} = Rm 863 // {2-0} = Rn 864 const MCOperand &MO1 = MI.getOperand(OpIdx); 865 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); 866 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 867 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); 868 return (Rm << 3) | Rn; 869 } 870 871 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand. 872 uint32_t ARMMCCodeEmitter:: 873 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 874 SmallVectorImpl<MCFixup> &Fixups, 875 const MCSubtargetInfo &STI) const { 876 // {17-13} = reg 877 // {12} = (U)nsigned (add == '1', sub == '0') 878 // {11-0} = imm12 879 unsigned Reg, Imm12; 880 bool isAdd = true; 881 // If The first operand isn't a register, we have a label reference. 882 const MCOperand &MO = MI.getOperand(OpIdx); 883 if (!MO.isReg()) { 884 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 885 Imm12 = 0; 886 887 if (MO.isExpr()) { 888 const MCExpr *Expr = MO.getExpr(); 889 isAdd = false ; // 'U' bit is set as part of the fixup. 890 891 MCFixupKind Kind; 892 if (isThumb2(STI)) 893 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12); 894 else 895 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12); 896 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 897 898 ++MCNumCPRelocations; 899 } else { 900 Reg = ARM::PC; 901 int32_t Offset = MO.getImm(); 902 if (Offset == INT32_MIN) { 903 Offset = 0; 904 isAdd = false; 905 } else if (Offset < 0) { 906 Offset *= -1; 907 isAdd = false; 908 } 909 Imm12 = Offset; 910 } 911 } else 912 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI); 913 914 uint32_t Binary = Imm12 & 0xfff; 915 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 916 if (isAdd) 917 Binary |= (1 << 12); 918 Binary |= (Reg << 13); 919 return Binary; 920 } 921 922 /// getT2Imm8s4OpValue - Return encoding info for 923 /// '+/- imm8<<2' operand. 924 uint32_t ARMMCCodeEmitter:: 925 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, 926 SmallVectorImpl<MCFixup> &Fixups, 927 const MCSubtargetInfo &STI) const { 928 // FIXME: The immediate operand should have already been encoded like this 929 // before ever getting here. The encoder method should just need to combine 930 // the MI operands for the register and the offset into a single 931 // representation for the complex operand in the .td file. This isn't just 932 // style, unfortunately. As-is, we can't represent the distinct encoding 933 // for #-0. 934 935 // {8} = (U)nsigned (add == '1', sub == '0') 936 // {7-0} = imm8 937 int32_t Imm8 = MI.getOperand(OpIdx).getImm(); 938 bool isAdd = Imm8 >= 0; 939 940 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 941 if (Imm8 < 0) 942 Imm8 = -(uint32_t)Imm8; 943 944 // Scaled by 4. 945 Imm8 /= 4; 946 947 uint32_t Binary = Imm8 & 0xff; 948 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 949 if (isAdd) 950 Binary |= (1 << 8); 951 return Binary; 952 } 953 954 /// getT2AddrModeImm8s4OpValue - Return encoding info for 955 /// 'reg +/- imm8<<2' operand. 956 uint32_t ARMMCCodeEmitter:: 957 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 958 SmallVectorImpl<MCFixup> &Fixups, 959 const MCSubtargetInfo &STI) const { 960 // {12-9} = reg 961 // {8} = (U)nsigned (add == '1', sub == '0') 962 // {7-0} = imm8 963 unsigned Reg, Imm8; 964 bool isAdd = true; 965 // If The first operand isn't a register, we have a label reference. 966 const MCOperand &MO = MI.getOperand(OpIdx); 967 if (!MO.isReg()) { 968 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 969 Imm8 = 0; 970 isAdd = false ; // 'U' bit is set as part of the fixup. 971 972 assert(MO.isExpr() && "Unexpected machine operand type!"); 973 const MCExpr *Expr = MO.getExpr(); 974 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); 975 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 976 977 ++MCNumCPRelocations; 978 } else 979 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); 980 981 // FIXME: The immediate operand should have already been encoded like this 982 // before ever getting here. The encoder method should just need to combine 983 // the MI operands for the register and the offset into a single 984 // representation for the complex operand in the .td file. This isn't just 985 // style, unfortunately. As-is, we can't represent the distinct encoding 986 // for #-0. 987 uint32_t Binary = (Imm8 >> 2) & 0xff; 988 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 989 if (isAdd) 990 Binary |= (1 << 8); 991 Binary |= (Reg << 9); 992 return Binary; 993 } 994 995 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 996 /// 'reg + imm8<<2' operand. 997 uint32_t ARMMCCodeEmitter:: 998 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, 999 SmallVectorImpl<MCFixup> &Fixups, 1000 const MCSubtargetInfo &STI) const { 1001 // {11-8} = reg 1002 // {7-0} = imm8 1003 const MCOperand &MO = MI.getOperand(OpIdx); 1004 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1005 unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1006 unsigned Imm8 = MO1.getImm(); 1007 return (Reg << 8) | Imm8; 1008 } 1009 1010 uint32_t 1011 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 1012 SmallVectorImpl<MCFixup> &Fixups, 1013 const MCSubtargetInfo &STI) const { 1014 // {20-16} = imm{15-12} 1015 // {11-0} = imm{11-0} 1016 const MCOperand &MO = MI.getOperand(OpIdx); 1017 if (MO.isImm()) 1018 // Hi / lo 16 bits already extracted during earlier passes. 1019 return static_cast<unsigned>(MO.getImm()); 1020 1021 // Handle :upper16: and :lower16: assembly prefixes. 1022 const MCExpr *E = MO.getExpr(); 1023 MCFixupKind Kind; 1024 if (E->getKind() == MCExpr::Target) { 1025 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E); 1026 E = ARM16Expr->getSubExpr(); 1027 1028 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) { 1029 const int64_t Value = MCE->getValue(); 1030 if (Value > UINT32_MAX) 1031 report_fatal_error("constant value truncated (limited to 32-bit)"); 1032 1033 switch (ARM16Expr->getKind()) { 1034 case ARMMCExpr::VK_ARM_HI16: 1035 return (int32_t(Value) & 0xffff0000) >> 16; 1036 case ARMMCExpr::VK_ARM_LO16: 1037 return (int32_t(Value) & 0x0000ffff); 1038 default: llvm_unreachable("Unsupported ARMFixup"); 1039 } 1040 } 1041 1042 switch (ARM16Expr->getKind()) { 1043 default: llvm_unreachable("Unsupported ARMFixup"); 1044 case ARMMCExpr::VK_ARM_HI16: 1045 Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movt_hi16 1046 : ARM::fixup_arm_movt_hi16); 1047 break; 1048 case ARMMCExpr::VK_ARM_LO16: 1049 Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movw_lo16 1050 : ARM::fixup_arm_movw_lo16); 1051 break; 1052 } 1053 1054 Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc())); 1055 return 0; 1056 } 1057 // If the expression doesn't have :upper16: or :lower16: on it, 1058 // it's just a plain immediate expression, previously those evaluated to 1059 // the lower 16 bits of the expression regardless of whether 1060 // we have a movt or a movw, but that led to misleadingly results. 1061 // This is disallowed in the AsmParser in validateInstruction() 1062 // so this should never happen. 1063 llvm_unreachable("expression without :upper16: or :lower16:"); 1064 } 1065 1066 uint32_t ARMMCCodeEmitter:: 1067 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 1068 SmallVectorImpl<MCFixup> &Fixups, 1069 const MCSubtargetInfo &STI) const { 1070 const MCOperand &MO = MI.getOperand(OpIdx); 1071 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1072 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 1073 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1074 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1075 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); 1076 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; 1077 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); 1078 unsigned SBits = getShiftOp(ShOp); 1079 1080 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift 1081 // amount. However, it would be an easy mistake to make so check here. 1082 assert((ShImm & ~0x1f) == 0 && "Out of range shift amount"); 1083 1084 // {16-13} = Rn 1085 // {12} = isAdd 1086 // {11-0} = shifter 1087 // {3-0} = Rm 1088 // {4} = 0 1089 // {6-5} = type 1090 // {11-7} = imm 1091 uint32_t Binary = Rm; 1092 Binary |= Rn << 13; 1093 Binary |= SBits << 5; 1094 Binary |= ShImm << 7; 1095 if (isAdd) 1096 Binary |= 1 << 12; 1097 return Binary; 1098 } 1099 1100 uint32_t ARMMCCodeEmitter:: 1101 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 1102 SmallVectorImpl<MCFixup> &Fixups, 1103 const MCSubtargetInfo &STI) const { 1104 // {13} 1 == imm12, 0 == Rm 1105 // {12} isAdd 1106 // {11-0} imm12/Rm 1107 const MCOperand &MO = MI.getOperand(OpIdx); 1108 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1109 unsigned Imm = MO1.getImm(); 1110 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add; 1111 bool isReg = MO.getReg() != 0; 1112 uint32_t Binary = ARM_AM::getAM2Offset(Imm); 1113 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12 1114 if (isReg) { 1115 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); 1116 Binary <<= 7; // Shift amount is bits [11:7] 1117 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] 1118 Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0] 1119 } 1120 return Binary | (isAdd << 12) | (isReg << 13); 1121 } 1122 1123 uint32_t ARMMCCodeEmitter:: 1124 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 1125 SmallVectorImpl<MCFixup> &Fixups, 1126 const MCSubtargetInfo &STI) const { 1127 // {4} isAdd 1128 // {3-0} Rm 1129 const MCOperand &MO = MI.getOperand(OpIdx); 1130 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1131 bool isAdd = MO1.getImm() != 0; 1132 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4); 1133 } 1134 1135 uint32_t ARMMCCodeEmitter:: 1136 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 1137 SmallVectorImpl<MCFixup> &Fixups, 1138 const MCSubtargetInfo &STI) const { 1139 // {9} 1 == imm8, 0 == Rm 1140 // {8} isAdd 1141 // {7-4} imm7_4/zero 1142 // {3-0} imm3_0/Rm 1143 const MCOperand &MO = MI.getOperand(OpIdx); 1144 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1145 unsigned Imm = MO1.getImm(); 1146 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 1147 bool isImm = MO.getReg() == 0; 1148 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 1149 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 1150 if (!isImm) 1151 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1152 return Imm8 | (isAdd << 8) | (isImm << 9); 1153 } 1154 1155 uint32_t ARMMCCodeEmitter:: 1156 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 1157 SmallVectorImpl<MCFixup> &Fixups, 1158 const MCSubtargetInfo &STI) const { 1159 // {13} 1 == imm8, 0 == Rm 1160 // {12-9} Rn 1161 // {8} isAdd 1162 // {7-4} imm7_4/zero 1163 // {3-0} imm3_0/Rm 1164 const MCOperand &MO = MI.getOperand(OpIdx); 1165 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1166 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 1167 1168 // If The first operand isn't a register, we have a label reference. 1169 if (!MO.isReg()) { 1170 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 1171 1172 assert(MO.isExpr() && "Unexpected machine operand type!"); 1173 const MCExpr *Expr = MO.getExpr(); 1174 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled); 1175 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 1176 1177 ++MCNumCPRelocations; 1178 return (Rn << 9) | (1 << 13); 1179 } 1180 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1181 unsigned Imm = MO2.getImm(); 1182 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 1183 bool isImm = MO1.getReg() == 0; 1184 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 1185 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 1186 if (!isImm) 1187 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1188 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13); 1189 } 1190 1191 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands. 1192 uint32_t ARMMCCodeEmitter:: 1193 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 1194 SmallVectorImpl<MCFixup> &Fixups, 1195 const MCSubtargetInfo &STI) const { 1196 // [SP, #imm] 1197 // {7-0} = imm8 1198 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1199 assert(MI.getOperand(OpIdx).getReg() == ARM::SP && 1200 "Unexpected base register!"); 1201 1202 // The immediate is already shifted for the implicit zeroes, so no change 1203 // here. 1204 return MO1.getImm() & 0xff; 1205 } 1206 1207 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 1208 uint32_t ARMMCCodeEmitter:: 1209 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 1210 SmallVectorImpl<MCFixup> &Fixups, 1211 const MCSubtargetInfo &STI) const { 1212 // [Rn, #imm] 1213 // {7-3} = imm5 1214 // {2-0} = Rn 1215 const MCOperand &MO = MI.getOperand(OpIdx); 1216 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1217 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1218 unsigned Imm5 = MO1.getImm(); 1219 return ((Imm5 & 0x1f) << 3) | Rn; 1220 } 1221 1222 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 1223 uint32_t ARMMCCodeEmitter:: 1224 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 1225 SmallVectorImpl<MCFixup> &Fixups, 1226 const MCSubtargetInfo &STI) const { 1227 const MCOperand MO = MI.getOperand(OpIdx); 1228 if (MO.isExpr()) 1229 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI); 1230 return (MO.getImm() >> 2); 1231 } 1232 1233 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand. 1234 uint32_t ARMMCCodeEmitter:: 1235 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 1236 SmallVectorImpl<MCFixup> &Fixups, 1237 const MCSubtargetInfo &STI) const { 1238 // {12-9} = reg 1239 // {8} = (U)nsigned (add == '1', sub == '0') 1240 // {7-0} = imm8 1241 unsigned Reg, Imm8; 1242 bool isAdd; 1243 // If The first operand isn't a register, we have a label reference. 1244 const MCOperand &MO = MI.getOperand(OpIdx); 1245 if (!MO.isReg()) { 1246 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 1247 Imm8 = 0; 1248 isAdd = false; // 'U' bit is handled as part of the fixup. 1249 1250 assert(MO.isExpr() && "Unexpected machine operand type!"); 1251 const MCExpr *Expr = MO.getExpr(); 1252 MCFixupKind Kind; 1253 if (isThumb2(STI)) 1254 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); 1255 else 1256 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10); 1257 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 1258 1259 ++MCNumCPRelocations; 1260 } else { 1261 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); 1262 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add; 1263 } 1264 1265 uint32_t Binary = ARM_AM::getAM5Offset(Imm8); 1266 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1267 if (isAdd) 1268 Binary |= (1 << 8); 1269 Binary |= (Reg << 9); 1270 return Binary; 1271 } 1272 1273 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand. 1274 uint32_t ARMMCCodeEmitter:: 1275 getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx, 1276 SmallVectorImpl<MCFixup> &Fixups, 1277 const MCSubtargetInfo &STI) const { 1278 // {12-9} = reg 1279 // {8} = (U)nsigned (add == '1', sub == '0') 1280 // {7-0} = imm8 1281 unsigned Reg, Imm8; 1282 bool isAdd; 1283 // If The first operand isn't a register, we have a label reference. 1284 const MCOperand &MO = MI.getOperand(OpIdx); 1285 if (!MO.isReg()) { 1286 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 1287 Imm8 = 0; 1288 isAdd = false; // 'U' bit is handled as part of the fixup. 1289 1290 assert(MO.isExpr() && "Unexpected machine operand type!"); 1291 const MCExpr *Expr = MO.getExpr(); 1292 MCFixupKind Kind; 1293 if (isThumb2(STI)) 1294 Kind = MCFixupKind(ARM::fixup_t2_pcrel_9); 1295 else 1296 Kind = MCFixupKind(ARM::fixup_arm_pcrel_9); 1297 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 1298 1299 ++MCNumCPRelocations; 1300 } else { 1301 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); 1302 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add; 1303 } 1304 1305 uint32_t Binary = ARM_AM::getAM5Offset(Imm8); 1306 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1307 if (isAdd) 1308 Binary |= (1 << 8); 1309 Binary |= (Reg << 9); 1310 return Binary; 1311 } 1312 1313 unsigned ARMMCCodeEmitter:: 1314 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, 1315 SmallVectorImpl<MCFixup> &Fixups, 1316 const MCSubtargetInfo &STI) const { 1317 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be 1318 // shifted. The second is Rs, the amount to shift by, and the third specifies 1319 // the type of the shift. 1320 // 1321 // {3-0} = Rm. 1322 // {4} = 1 1323 // {6-5} = type 1324 // {11-8} = Rs 1325 // {7} = 0 1326 1327 const MCOperand &MO = MI.getOperand(OpIdx); 1328 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1329 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); 1330 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 1331 1332 // Encode Rm. 1333 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1334 1335 // Encode the shift opcode. 1336 unsigned SBits = 0; 1337 unsigned Rs = MO1.getReg(); 1338 if (Rs) { 1339 // Set shift operand (bit[7:4]). 1340 // LSL - 0001 1341 // LSR - 0011 1342 // ASR - 0101 1343 // ROR - 0111 1344 switch (SOpc) { 1345 default: llvm_unreachable("Unknown shift opc!"); 1346 case ARM_AM::lsl: SBits = 0x1; break; 1347 case ARM_AM::lsr: SBits = 0x3; break; 1348 case ARM_AM::asr: SBits = 0x5; break; 1349 case ARM_AM::ror: SBits = 0x7; break; 1350 } 1351 } 1352 1353 Binary |= SBits << 4; 1354 1355 // Encode the shift operation Rs. 1356 // Encode Rs bit[11:8]. 1357 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 1358 return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift); 1359 } 1360 1361 unsigned ARMMCCodeEmitter:: 1362 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, 1363 SmallVectorImpl<MCFixup> &Fixups, 1364 const MCSubtargetInfo &STI) const { 1365 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 1366 // shifted. The second is the amount to shift by. 1367 // 1368 // {3-0} = Rm. 1369 // {4} = 0 1370 // {6-5} = type 1371 // {11-7} = imm 1372 1373 const MCOperand &MO = MI.getOperand(OpIdx); 1374 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1375 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 1376 1377 // Encode Rm. 1378 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1379 1380 // Encode the shift opcode. 1381 unsigned SBits = 0; 1382 1383 // Set shift operand (bit[6:4]). 1384 // LSL - 000 1385 // LSR - 010 1386 // ASR - 100 1387 // ROR - 110 1388 // RRX - 110 and bit[11:8] clear. 1389 switch (SOpc) { 1390 default: llvm_unreachable("Unknown shift opc!"); 1391 case ARM_AM::lsl: SBits = 0x0; break; 1392 case ARM_AM::lsr: SBits = 0x2; break; 1393 case ARM_AM::asr: SBits = 0x4; break; 1394 case ARM_AM::ror: SBits = 0x6; break; 1395 case ARM_AM::rrx: 1396 Binary |= 0x60; 1397 return Binary; 1398 } 1399 1400 // Encode shift_imm bit[11:7]. 1401 Binary |= SBits << 4; 1402 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm()); 1403 assert(Offset < 32 && "Offset must be in range 0-31!"); 1404 return Binary | (Offset << 7); 1405 } 1406 1407 1408 unsigned ARMMCCodeEmitter:: 1409 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 1410 SmallVectorImpl<MCFixup> &Fixups, 1411 const MCSubtargetInfo &STI) const { 1412 const MCOperand &MO1 = MI.getOperand(OpNum); 1413 const MCOperand &MO2 = MI.getOperand(OpNum+1); 1414 const MCOperand &MO3 = MI.getOperand(OpNum+2); 1415 1416 // Encoded as [Rn, Rm, imm]. 1417 // FIXME: Needs fixup support. 1418 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1419 Value <<= 4; 1420 Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); 1421 Value <<= 2; 1422 Value |= MO3.getImm(); 1423 1424 return Value; 1425 } 1426 1427 unsigned ARMMCCodeEmitter:: 1428 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, 1429 SmallVectorImpl<MCFixup> &Fixups, 1430 const MCSubtargetInfo &STI) const { 1431 const MCOperand &MO1 = MI.getOperand(OpNum); 1432 const MCOperand &MO2 = MI.getOperand(OpNum+1); 1433 1434 // FIXME: Needs fixup support. 1435 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1436 1437 // Even though the immediate is 8 bits long, we need 9 bits in order 1438 // to represent the (inverse of the) sign bit. 1439 Value <<= 9; 1440 int32_t tmp = (int32_t)MO2.getImm(); 1441 if (tmp < 0) 1442 tmp = abs(tmp); 1443 else 1444 Value |= 256; // Set the ADD bit 1445 Value |= tmp & 255; 1446 return Value; 1447 } 1448 1449 unsigned ARMMCCodeEmitter:: 1450 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 1451 SmallVectorImpl<MCFixup> &Fixups, 1452 const MCSubtargetInfo &STI) const { 1453 const MCOperand &MO1 = MI.getOperand(OpNum); 1454 1455 // FIXME: Needs fixup support. 1456 unsigned Value = 0; 1457 int32_t tmp = (int32_t)MO1.getImm(); 1458 if (tmp < 0) 1459 tmp = abs(tmp); 1460 else 1461 Value |= 256; // Set the ADD bit 1462 Value |= tmp & 255; 1463 return Value; 1464 } 1465 1466 unsigned ARMMCCodeEmitter:: 1467 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx, 1468 SmallVectorImpl<MCFixup> &Fixups, 1469 const MCSubtargetInfo &STI) const { 1470 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 1471 // shifted. The second is the amount to shift by. 1472 // 1473 // {3-0} = Rm. 1474 // {4} = 0 1475 // {6-5} = type 1476 // {11-7} = imm 1477 1478 const MCOperand &MO = MI.getOperand(OpIdx); 1479 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1480 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 1481 1482 // Encode Rm. 1483 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1484 1485 // Encode the shift opcode. 1486 unsigned SBits = 0; 1487 // Set shift operand (bit[6:4]). 1488 // LSL - 000 1489 // LSR - 010 1490 // ASR - 100 1491 // ROR - 110 1492 switch (SOpc) { 1493 default: llvm_unreachable("Unknown shift opc!"); 1494 case ARM_AM::lsl: SBits = 0x0; break; 1495 case ARM_AM::lsr: SBits = 0x2; break; 1496 case ARM_AM::asr: SBits = 0x4; break; 1497 case ARM_AM::rrx: // FALLTHROUGH 1498 case ARM_AM::ror: SBits = 0x6; break; 1499 } 1500 1501 Binary |= SBits << 4; 1502 if (SOpc == ARM_AM::rrx) 1503 return Binary; 1504 1505 // Encode shift_imm bit[11:7]. 1506 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7; 1507 } 1508 1509 unsigned ARMMCCodeEmitter:: 1510 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 1511 SmallVectorImpl<MCFixup> &Fixups, 1512 const MCSubtargetInfo &STI) const { 1513 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the 1514 // msb of the mask. 1515 const MCOperand &MO = MI.getOperand(Op); 1516 uint32_t v = ~MO.getImm(); 1517 uint32_t lsb = countTrailingZeros(v); 1518 uint32_t msb = (32 - countLeadingZeros (v)) - 1; 1519 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!"); 1520 return lsb | (msb << 5); 1521 } 1522 1523 unsigned ARMMCCodeEmitter:: 1524 getRegisterListOpValue(const MCInst &MI, unsigned Op, 1525 SmallVectorImpl<MCFixup> &Fixups, 1526 const MCSubtargetInfo &STI) const { 1527 // VLDM/VSTM: 1528 // {12-8} = Vd 1529 // {7-0} = Number of registers 1530 // 1531 // LDM/STM: 1532 // {15-0} = Bitfield of GPRs. 1533 unsigned Reg = MI.getOperand(Op).getReg(); 1534 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg); 1535 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg); 1536 1537 unsigned Binary = 0; 1538 1539 if (SPRRegs || DPRRegs) { 1540 // VLDM/VSTM 1541 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); 1542 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff; 1543 Binary |= (RegNo & 0x1f) << 8; 1544 if (SPRRegs) 1545 Binary |= NumRegs; 1546 else 1547 Binary |= NumRegs * 2; 1548 } else { 1549 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) { 1550 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(MI.getOperand(I).getReg()); 1551 Binary |= 1 << RegNo; 1552 } 1553 } 1554 1555 return Binary; 1556 } 1557 1558 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along 1559 /// with the alignment operand. 1560 unsigned ARMMCCodeEmitter:: 1561 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 1562 SmallVectorImpl<MCFixup> &Fixups, 1563 const MCSubtargetInfo &STI) const { 1564 const MCOperand &Reg = MI.getOperand(Op); 1565 const MCOperand &Imm = MI.getOperand(Op + 1); 1566 1567 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg()); 1568 unsigned Align = 0; 1569 1570 switch (Imm.getImm()) { 1571 default: break; 1572 case 2: 1573 case 4: 1574 case 8: Align = 0x01; break; 1575 case 16: Align = 0x02; break; 1576 case 32: Align = 0x03; break; 1577 } 1578 1579 return RegNo | (Align << 4); 1580 } 1581 1582 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number 1583 /// along with the alignment operand for use in VST1 and VLD1 with size 32. 1584 unsigned ARMMCCodeEmitter:: 1585 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 1586 SmallVectorImpl<MCFixup> &Fixups, 1587 const MCSubtargetInfo &STI) const { 1588 const MCOperand &Reg = MI.getOperand(Op); 1589 const MCOperand &Imm = MI.getOperand(Op + 1); 1590 1591 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg()); 1592 unsigned Align = 0; 1593 1594 switch (Imm.getImm()) { 1595 default: break; 1596 case 8: 1597 case 16: 1598 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes. 1599 case 2: Align = 0x00; break; 1600 case 4: Align = 0x03; break; 1601 } 1602 1603 return RegNo | (Align << 4); 1604 } 1605 1606 1607 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and 1608 /// alignment operand for use in VLD-dup instructions. This is the same as 1609 /// getAddrMode6AddressOpValue except for the alignment encoding, which is 1610 /// different for VLD4-dup. 1611 unsigned ARMMCCodeEmitter:: 1612 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 1613 SmallVectorImpl<MCFixup> &Fixups, 1614 const MCSubtargetInfo &STI) const { 1615 const MCOperand &Reg = MI.getOperand(Op); 1616 const MCOperand &Imm = MI.getOperand(Op + 1); 1617 1618 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg()); 1619 unsigned Align = 0; 1620 1621 switch (Imm.getImm()) { 1622 default: break; 1623 case 2: 1624 case 4: 1625 case 8: Align = 0x01; break; 1626 case 16: Align = 0x03; break; 1627 } 1628 1629 return RegNo | (Align << 4); 1630 } 1631 1632 unsigned ARMMCCodeEmitter:: 1633 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 1634 SmallVectorImpl<MCFixup> &Fixups, 1635 const MCSubtargetInfo &STI) const { 1636 const MCOperand &MO = MI.getOperand(Op); 1637 if (MO.getReg() == 0) return 0x0D; 1638 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1639 } 1640 1641 unsigned ARMMCCodeEmitter:: 1642 getShiftRight8Imm(const MCInst &MI, unsigned Op, 1643 SmallVectorImpl<MCFixup> &Fixups, 1644 const MCSubtargetInfo &STI) const { 1645 return 8 - MI.getOperand(Op).getImm(); 1646 } 1647 1648 unsigned ARMMCCodeEmitter:: 1649 getShiftRight16Imm(const MCInst &MI, unsigned Op, 1650 SmallVectorImpl<MCFixup> &Fixups, 1651 const MCSubtargetInfo &STI) const { 1652 return 16 - MI.getOperand(Op).getImm(); 1653 } 1654 1655 unsigned ARMMCCodeEmitter:: 1656 getShiftRight32Imm(const MCInst &MI, unsigned Op, 1657 SmallVectorImpl<MCFixup> &Fixups, 1658 const MCSubtargetInfo &STI) const { 1659 return 32 - MI.getOperand(Op).getImm(); 1660 } 1661 1662 unsigned ARMMCCodeEmitter:: 1663 getShiftRight64Imm(const MCInst &MI, unsigned Op, 1664 SmallVectorImpl<MCFixup> &Fixups, 1665 const MCSubtargetInfo &STI) const { 1666 return 64 - MI.getOperand(Op).getImm(); 1667 } 1668 1669 void ARMMCCodeEmitter:: 1670 encodeInstruction(const MCInst &MI, raw_ostream &OS, 1671 SmallVectorImpl<MCFixup> &Fixups, 1672 const MCSubtargetInfo &STI) const { 1673 // Pseudo instructions don't get encoded. 1674 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 1675 uint64_t TSFlags = Desc.TSFlags; 1676 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo) 1677 return; 1678 1679 int Size; 1680 if (Desc.getSize() == 2 || Desc.getSize() == 4) 1681 Size = Desc.getSize(); 1682 else 1683 llvm_unreachable("Unexpected instruction size!"); 1684 1685 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI); 1686 // Thumb 32-bit wide instructions need to emit the high order halfword 1687 // first. 1688 if (isThumb(STI) && Size == 4) { 1689 EmitConstant(Binary >> 16, 2, OS); 1690 EmitConstant(Binary & 0xffff, 2, OS); 1691 } else 1692 EmitConstant(Binary, Size, OS); 1693 ++MCNumEmitted; // Keep track of the # of mi's emitted. 1694 } 1695 1696 #include "ARMGenMCCodeEmitter.inc" 1697