1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARMMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MCTargetDesc/ARMMCTargetDesc.h"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMFixupKinds.h"
18 #include "MCTargetDesc/ARMMCExpr.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/MC/MCCodeEmitter.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCExpr.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/raw_ostream.h"
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "mccodeemitter"
34 
35 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
36 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
37 
38 namespace {
39 class ARMMCCodeEmitter : public MCCodeEmitter {
40   ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete;
41   void operator=(const ARMMCCodeEmitter &) = delete;
42   const MCInstrInfo &MCII;
43   const MCContext &CTX;
44   bool IsLittleEndian;
45 
46 public:
47   ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle)
48     : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
49   }
50 
51   ~ARMMCCodeEmitter() override {}
52 
53   bool isThumb(const MCSubtargetInfo &STI) const {
54     return STI.getFeatureBits()[ARM::ModeThumb];
55   }
56   bool isThumb2(const MCSubtargetInfo &STI) const {
57     return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
58   }
59   bool isTargetMachO(const MCSubtargetInfo &STI) const {
60     const Triple &TT = STI.getTargetTriple();
61     return TT.isOSBinFormatMachO();
62   }
63 
64   unsigned getMachineSoImmOpValue(unsigned SoImm) const;
65 
66   // getBinaryCodeForInstr - TableGen'erated function for getting the
67   // binary encoding for an instruction.
68   uint64_t getBinaryCodeForInstr(const MCInst &MI,
69                                  SmallVectorImpl<MCFixup> &Fixups,
70                                  const MCSubtargetInfo &STI) const;
71 
72   /// getMachineOpValue - Return binary encoding of operand. If the machine
73   /// operand requires relocation, record the relocation and return zero.
74   unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
75                              SmallVectorImpl<MCFixup> &Fixups,
76                              const MCSubtargetInfo &STI) const;
77 
78   /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
79   /// the specified operand. This is used for operands with :lower16: and
80   /// :upper16: prefixes.
81   uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
82                                SmallVectorImpl<MCFixup> &Fixups,
83                                const MCSubtargetInfo &STI) const;
84 
85   bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
86                               unsigned &Reg, unsigned &Imm,
87                               SmallVectorImpl<MCFixup> &Fixups,
88                               const MCSubtargetInfo &STI) const;
89 
90   /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
91   /// BL branch target.
92   uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
93                                    SmallVectorImpl<MCFixup> &Fixups,
94                                    const MCSubtargetInfo &STI) const;
95 
96   /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
97   /// BLX branch target.
98   uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
99                                     SmallVectorImpl<MCFixup> &Fixups,
100                                     const MCSubtargetInfo &STI) const;
101 
102   /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
103   uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
104                                    SmallVectorImpl<MCFixup> &Fixups,
105                                    const MCSubtargetInfo &STI) const;
106 
107   /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
108   uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
109                                     SmallVectorImpl<MCFixup> &Fixups,
110                                     const MCSubtargetInfo &STI) const;
111 
112   /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
113   uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
114                                    SmallVectorImpl<MCFixup> &Fixups,
115                                    const MCSubtargetInfo &STI) const;
116 
117   /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
118   /// branch target.
119   uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
120                                   SmallVectorImpl<MCFixup> &Fixups,
121                                   const MCSubtargetInfo &STI) const;
122 
123   /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
124   /// immediate Thumb2 direct branch target.
125   uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
126                                   SmallVectorImpl<MCFixup> &Fixups,
127                                   const MCSubtargetInfo &STI) const;
128 
129   /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
130   /// branch target.
131   uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
132                                      SmallVectorImpl<MCFixup> &Fixups,
133                                      const MCSubtargetInfo &STI) const;
134   uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
135                                  SmallVectorImpl<MCFixup> &Fixups,
136                                  const MCSubtargetInfo &STI) const;
137   uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
138                                   SmallVectorImpl<MCFixup> &Fixups,
139                                   const MCSubtargetInfo &STI) const;
140 
141   /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
142   /// ADR label target.
143   uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
144                               SmallVectorImpl<MCFixup> &Fixups,
145                               const MCSubtargetInfo &STI) const;
146   uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
147                               SmallVectorImpl<MCFixup> &Fixups,
148                               const MCSubtargetInfo &STI) const;
149   uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
150                               SmallVectorImpl<MCFixup> &Fixups,
151                               const MCSubtargetInfo &STI) const;
152 
153 
154   /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
155   /// operand.
156   uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
157                                    SmallVectorImpl<MCFixup> &Fixups,
158                                    const MCSubtargetInfo &STI) const;
159 
160   /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
161   uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
162                                          SmallVectorImpl<MCFixup> &Fixups,
163                                          const MCSubtargetInfo &STI) const;
164 
165   /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
166   /// operand.
167   uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
168                                    SmallVectorImpl<MCFixup> &Fixups,
169                                    const MCSubtargetInfo &STI) const;
170 
171   /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
172   /// operand.
173   uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
174                                    SmallVectorImpl<MCFixup> &Fixups,
175                                    const MCSubtargetInfo &STI) const;
176 
177   /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
178   /// operand.
179   uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
180                               SmallVectorImpl<MCFixup> &Fixups,
181                               const MCSubtargetInfo &STI) const;
182 
183 
184   /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
185   /// operand as needed by load/store instructions.
186   uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
187                                SmallVectorImpl<MCFixup> &Fixups,
188                                const MCSubtargetInfo &STI) const;
189 
190   /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
191   uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
192                                SmallVectorImpl<MCFixup> &Fixups,
193                                const MCSubtargetInfo &STI) const {
194     ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
195     switch (Mode) {
196     default: llvm_unreachable("Unknown addressing sub-mode!");
197     case ARM_AM::da: return 0;
198     case ARM_AM::ia: return 1;
199     case ARM_AM::db: return 2;
200     case ARM_AM::ib: return 3;
201     }
202   }
203   /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
204   ///
205   unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
206     switch (ShOpc) {
207     case ARM_AM::no_shift:
208     case ARM_AM::lsl: return 0;
209     case ARM_AM::lsr: return 1;
210     case ARM_AM::asr: return 2;
211     case ARM_AM::ror:
212     case ARM_AM::rrx: return 3;
213     }
214     llvm_unreachable("Invalid ShiftOpc!");
215   }
216 
217   /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
218   uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
219                                SmallVectorImpl<MCFixup> &Fixups,
220                                const MCSubtargetInfo &STI) const;
221 
222   /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
223   uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
224                                      SmallVectorImpl<MCFixup> &Fixups,
225                                      const MCSubtargetInfo &STI) const;
226 
227   /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
228   uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
229                                 SmallVectorImpl<MCFixup> &Fixups,
230                                 const MCSubtargetInfo &STI) const;
231 
232   /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
233   uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
234                                      SmallVectorImpl<MCFixup> &Fixups,
235                                      const MCSubtargetInfo &STI) const;
236 
237   /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
238   uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
239                                SmallVectorImpl<MCFixup> &Fixups,
240                                const MCSubtargetInfo &STI) const;
241 
242   /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
243   /// operand.
244   uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
245                                      SmallVectorImpl<MCFixup> &Fixups,
246                                      const MCSubtargetInfo &STI) const;
247 
248   /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
249   uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
250                                 SmallVectorImpl<MCFixup> &Fixups,
251                                 const MCSubtargetInfo &STI) const;
252 
253   /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
254   uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
255                                 SmallVectorImpl<MCFixup> &Fixups,
256                                 const MCSubtargetInfo &STI) const;
257 
258   /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
259   uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
260                                SmallVectorImpl<MCFixup> &Fixups,
261                                const MCSubtargetInfo &STI) const;
262 
263   /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
264   uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
265                                SmallVectorImpl<MCFixup> &Fixups,
266                                const MCSubtargetInfo &STI) const;
267 
268   /// getCCOutOpValue - Return encoding of the 's' bit.
269   unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
270                            SmallVectorImpl<MCFixup> &Fixups,
271                            const MCSubtargetInfo &STI) const {
272     // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
273     // '1' respectively.
274     return MI.getOperand(Op).getReg() == ARM::CPSR;
275   }
276 
277   /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
278   unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
279                            SmallVectorImpl<MCFixup> &Fixups,
280                            const MCSubtargetInfo &STI) const {
281 
282     const MCOperand &MO = MI.getOperand(Op);
283 
284     // We expect MO to be an immediate or an expression,
285     // if it is an immediate - that's fine, just encode the value.
286     // Otherwise - create a Fixup.
287     if (MO.isExpr()) {
288       const MCExpr *Expr = MO.getExpr();
289       // In instruction code this value always encoded as lowest 12 bits,
290       // so we don't have to perform any specific adjustments.
291       // Due to requirements of relocatable records we have to use FK_Data_4.
292       // See ARMELFObjectWriter::ExplicitRelSym and
293       //     ARMELFObjectWriter::GetRelocTypeInner for more details.
294       MCFixupKind Kind = MCFixupKind(FK_Data_4);
295       Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
296       return 0;
297     }
298 
299     unsigned SoImm = MO.getImm();
300     int SoImmVal = ARM_AM::getSOImmVal(SoImm);
301     assert(SoImmVal != -1 && "Not a valid so_imm value!");
302 
303     // Encode rotate_imm.
304     unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
305       << ARMII::SoRotImmShift;
306 
307     // Encode immed_8.
308     Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
309     return Binary;
310   }
311 
312   unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
313                             SmallVectorImpl<MCFixup> &Fixups,
314                             const MCSubtargetInfo &ST) const {
315     const MCOperand &MO = MI.getOperand(Op);
316 
317     // Support for fixups (MCFixup)
318     if (MO.isExpr()) {
319       const MCExpr *Expr = MO.getExpr();
320       // In instruction code this value always encoded as lowest 12 bits,
321       // so we don't have to perform any specific adjustments.
322       // Due to requirements of relocatable records we have to use FK_Data_4.
323       // See ARMELFObjectWriter::ExplicitRelSym and
324       //     ARMELFObjectWriter::GetRelocTypeInner for more details.
325       MCFixupKind Kind = MCFixupKind(FK_Data_4);
326       Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
327       return 0;
328     }
329 
330     // Immediate is already in its encoded format
331     return MO.getImm();
332   }
333 
334   /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
335   unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
336                            SmallVectorImpl<MCFixup> &Fixups,
337                            const MCSubtargetInfo &STI) const {
338     unsigned SoImm = MI.getOperand(Op).getImm();
339     unsigned Encoded =  ARM_AM::getT2SOImmVal(SoImm);
340     assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
341     return Encoded;
342   }
343 
344   unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
345     SmallVectorImpl<MCFixup> &Fixups,
346     const MCSubtargetInfo &STI) const;
347   unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
348     SmallVectorImpl<MCFixup> &Fixups,
349     const MCSubtargetInfo &STI) const;
350   unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
351     SmallVectorImpl<MCFixup> &Fixups,
352     const MCSubtargetInfo &STI) const;
353   unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
354     SmallVectorImpl<MCFixup> &Fixups,
355     const MCSubtargetInfo &STI) const;
356 
357   /// getSORegOpValue - Return an encoded so_reg shifted register value.
358   unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
359                            SmallVectorImpl<MCFixup> &Fixups,
360                            const MCSubtargetInfo &STI) const;
361   unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
362                            SmallVectorImpl<MCFixup> &Fixups,
363                            const MCSubtargetInfo &STI) const;
364   unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
365                              SmallVectorImpl<MCFixup> &Fixups,
366                              const MCSubtargetInfo &STI) const;
367 
368   unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
369                                    SmallVectorImpl<MCFixup> &Fixups,
370                                    const MCSubtargetInfo &STI) const {
371     return 64 - MI.getOperand(Op).getImm();
372   }
373 
374   unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
375                                       SmallVectorImpl<MCFixup> &Fixups,
376                                       const MCSubtargetInfo &STI) const;
377 
378   unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
379                                   SmallVectorImpl<MCFixup> &Fixups,
380                                   const MCSubtargetInfo &STI) const;
381   unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
382                                       SmallVectorImpl<MCFixup> &Fixups,
383                                       const MCSubtargetInfo &STI) const;
384   unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
385                                         SmallVectorImpl<MCFixup> &Fixups,
386                                         const MCSubtargetInfo &STI) const;
387   unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
388                                         SmallVectorImpl<MCFixup> &Fixups,
389                                         const MCSubtargetInfo &STI) const;
390   unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
391                                      SmallVectorImpl<MCFixup> &Fixups,
392                                      const MCSubtargetInfo &STI) const;
393 
394   unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
395                              SmallVectorImpl<MCFixup> &Fixups,
396                              const MCSubtargetInfo &STI) const;
397   unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
398                               SmallVectorImpl<MCFixup> &Fixups,
399                               const MCSubtargetInfo &STI) const;
400   unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
401                               SmallVectorImpl<MCFixup> &Fixups,
402                               const MCSubtargetInfo &STI) const;
403   unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
404                               SmallVectorImpl<MCFixup> &Fixups,
405                               const MCSubtargetInfo &STI) const;
406 
407   unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
408                                  SmallVectorImpl<MCFixup> &Fixups,
409                                  const MCSubtargetInfo &STI) const;
410 
411   unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
412                                       unsigned EncodedValue,
413                                       const MCSubtargetInfo &STI) const;
414   unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
415                                           unsigned EncodedValue,
416                                           const MCSubtargetInfo &STI) const;
417   unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
418                                     unsigned EncodedValue,
419                                     const MCSubtargetInfo &STI) const;
420   unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
421                                    unsigned EncodedValue,
422                                    const MCSubtargetInfo &STI) const;
423 
424   unsigned VFPThumb2PostEncoder(const MCInst &MI,
425                                 unsigned EncodedValue,
426                                 const MCSubtargetInfo &STI) const;
427 
428   void EmitByte(unsigned char C, raw_ostream &OS) const {
429     OS << (char)C;
430   }
431 
432   void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
433     // Output the constant in little endian byte order.
434     for (unsigned i = 0; i != Size; ++i) {
435       unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
436       EmitByte((Val >> Shift) & 0xff, OS);
437     }
438   }
439 
440   void encodeInstruction(const MCInst &MI, raw_ostream &OS,
441                          SmallVectorImpl<MCFixup> &Fixups,
442                          const MCSubtargetInfo &STI) const override;
443 };
444 
445 } // end anonymous namespace
446 
447 MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
448                                               const MCRegisterInfo &MRI,
449                                               MCContext &Ctx) {
450   return new ARMMCCodeEmitter(MCII, Ctx, true);
451 }
452 
453 MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
454                                               const MCRegisterInfo &MRI,
455                                               MCContext &Ctx) {
456   return new ARMMCCodeEmitter(MCII, Ctx, false);
457 }
458 
459 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
460 /// instructions, and rewrite them to their Thumb2 form if we are currently in
461 /// Thumb2 mode.
462 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
463                                                  unsigned EncodedValue,
464                                                  const MCSubtargetInfo &STI) const {
465   if (isThumb2(STI)) {
466     // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
467     // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
468     // set to 1111.
469     unsigned Bit24 = EncodedValue & 0x01000000;
470     unsigned Bit28 = Bit24 << 4;
471     EncodedValue &= 0xEFFFFFFF;
472     EncodedValue |= Bit28;
473     EncodedValue |= 0x0F000000;
474   }
475 
476   return EncodedValue;
477 }
478 
479 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
480 /// instructions, and rewrite them to their Thumb2 form if we are currently in
481 /// Thumb2 mode.
482 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
483                                                  unsigned EncodedValue,
484                                                  const MCSubtargetInfo &STI) const {
485   if (isThumb2(STI)) {
486     EncodedValue &= 0xF0FFFFFF;
487     EncodedValue |= 0x09000000;
488   }
489 
490   return EncodedValue;
491 }
492 
493 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
494 /// instructions, and rewrite them to their Thumb2 form if we are currently in
495 /// Thumb2 mode.
496 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
497                                                  unsigned EncodedValue,
498                                                  const MCSubtargetInfo &STI) const {
499   if (isThumb2(STI)) {
500     EncodedValue &= 0x00FFFFFF;
501     EncodedValue |= 0xEE000000;
502   }
503 
504   return EncodedValue;
505 }
506 
507 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
508 /// if we are in Thumb2.
509 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
510                                                  unsigned EncodedValue,
511                                                  const MCSubtargetInfo &STI) const {
512   if (isThumb2(STI)) {
513     EncodedValue |= 0xC000000; // Set bits 27-26
514   }
515 
516   return EncodedValue;
517 }
518 
519 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
520 /// them to their Thumb2 form if we are currently in Thumb2 mode.
521 unsigned ARMMCCodeEmitter::
522 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
523                      const MCSubtargetInfo &STI) const {
524   if (isThumb2(STI)) {
525     EncodedValue &= 0x0FFFFFFF;
526     EncodedValue |= 0xE0000000;
527   }
528   return EncodedValue;
529 }
530 
531 /// getMachineOpValue - Return binary encoding of operand. If the machine
532 /// operand requires relocation, record the relocation and return zero.
533 unsigned ARMMCCodeEmitter::
534 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
535                   SmallVectorImpl<MCFixup> &Fixups,
536                   const MCSubtargetInfo &STI) const {
537   if (MO.isReg()) {
538     unsigned Reg = MO.getReg();
539     unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
540 
541     // Q registers are encoded as 2x their register number.
542     switch (Reg) {
543     default:
544       return RegNo;
545     case ARM::Q0:  case ARM::Q1:  case ARM::Q2:  case ARM::Q3:
546     case ARM::Q4:  case ARM::Q5:  case ARM::Q6:  case ARM::Q7:
547     case ARM::Q8:  case ARM::Q9:  case ARM::Q10: case ARM::Q11:
548     case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
549       return 2 * RegNo;
550     }
551   } else if (MO.isImm()) {
552     return static_cast<unsigned>(MO.getImm());
553   } else if (MO.isFPImm()) {
554     return static_cast<unsigned>(APFloat(MO.getFPImm())
555                      .bitcastToAPInt().getHiBits(32).getLimitedValue());
556   }
557 
558   llvm_unreachable("Unable to encode MCOperand!");
559 }
560 
561 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
562 bool ARMMCCodeEmitter::
563 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
564                        unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
565  const MCSubtargetInfo &STI) const {
566   const MCOperand &MO  = MI.getOperand(OpIdx);
567   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
568 
569   Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
570 
571   int32_t SImm = MO1.getImm();
572   bool isAdd = true;
573 
574   // Special value for #-0
575   if (SImm == INT32_MIN) {
576     SImm = 0;
577     isAdd = false;
578   }
579 
580   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
581   if (SImm < 0) {
582     SImm = -SImm;
583     isAdd = false;
584   }
585 
586   Imm = SImm;
587   return isAdd;
588 }
589 
590 /// getBranchTargetOpValue - Helper function to get the branch target operand,
591 /// which is either an immediate or requires a fixup.
592 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
593                                        unsigned FixupKind,
594                                        SmallVectorImpl<MCFixup> &Fixups,
595                                        const MCSubtargetInfo &STI) {
596   const MCOperand &MO = MI.getOperand(OpIdx);
597 
598   // If the destination is an immediate, we have nothing to do.
599   if (MO.isImm()) return MO.getImm();
600   assert(MO.isExpr() && "Unexpected branch target type!");
601   const MCExpr *Expr = MO.getExpr();
602   MCFixupKind Kind = MCFixupKind(FixupKind);
603   Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
604 
605   // All of the information is in the fixup.
606   return 0;
607 }
608 
609 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
610 // determined by negating them and XOR'ing them with bit 23.
611 static int32_t encodeThumbBLOffset(int32_t offset) {
612   offset >>= 1;
613   uint32_t S  = (offset & 0x800000) >> 23;
614   uint32_t J1 = (offset & 0x400000) >> 22;
615   uint32_t J2 = (offset & 0x200000) >> 21;
616   J1 = (~J1 & 0x1);
617   J2 = (~J2 & 0x1);
618   J1 ^= S;
619   J2 ^= S;
620 
621   offset &= ~0x600000;
622   offset |= J1 << 22;
623   offset |= J2 << 21;
624 
625   return offset;
626 }
627 
628 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
629 uint32_t ARMMCCodeEmitter::
630 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
631                         SmallVectorImpl<MCFixup> &Fixups,
632                         const MCSubtargetInfo &STI) const {
633   const MCOperand MO = MI.getOperand(OpIdx);
634   if (MO.isExpr())
635     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
636                                     Fixups, STI);
637   return encodeThumbBLOffset(MO.getImm());
638 }
639 
640 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
641 /// BLX branch target.
642 uint32_t ARMMCCodeEmitter::
643 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
644                          SmallVectorImpl<MCFixup> &Fixups,
645                          const MCSubtargetInfo &STI) const {
646   const MCOperand MO = MI.getOperand(OpIdx);
647   if (MO.isExpr())
648     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
649                                     Fixups, STI);
650   return encodeThumbBLOffset(MO.getImm());
651 }
652 
653 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
654 uint32_t ARMMCCodeEmitter::
655 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
656                         SmallVectorImpl<MCFixup> &Fixups,
657                         const MCSubtargetInfo &STI) const {
658   const MCOperand MO = MI.getOperand(OpIdx);
659   if (MO.isExpr())
660     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
661                                     Fixups, STI);
662   return (MO.getImm() >> 1);
663 }
664 
665 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
666 uint32_t ARMMCCodeEmitter::
667 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
668                          SmallVectorImpl<MCFixup> &Fixups,
669                          const MCSubtargetInfo &STI) const {
670   const MCOperand MO = MI.getOperand(OpIdx);
671   if (MO.isExpr())
672     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
673                                     Fixups, STI);
674   return (MO.getImm() >> 1);
675 }
676 
677 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
678 uint32_t ARMMCCodeEmitter::
679 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
680                         SmallVectorImpl<MCFixup> &Fixups,
681                         const MCSubtargetInfo &STI) const {
682   const MCOperand MO = MI.getOperand(OpIdx);
683   if (MO.isExpr())
684     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI);
685   return (MO.getImm() >> 1);
686 }
687 
688 /// Return true if this branch has a non-always predication
689 static bool HasConditionalBranch(const MCInst &MI) {
690   int NumOp = MI.getNumOperands();
691   if (NumOp >= 2) {
692     for (int i = 0; i < NumOp-1; ++i) {
693       const MCOperand &MCOp1 = MI.getOperand(i);
694       const MCOperand &MCOp2 = MI.getOperand(i + 1);
695       if (MCOp1.isImm() && MCOp2.isReg() &&
696           (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
697         if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
698           return true;
699       }
700     }
701   }
702   return false;
703 }
704 
705 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
706 /// target.
707 uint32_t ARMMCCodeEmitter::
708 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
709                        SmallVectorImpl<MCFixup> &Fixups,
710                        const MCSubtargetInfo &STI) const {
711   // FIXME: This really, really shouldn't use TargetMachine. We don't want
712   // coupling between MC and TM anywhere we can help it.
713   if (isThumb2(STI))
714     return
715       ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI);
716   return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
717 }
718 
719 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
720 /// target.
721 uint32_t ARMMCCodeEmitter::
722 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
723                           SmallVectorImpl<MCFixup> &Fixups,
724                           const MCSubtargetInfo &STI) const {
725   const MCOperand MO = MI.getOperand(OpIdx);
726   if (MO.isExpr()) {
727     if (HasConditionalBranch(MI))
728       return ::getBranchTargetOpValue(MI, OpIdx,
729                                       ARM::fixup_arm_condbranch, Fixups, STI);
730     return ::getBranchTargetOpValue(MI, OpIdx,
731                                     ARM::fixup_arm_uncondbranch, Fixups, STI);
732   }
733 
734   return MO.getImm() >> 2;
735 }
736 
737 uint32_t ARMMCCodeEmitter::
738 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
739                           SmallVectorImpl<MCFixup> &Fixups,
740                           const MCSubtargetInfo &STI) const {
741   const MCOperand MO = MI.getOperand(OpIdx);
742   if (MO.isExpr()) {
743     if (HasConditionalBranch(MI))
744       return ::getBranchTargetOpValue(MI, OpIdx,
745                                       ARM::fixup_arm_condbl, Fixups, STI);
746     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI);
747   }
748 
749   return MO.getImm() >> 2;
750 }
751 
752 uint32_t ARMMCCodeEmitter::
753 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
754                           SmallVectorImpl<MCFixup> &Fixups,
755                           const MCSubtargetInfo &STI) const {
756   const MCOperand MO = MI.getOperand(OpIdx);
757   if (MO.isExpr())
758     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI);
759 
760   return MO.getImm() >> 1;
761 }
762 
763 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
764 /// immediate branch target.
765 uint32_t ARMMCCodeEmitter::
766 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
767                        SmallVectorImpl<MCFixup> &Fixups,
768                        const MCSubtargetInfo &STI) const {
769   unsigned Val = 0;
770   const MCOperand MO = MI.getOperand(OpIdx);
771 
772   if(MO.isExpr())
773     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI);
774   else
775     Val = MO.getImm() >> 1;
776 
777   bool I  = (Val & 0x800000);
778   bool J1 = (Val & 0x400000);
779   bool J2 = (Val & 0x200000);
780   if (I ^ J1)
781     Val &= ~0x400000;
782   else
783     Val |= 0x400000;
784 
785   if (I ^ J2)
786     Val &= ~0x200000;
787   else
788     Val |= 0x200000;
789 
790   return Val;
791 }
792 
793 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
794 /// ADR label target.
795 uint32_t ARMMCCodeEmitter::
796 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
797                    SmallVectorImpl<MCFixup> &Fixups,
798                    const MCSubtargetInfo &STI) const {
799   const MCOperand MO = MI.getOperand(OpIdx);
800   if (MO.isExpr())
801     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
802                                     Fixups, STI);
803   int64_t offset = MO.getImm();
804   uint32_t Val = 0x2000;
805 
806   int SoImmVal;
807   if (offset == INT32_MIN) {
808     Val = 0x1000;
809     SoImmVal = 0;
810   } else if (offset < 0) {
811     Val = 0x1000;
812     offset *= -1;
813     SoImmVal = ARM_AM::getSOImmVal(offset);
814     if(SoImmVal == -1) {
815       Val = 0x2000;
816       offset *= -1;
817       SoImmVal = ARM_AM::getSOImmVal(offset);
818     }
819   } else {
820     SoImmVal = ARM_AM::getSOImmVal(offset);
821     if(SoImmVal == -1) {
822       Val = 0x1000;
823       offset *= -1;
824       SoImmVal = ARM_AM::getSOImmVal(offset);
825     }
826   }
827 
828   assert(SoImmVal != -1 && "Not a valid so_imm value!");
829 
830   Val |= SoImmVal;
831   return Val;
832 }
833 
834 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
835 /// target.
836 uint32_t ARMMCCodeEmitter::
837 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
838                    SmallVectorImpl<MCFixup> &Fixups,
839                    const MCSubtargetInfo &STI) const {
840   const MCOperand MO = MI.getOperand(OpIdx);
841   if (MO.isExpr())
842     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
843                                     Fixups, STI);
844   int32_t Val = MO.getImm();
845   if (Val == INT32_MIN)
846     Val = 0x1000;
847   else if (Val < 0) {
848     Val *= -1;
849     Val |= 0x1000;
850   }
851   return Val;
852 }
853 
854 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
855 /// target.
856 uint32_t ARMMCCodeEmitter::
857 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
858                    SmallVectorImpl<MCFixup> &Fixups,
859                    const MCSubtargetInfo &STI) const {
860   const MCOperand MO = MI.getOperand(OpIdx);
861   if (MO.isExpr())
862     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
863                                     Fixups, STI);
864   return MO.getImm();
865 }
866 
867 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
868 /// operand.
869 uint32_t ARMMCCodeEmitter::
870 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
871                               SmallVectorImpl<MCFixup> &,
872                               const MCSubtargetInfo &STI) const {
873   // [Rn, Rm]
874   //   {5-3} = Rm
875   //   {2-0} = Rn
876   const MCOperand &MO1 = MI.getOperand(OpIdx);
877   const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
878   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
879   unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
880   return (Rm << 3) | Rn;
881 }
882 
883 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
884 uint32_t ARMMCCodeEmitter::
885 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
886                         SmallVectorImpl<MCFixup> &Fixups,
887                         const MCSubtargetInfo &STI) const {
888   // {17-13} = reg
889   // {12}    = (U)nsigned (add == '1', sub == '0')
890   // {11-0}  = imm12
891   unsigned Reg, Imm12;
892   bool isAdd = true;
893   // If The first operand isn't a register, we have a label reference.
894   const MCOperand &MO = MI.getOperand(OpIdx);
895   if (!MO.isReg()) {
896     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
897     Imm12 = 0;
898 
899     if (MO.isExpr()) {
900       const MCExpr *Expr = MO.getExpr();
901       isAdd = false ; // 'U' bit is set as part of the fixup.
902 
903       MCFixupKind Kind;
904       if (isThumb2(STI))
905         Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
906       else
907         Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
908       Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
909 
910       ++MCNumCPRelocations;
911     } else {
912       Reg = ARM::PC;
913       int32_t Offset = MO.getImm();
914       if (Offset == INT32_MIN) {
915         Offset = 0;
916         isAdd = false;
917       } else if (Offset < 0) {
918         Offset *= -1;
919         isAdd = false;
920       }
921       Imm12 = Offset;
922     }
923   } else
924     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
925 
926   uint32_t Binary = Imm12 & 0xfff;
927   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
928   if (isAdd)
929     Binary |= (1 << 12);
930   Binary |= (Reg << 13);
931   return Binary;
932 }
933 
934 /// getT2Imm8s4OpValue - Return encoding info for
935 /// '+/- imm8<<2' operand.
936 uint32_t ARMMCCodeEmitter::
937 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
938                    SmallVectorImpl<MCFixup> &Fixups,
939                    const MCSubtargetInfo &STI) const {
940   // FIXME: The immediate operand should have already been encoded like this
941   // before ever getting here. The encoder method should just need to combine
942   // the MI operands for the register and the offset into a single
943   // representation for the complex operand in the .td file. This isn't just
944   // style, unfortunately. As-is, we can't represent the distinct encoding
945   // for #-0.
946 
947   // {8}    = (U)nsigned (add == '1', sub == '0')
948   // {7-0}  = imm8
949   int32_t Imm8 = MI.getOperand(OpIdx).getImm();
950   bool isAdd = Imm8 >= 0;
951 
952   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
953   if (Imm8 < 0)
954     Imm8 = -(uint32_t)Imm8;
955 
956   // Scaled by 4.
957   Imm8 /= 4;
958 
959   uint32_t Binary = Imm8 & 0xff;
960   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
961   if (isAdd)
962     Binary |= (1 << 8);
963   return Binary;
964 }
965 
966 /// getT2AddrModeImm8s4OpValue - Return encoding info for
967 /// 'reg +/- imm8<<2' operand.
968 uint32_t ARMMCCodeEmitter::
969 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
970                         SmallVectorImpl<MCFixup> &Fixups,
971                         const MCSubtargetInfo &STI) const {
972   // {12-9} = reg
973   // {8}    = (U)nsigned (add == '1', sub == '0')
974   // {7-0}  = imm8
975   unsigned Reg, Imm8;
976   bool isAdd = true;
977   // If The first operand isn't a register, we have a label reference.
978   const MCOperand &MO = MI.getOperand(OpIdx);
979   if (!MO.isReg()) {
980     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
981     Imm8 = 0;
982     isAdd = false ; // 'U' bit is set as part of the fixup.
983 
984     assert(MO.isExpr() && "Unexpected machine operand type!");
985     const MCExpr *Expr = MO.getExpr();
986     MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
987     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
988 
989     ++MCNumCPRelocations;
990   } else
991     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
992 
993   // FIXME: The immediate operand should have already been encoded like this
994   // before ever getting here. The encoder method should just need to combine
995   // the MI operands for the register and the offset into a single
996   // representation for the complex operand in the .td file. This isn't just
997   // style, unfortunately. As-is, we can't represent the distinct encoding
998   // for #-0.
999   uint32_t Binary = (Imm8 >> 2) & 0xff;
1000   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1001   if (isAdd)
1002     Binary |= (1 << 8);
1003   Binary |= (Reg << 9);
1004   return Binary;
1005 }
1006 
1007 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
1008 /// 'reg + imm8<<2' operand.
1009 uint32_t ARMMCCodeEmitter::
1010 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
1011                         SmallVectorImpl<MCFixup> &Fixups,
1012                         const MCSubtargetInfo &STI) const {
1013   // {11-8} = reg
1014   // {7-0}  = imm8
1015   const MCOperand &MO = MI.getOperand(OpIdx);
1016   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1017   unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1018   unsigned Imm8 = MO1.getImm();
1019   return (Reg << 8) | Imm8;
1020 }
1021 
1022 uint32_t
1023 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
1024                                       SmallVectorImpl<MCFixup> &Fixups,
1025                                       const MCSubtargetInfo &STI) const {
1026   // {20-16} = imm{15-12}
1027   // {11-0}  = imm{11-0}
1028   const MCOperand &MO = MI.getOperand(OpIdx);
1029   if (MO.isImm())
1030     // Hi / lo 16 bits already extracted during earlier passes.
1031     return static_cast<unsigned>(MO.getImm());
1032 
1033   // Handle :upper16: and :lower16: assembly prefixes.
1034   const MCExpr *E = MO.getExpr();
1035   MCFixupKind Kind;
1036   if (E->getKind() == MCExpr::Target) {
1037     const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
1038     E = ARM16Expr->getSubExpr();
1039 
1040     if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) {
1041       const int64_t Value = MCE->getValue();
1042       if (Value > UINT32_MAX)
1043         report_fatal_error("constant value truncated (limited to 32-bit)");
1044 
1045       switch (ARM16Expr->getKind()) {
1046       case ARMMCExpr::VK_ARM_HI16:
1047         return (int32_t(Value) & 0xffff0000) >> 16;
1048       case ARMMCExpr::VK_ARM_LO16:
1049         return (int32_t(Value) & 0x0000ffff);
1050       default: llvm_unreachable("Unsupported ARMFixup");
1051       }
1052     }
1053 
1054     switch (ARM16Expr->getKind()) {
1055     default: llvm_unreachable("Unsupported ARMFixup");
1056     case ARMMCExpr::VK_ARM_HI16:
1057       Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movt_hi16
1058                                       : ARM::fixup_arm_movt_hi16);
1059       break;
1060     case ARMMCExpr::VK_ARM_LO16:
1061       Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movw_lo16
1062                                       : ARM::fixup_arm_movw_lo16);
1063       break;
1064     }
1065 
1066     Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc()));
1067     return 0;
1068   }
1069   // If the expression doesn't have :upper16: or :lower16: on it,
1070   // it's just a plain immediate expression, previously those evaluated to
1071   // the lower 16 bits of the expression regardless of whether
1072   // we have a movt or a movw, but that led to misleadingly results.
1073   // This is disallowed in the AsmParser in validateInstruction()
1074   // so this should never happen.
1075   llvm_unreachable("expression without :upper16: or :lower16:");
1076 }
1077 
1078 uint32_t ARMMCCodeEmitter::
1079 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1080                     SmallVectorImpl<MCFixup> &Fixups,
1081                     const MCSubtargetInfo &STI) const {
1082   const MCOperand &MO = MI.getOperand(OpIdx);
1083   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1084   const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1085   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1086   unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1087   unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
1088   bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
1089   ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
1090   unsigned SBits = getShiftOp(ShOp);
1091 
1092   // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1093   // amount. However, it would be an easy mistake to make so check here.
1094   assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
1095 
1096   // {16-13} = Rn
1097   // {12}    = isAdd
1098   // {11-0}  = shifter
1099   //  {3-0}  = Rm
1100   //  {4}    = 0
1101   //  {6-5}  = type
1102   //  {11-7} = imm
1103   uint32_t Binary = Rm;
1104   Binary |= Rn << 13;
1105   Binary |= SBits << 5;
1106   Binary |= ShImm << 7;
1107   if (isAdd)
1108     Binary |= 1 << 12;
1109   return Binary;
1110 }
1111 
1112 uint32_t ARMMCCodeEmitter::
1113 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
1114                     SmallVectorImpl<MCFixup> &Fixups,
1115                     const MCSubtargetInfo &STI) const {
1116   // {17-14}  Rn
1117   // {13}     1 == imm12, 0 == Rm
1118   // {12}     isAdd
1119   // {11-0}   imm12/Rm
1120   const MCOperand &MO = MI.getOperand(OpIdx);
1121   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1122   uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups, STI);
1123   Binary |= Rn << 14;
1124   return Binary;
1125 }
1126 
1127 uint32_t ARMMCCodeEmitter::
1128 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1129                           SmallVectorImpl<MCFixup> &Fixups,
1130                           const MCSubtargetInfo &STI) const {
1131   // {13}     1 == imm12, 0 == Rm
1132   // {12}     isAdd
1133   // {11-0}   imm12/Rm
1134   const MCOperand &MO = MI.getOperand(OpIdx);
1135   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1136   unsigned Imm = MO1.getImm();
1137   bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1138   bool isReg = MO.getReg() != 0;
1139   uint32_t Binary = ARM_AM::getAM2Offset(Imm);
1140   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
1141   if (isReg) {
1142     ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
1143     Binary <<= 7;                    // Shift amount is bits [11:7]
1144     Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1145     Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1146   }
1147   return Binary | (isAdd << 12) | (isReg << 13);
1148 }
1149 
1150 uint32_t ARMMCCodeEmitter::
1151 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1152                      SmallVectorImpl<MCFixup> &Fixups,
1153                      const MCSubtargetInfo &STI) const {
1154   // {4}      isAdd
1155   // {3-0}    Rm
1156   const MCOperand &MO = MI.getOperand(OpIdx);
1157   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1158   bool isAdd = MO1.getImm() != 0;
1159   return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
1160 }
1161 
1162 uint32_t ARMMCCodeEmitter::
1163 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1164                           SmallVectorImpl<MCFixup> &Fixups,
1165                           const MCSubtargetInfo &STI) const {
1166   // {9}      1 == imm8, 0 == Rm
1167   // {8}      isAdd
1168   // {7-4}    imm7_4/zero
1169   // {3-0}    imm3_0/Rm
1170   const MCOperand &MO = MI.getOperand(OpIdx);
1171   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1172   unsigned Imm = MO1.getImm();
1173   bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1174   bool isImm = MO.getReg() == 0;
1175   uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1176   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1177   if (!isImm)
1178     Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1179   return Imm8 | (isAdd << 8) | (isImm << 9);
1180 }
1181 
1182 uint32_t ARMMCCodeEmitter::
1183 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1184                     SmallVectorImpl<MCFixup> &Fixups,
1185                     const MCSubtargetInfo &STI) const {
1186   // {13}     1 == imm8, 0 == Rm
1187   // {12-9}   Rn
1188   // {8}      isAdd
1189   // {7-4}    imm7_4/zero
1190   // {3-0}    imm3_0/Rm
1191   const MCOperand &MO = MI.getOperand(OpIdx);
1192   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1193   const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1194 
1195   // If The first operand isn't a register, we have a label reference.
1196   if (!MO.isReg()) {
1197     unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1198 
1199     assert(MO.isExpr() && "Unexpected machine operand type!");
1200     const MCExpr *Expr = MO.getExpr();
1201     MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1202     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1203 
1204     ++MCNumCPRelocations;
1205     return (Rn << 9) | (1 << 13);
1206   }
1207   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1208   unsigned Imm = MO2.getImm();
1209   bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1210   bool isImm = MO1.getReg() == 0;
1211   uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1212   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1213   if (!isImm)
1214     Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1215   return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1216 }
1217 
1218 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1219 uint32_t ARMMCCodeEmitter::
1220 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1221                           SmallVectorImpl<MCFixup> &Fixups,
1222                           const MCSubtargetInfo &STI) const {
1223   // [SP, #imm]
1224   //   {7-0} = imm8
1225   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1226   assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1227          "Unexpected base register!");
1228 
1229   // The immediate is already shifted for the implicit zeroes, so no change
1230   // here.
1231   return MO1.getImm() & 0xff;
1232 }
1233 
1234 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1235 uint32_t ARMMCCodeEmitter::
1236 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1237                      SmallVectorImpl<MCFixup> &Fixups,
1238                      const MCSubtargetInfo &STI) const {
1239   // [Rn, #imm]
1240   //   {7-3} = imm5
1241   //   {2-0} = Rn
1242   const MCOperand &MO = MI.getOperand(OpIdx);
1243   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1244   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1245   unsigned Imm5 = MO1.getImm();
1246   return ((Imm5 & 0x1f) << 3) | Rn;
1247 }
1248 
1249 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1250 uint32_t ARMMCCodeEmitter::
1251 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1252                      SmallVectorImpl<MCFixup> &Fixups,
1253                      const MCSubtargetInfo &STI) const {
1254   const MCOperand MO = MI.getOperand(OpIdx);
1255   if (MO.isExpr())
1256     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI);
1257   return (MO.getImm() >> 2);
1258 }
1259 
1260 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
1261 uint32_t ARMMCCodeEmitter::
1262 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1263                     SmallVectorImpl<MCFixup> &Fixups,
1264                     const MCSubtargetInfo &STI) const {
1265   // {12-9} = reg
1266   // {8}    = (U)nsigned (add == '1', sub == '0')
1267   // {7-0}  = imm8
1268   unsigned Reg, Imm8;
1269   bool isAdd;
1270   // If The first operand isn't a register, we have a label reference.
1271   const MCOperand &MO = MI.getOperand(OpIdx);
1272   if (!MO.isReg()) {
1273     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1274     Imm8 = 0;
1275     isAdd = false; // 'U' bit is handled as part of the fixup.
1276 
1277     assert(MO.isExpr() && "Unexpected machine operand type!");
1278     const MCExpr *Expr = MO.getExpr();
1279     MCFixupKind Kind;
1280     if (isThumb2(STI))
1281       Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1282     else
1283       Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1284     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1285 
1286     ++MCNumCPRelocations;
1287   } else {
1288     EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1289     isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1290   }
1291 
1292   uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1293   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1294   if (isAdd)
1295     Binary |= (1 << 8);
1296   Binary |= (Reg << 9);
1297   return Binary;
1298 }
1299 
1300 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
1301 uint32_t ARMMCCodeEmitter::
1302 getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
1303                     SmallVectorImpl<MCFixup> &Fixups,
1304                     const MCSubtargetInfo &STI) const {
1305   // {12-9} = reg
1306   // {8}    = (U)nsigned (add == '1', sub == '0')
1307   // {7-0}  = imm8
1308   unsigned Reg, Imm8;
1309   bool isAdd;
1310   // If The first operand isn't a register, we have a label reference.
1311   const MCOperand &MO = MI.getOperand(OpIdx);
1312   if (!MO.isReg()) {
1313     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1314     Imm8 = 0;
1315     isAdd = false; // 'U' bit is handled as part of the fixup.
1316 
1317     assert(MO.isExpr() && "Unexpected machine operand type!");
1318     const MCExpr *Expr = MO.getExpr();
1319     MCFixupKind Kind;
1320     if (isThumb2(STI))
1321       Kind = MCFixupKind(ARM::fixup_t2_pcrel_9);
1322     else
1323       Kind = MCFixupKind(ARM::fixup_arm_pcrel_9);
1324     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1325 
1326     ++MCNumCPRelocations;
1327   } else {
1328     EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1329     isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1330   }
1331 
1332   uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1333   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1334   if (isAdd)
1335     Binary |= (1 << 8);
1336   Binary |= (Reg << 9);
1337   return Binary;
1338 }
1339 
1340 unsigned ARMMCCodeEmitter::
1341 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1342                 SmallVectorImpl<MCFixup> &Fixups,
1343                 const MCSubtargetInfo &STI) const {
1344   // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1345   // shifted. The second is Rs, the amount to shift by, and the third specifies
1346   // the type of the shift.
1347   //
1348   // {3-0} = Rm.
1349   // {4}   = 1
1350   // {6-5} = type
1351   // {11-8} = Rs
1352   // {7}    = 0
1353 
1354   const MCOperand &MO  = MI.getOperand(OpIdx);
1355   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1356   const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1357   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1358 
1359   // Encode Rm.
1360   unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1361 
1362   // Encode the shift opcode.
1363   unsigned SBits = 0;
1364   unsigned Rs = MO1.getReg();
1365   if (Rs) {
1366     // Set shift operand (bit[7:4]).
1367     // LSL - 0001
1368     // LSR - 0011
1369     // ASR - 0101
1370     // ROR - 0111
1371     switch (SOpc) {
1372     default: llvm_unreachable("Unknown shift opc!");
1373     case ARM_AM::lsl: SBits = 0x1; break;
1374     case ARM_AM::lsr: SBits = 0x3; break;
1375     case ARM_AM::asr: SBits = 0x5; break;
1376     case ARM_AM::ror: SBits = 0x7; break;
1377     }
1378   }
1379 
1380   Binary |= SBits << 4;
1381 
1382   // Encode the shift operation Rs.
1383   // Encode Rs bit[11:8].
1384   assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1385   return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
1386 }
1387 
1388 unsigned ARMMCCodeEmitter::
1389 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1390                 SmallVectorImpl<MCFixup> &Fixups,
1391                 const MCSubtargetInfo &STI) const {
1392   // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1393   // shifted. The second is the amount to shift by.
1394   //
1395   // {3-0} = Rm.
1396   // {4}   = 0
1397   // {6-5} = type
1398   // {11-7} = imm
1399 
1400   const MCOperand &MO  = MI.getOperand(OpIdx);
1401   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1402   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1403 
1404   // Encode Rm.
1405   unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1406 
1407   // Encode the shift opcode.
1408   unsigned SBits = 0;
1409 
1410   // Set shift operand (bit[6:4]).
1411   // LSL - 000
1412   // LSR - 010
1413   // ASR - 100
1414   // ROR - 110
1415   // RRX - 110 and bit[11:8] clear.
1416   switch (SOpc) {
1417   default: llvm_unreachable("Unknown shift opc!");
1418   case ARM_AM::lsl: SBits = 0x0; break;
1419   case ARM_AM::lsr: SBits = 0x2; break;
1420   case ARM_AM::asr: SBits = 0x4; break;
1421   case ARM_AM::ror: SBits = 0x6; break;
1422   case ARM_AM::rrx:
1423     Binary |= 0x60;
1424     return Binary;
1425   }
1426 
1427   // Encode shift_imm bit[11:7].
1428   Binary |= SBits << 4;
1429   unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1430   assert(Offset < 32 && "Offset must be in range 0-31!");
1431   return Binary | (Offset << 7);
1432 }
1433 
1434 
1435 unsigned ARMMCCodeEmitter::
1436 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1437                 SmallVectorImpl<MCFixup> &Fixups,
1438                 const MCSubtargetInfo &STI) const {
1439   const MCOperand &MO1 = MI.getOperand(OpNum);
1440   const MCOperand &MO2 = MI.getOperand(OpNum+1);
1441   const MCOperand &MO3 = MI.getOperand(OpNum+2);
1442 
1443   // Encoded as [Rn, Rm, imm].
1444   // FIXME: Needs fixup support.
1445   unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1446   Value <<= 4;
1447   Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1448   Value <<= 2;
1449   Value |= MO3.getImm();
1450 
1451   return Value;
1452 }
1453 
1454 unsigned ARMMCCodeEmitter::
1455 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1456                          SmallVectorImpl<MCFixup> &Fixups,
1457                          const MCSubtargetInfo &STI) const {
1458   const MCOperand &MO1 = MI.getOperand(OpNum);
1459   const MCOperand &MO2 = MI.getOperand(OpNum+1);
1460 
1461   // FIXME: Needs fixup support.
1462   unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1463 
1464   // Even though the immediate is 8 bits long, we need 9 bits in order
1465   // to represent the (inverse of the) sign bit.
1466   Value <<= 9;
1467   int32_t tmp = (int32_t)MO2.getImm();
1468   if (tmp < 0)
1469     tmp = abs(tmp);
1470   else
1471     Value |= 256; // Set the ADD bit
1472   Value |= tmp & 255;
1473   return Value;
1474 }
1475 
1476 unsigned ARMMCCodeEmitter::
1477 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1478                          SmallVectorImpl<MCFixup> &Fixups,
1479                          const MCSubtargetInfo &STI) const {
1480   const MCOperand &MO1 = MI.getOperand(OpNum);
1481 
1482   // FIXME: Needs fixup support.
1483   unsigned Value = 0;
1484   int32_t tmp = (int32_t)MO1.getImm();
1485   if (tmp < 0)
1486     tmp = abs(tmp);
1487   else
1488     Value |= 256; // Set the ADD bit
1489   Value |= tmp & 255;
1490   return Value;
1491 }
1492 
1493 unsigned ARMMCCodeEmitter::
1494 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1495                          SmallVectorImpl<MCFixup> &Fixups,
1496                          const MCSubtargetInfo &STI) const {
1497   const MCOperand &MO1 = MI.getOperand(OpNum);
1498 
1499   // FIXME: Needs fixup support.
1500   unsigned Value = 0;
1501   int32_t tmp = (int32_t)MO1.getImm();
1502   if (tmp < 0)
1503     tmp = abs(tmp);
1504   else
1505     Value |= 4096; // Set the ADD bit
1506   Value |= tmp & 4095;
1507   return Value;
1508 }
1509 
1510 unsigned ARMMCCodeEmitter::
1511 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1512                 SmallVectorImpl<MCFixup> &Fixups,
1513                 const MCSubtargetInfo &STI) const {
1514   // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1515   // shifted. The second is the amount to shift by.
1516   //
1517   // {3-0} = Rm.
1518   // {4}   = 0
1519   // {6-5} = type
1520   // {11-7} = imm
1521 
1522   const MCOperand &MO  = MI.getOperand(OpIdx);
1523   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1524   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1525 
1526   // Encode Rm.
1527   unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1528 
1529   // Encode the shift opcode.
1530   unsigned SBits = 0;
1531   // Set shift operand (bit[6:4]).
1532   // LSL - 000
1533   // LSR - 010
1534   // ASR - 100
1535   // ROR - 110
1536   switch (SOpc) {
1537   default: llvm_unreachable("Unknown shift opc!");
1538   case ARM_AM::lsl: SBits = 0x0; break;
1539   case ARM_AM::lsr: SBits = 0x2; break;
1540   case ARM_AM::asr: SBits = 0x4; break;
1541   case ARM_AM::rrx: // FALLTHROUGH
1542   case ARM_AM::ror: SBits = 0x6; break;
1543   }
1544 
1545   Binary |= SBits << 4;
1546   if (SOpc == ARM_AM::rrx)
1547     return Binary;
1548 
1549   // Encode shift_imm bit[11:7].
1550   return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1551 }
1552 
1553 unsigned ARMMCCodeEmitter::
1554 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1555                                SmallVectorImpl<MCFixup> &Fixups,
1556                                const MCSubtargetInfo &STI) const {
1557   // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1558   // msb of the mask.
1559   const MCOperand &MO = MI.getOperand(Op);
1560   uint32_t v = ~MO.getImm();
1561   uint32_t lsb = countTrailingZeros(v);
1562   uint32_t msb = (32 - countLeadingZeros (v)) - 1;
1563   assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1564   return lsb | (msb << 5);
1565 }
1566 
1567 unsigned ARMMCCodeEmitter::
1568 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1569                        SmallVectorImpl<MCFixup> &Fixups,
1570                        const MCSubtargetInfo &STI) const {
1571   // VLDM/VSTM:
1572   //   {12-8} = Vd
1573   //   {7-0}  = Number of registers
1574   //
1575   // LDM/STM:
1576   //   {15-0}  = Bitfield of GPRs.
1577   unsigned Reg = MI.getOperand(Op).getReg();
1578   bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1579   bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1580 
1581   unsigned Binary = 0;
1582 
1583   if (SPRRegs || DPRRegs) {
1584     // VLDM/VSTM
1585     unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1586     unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1587     Binary |= (RegNo & 0x1f) << 8;
1588     if (SPRRegs)
1589       Binary |= NumRegs;
1590     else
1591       Binary |= NumRegs * 2;
1592   } else {
1593     for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1594       unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(MI.getOperand(I).getReg());
1595       Binary |= 1 << RegNo;
1596     }
1597   }
1598 
1599   return Binary;
1600 }
1601 
1602 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1603 /// with the alignment operand.
1604 unsigned ARMMCCodeEmitter::
1605 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1606                            SmallVectorImpl<MCFixup> &Fixups,
1607                            const MCSubtargetInfo &STI) const {
1608   const MCOperand &Reg = MI.getOperand(Op);
1609   const MCOperand &Imm = MI.getOperand(Op + 1);
1610 
1611   unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1612   unsigned Align = 0;
1613 
1614   switch (Imm.getImm()) {
1615   default: break;
1616   case 2:
1617   case 4:
1618   case 8:  Align = 0x01; break;
1619   case 16: Align = 0x02; break;
1620   case 32: Align = 0x03; break;
1621   }
1622 
1623   return RegNo | (Align << 4);
1624 }
1625 
1626 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1627 /// along  with the alignment operand for use in VST1 and VLD1 with size 32.
1628 unsigned ARMMCCodeEmitter::
1629 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1630                                     SmallVectorImpl<MCFixup> &Fixups,
1631                                     const MCSubtargetInfo &STI) const {
1632   const MCOperand &Reg = MI.getOperand(Op);
1633   const MCOperand &Imm = MI.getOperand(Op + 1);
1634 
1635   unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1636   unsigned Align = 0;
1637 
1638   switch (Imm.getImm()) {
1639   default: break;
1640   case 8:
1641   case 16:
1642   case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1643   case 2: Align = 0x00; break;
1644   case 4: Align = 0x03; break;
1645   }
1646 
1647   return RegNo | (Align << 4);
1648 }
1649 
1650 
1651 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1652 /// alignment operand for use in VLD-dup instructions.  This is the same as
1653 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1654 /// different for VLD4-dup.
1655 unsigned ARMMCCodeEmitter::
1656 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1657                               SmallVectorImpl<MCFixup> &Fixups,
1658                               const MCSubtargetInfo &STI) const {
1659   const MCOperand &Reg = MI.getOperand(Op);
1660   const MCOperand &Imm = MI.getOperand(Op + 1);
1661 
1662   unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1663   unsigned Align = 0;
1664 
1665   switch (Imm.getImm()) {
1666   default: break;
1667   case 2:
1668   case 4:
1669   case 8:  Align = 0x01; break;
1670   case 16: Align = 0x03; break;
1671   }
1672 
1673   return RegNo | (Align << 4);
1674 }
1675 
1676 unsigned ARMMCCodeEmitter::
1677 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1678                           SmallVectorImpl<MCFixup> &Fixups,
1679                           const MCSubtargetInfo &STI) const {
1680   const MCOperand &MO = MI.getOperand(Op);
1681   if (MO.getReg() == 0) return 0x0D;
1682   return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1683 }
1684 
1685 unsigned ARMMCCodeEmitter::
1686 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1687                   SmallVectorImpl<MCFixup> &Fixups,
1688                   const MCSubtargetInfo &STI) const {
1689   return 8 - MI.getOperand(Op).getImm();
1690 }
1691 
1692 unsigned ARMMCCodeEmitter::
1693 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1694                    SmallVectorImpl<MCFixup> &Fixups,
1695                    const MCSubtargetInfo &STI) const {
1696   return 16 - MI.getOperand(Op).getImm();
1697 }
1698 
1699 unsigned ARMMCCodeEmitter::
1700 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1701                    SmallVectorImpl<MCFixup> &Fixups,
1702                    const MCSubtargetInfo &STI) const {
1703   return 32 - MI.getOperand(Op).getImm();
1704 }
1705 
1706 unsigned ARMMCCodeEmitter::
1707 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1708                    SmallVectorImpl<MCFixup> &Fixups,
1709                    const MCSubtargetInfo &STI) const {
1710   return 64 - MI.getOperand(Op).getImm();
1711 }
1712 
1713 void ARMMCCodeEmitter::
1714 encodeInstruction(const MCInst &MI, raw_ostream &OS,
1715                   SmallVectorImpl<MCFixup> &Fixups,
1716                   const MCSubtargetInfo &STI) const {
1717   // Pseudo instructions don't get encoded.
1718   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1719   uint64_t TSFlags = Desc.TSFlags;
1720   if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1721     return;
1722 
1723   int Size;
1724   if (Desc.getSize() == 2 || Desc.getSize() == 4)
1725     Size = Desc.getSize();
1726   else
1727     llvm_unreachable("Unexpected instruction size!");
1728 
1729   uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1730   // Thumb 32-bit wide instructions need to emit the high order halfword
1731   // first.
1732   if (isThumb(STI) && Size == 4) {
1733     EmitConstant(Binary >> 16, 2, OS);
1734     EmitConstant(Binary & 0xffff, 2, OS);
1735   } else
1736     EmitConstant(Binary, Size, OS);
1737   ++MCNumEmitted;  // Keep track of the # of mi's emitted.
1738 }
1739 
1740 #include "ARMGenMCCodeEmitter.inc"
1741