1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the ARMMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMFixupKinds.h"
16 #include "MCTargetDesc/ARMMCExpr.h"
17 #include "llvm/ADT/APFloat.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCFixup.h"
26 #include "llvm/MC/MCInst.h"
27 #include "llvm/MC/MCInstrDesc.h"
28 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/MC/MCSubtargetInfo.h"
31 #include "llvm/Support/Casting.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include <algorithm>
37 #include <cassert>
38 #include <cstdint>
39 #include <cstdlib>
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "mccodeemitter"
44 
45 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
46 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
47 
48 namespace {
49 
50 class ARMMCCodeEmitter : public MCCodeEmitter {
51   const MCInstrInfo &MCII;
52   MCContext &CTX;
53   bool IsLittleEndian;
54 
55 public:
56   ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle)
57     : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
58   }
59   ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete;
60   ARMMCCodeEmitter &operator=(const ARMMCCodeEmitter &) = delete;
61   ~ARMMCCodeEmitter() override = default;
62 
63   bool isThumb(const MCSubtargetInfo &STI) const {
64     return STI.getFeatureBits()[ARM::ModeThumb];
65   }
66 
67   bool isThumb2(const MCSubtargetInfo &STI) const {
68     return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
69   }
70 
71   bool isTargetMachO(const MCSubtargetInfo &STI) const {
72     const Triple &TT = STI.getTargetTriple();
73     return TT.isOSBinFormatMachO();
74   }
75 
76   unsigned getMachineSoImmOpValue(unsigned SoImm) const;
77 
78   // getBinaryCodeForInstr - TableGen'erated function for getting the
79   // binary encoding for an instruction.
80   uint64_t getBinaryCodeForInstr(const MCInst &MI,
81                                  SmallVectorImpl<MCFixup> &Fixups,
82                                  const MCSubtargetInfo &STI) const;
83 
84   /// getMachineOpValue - Return binary encoding of operand. If the machine
85   /// operand requires relocation, record the relocation and return zero.
86   unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
87                              SmallVectorImpl<MCFixup> &Fixups,
88                              const MCSubtargetInfo &STI) const;
89 
90   /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
91   /// the specified operand. This is used for operands with :lower16: and
92   /// :upper16: prefixes.
93   uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
94                                SmallVectorImpl<MCFixup> &Fixups,
95                                const MCSubtargetInfo &STI) const;
96 
97   bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
98                               unsigned &Reg, unsigned &Imm,
99                               SmallVectorImpl<MCFixup> &Fixups,
100                               const MCSubtargetInfo &STI) const;
101 
102   /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
103   /// BL branch target.
104   uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
105                                    SmallVectorImpl<MCFixup> &Fixups,
106                                    const MCSubtargetInfo &STI) const;
107 
108   /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
109   /// BLX branch target.
110   uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
111                                     SmallVectorImpl<MCFixup> &Fixups,
112                                     const MCSubtargetInfo &STI) const;
113 
114   /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
115   uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
116                                    SmallVectorImpl<MCFixup> &Fixups,
117                                    const MCSubtargetInfo &STI) const;
118 
119   /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
120   uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
121                                     SmallVectorImpl<MCFixup> &Fixups,
122                                     const MCSubtargetInfo &STI) const;
123 
124   /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
125   uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
126                                    SmallVectorImpl<MCFixup> &Fixups,
127                                    const MCSubtargetInfo &STI) const;
128 
129   /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
130   /// branch target.
131   uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
132                                   SmallVectorImpl<MCFixup> &Fixups,
133                                   const MCSubtargetInfo &STI) const;
134 
135   /// getThumbBranchTargetOpValue - Return encoding info for 24-bit
136   /// immediate Thumb2 direct branch target.
137   uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
138                                        SmallVectorImpl<MCFixup> &Fixups,
139                                        const MCSubtargetInfo &STI) const;
140 
141   /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
142   /// branch target.
143   uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
144                                      SmallVectorImpl<MCFixup> &Fixups,
145                                      const MCSubtargetInfo &STI) const;
146   uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
147                                  SmallVectorImpl<MCFixup> &Fixups,
148                                  const MCSubtargetInfo &STI) const;
149   uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
150                                   SmallVectorImpl<MCFixup> &Fixups,
151                                   const MCSubtargetInfo &STI) const;
152 
153   /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
154   /// ADR label target.
155   uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
156                               SmallVectorImpl<MCFixup> &Fixups,
157                               const MCSubtargetInfo &STI) const;
158   uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
159                               SmallVectorImpl<MCFixup> &Fixups,
160                               const MCSubtargetInfo &STI) const;
161   uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
162                               SmallVectorImpl<MCFixup> &Fixups,
163                               const MCSubtargetInfo &STI) const;
164 
165   uint32_t getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
166                             SmallVectorImpl<MCFixup> &Fixups,
167                             const MCSubtargetInfo &STI) const;
168 
169   /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
170   /// operand.
171   uint32_t getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
172                                  SmallVectorImpl<MCFixup> &Fixups,
173                                  const MCSubtargetInfo &STI) const;
174 
175   /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
176   /// operand.
177   uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
178                                    SmallVectorImpl<MCFixup> &Fixups,
179                                    const MCSubtargetInfo &STI) const;
180 
181   /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
182   uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
183                                          SmallVectorImpl<MCFixup> &Fixups,
184                                          const MCSubtargetInfo &STI) const;
185 
186   /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
187   /// operand.
188   uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
189                                    SmallVectorImpl<MCFixup> &Fixups,
190                                    const MCSubtargetInfo &STI) const;
191 
192   /// getT2AddrModeImm7s4OpValue - Return encoding info for 'reg +/- imm7<<2'
193   /// operand.
194   uint32_t getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
195                                       SmallVectorImpl<MCFixup> &Fixups,
196                                       const MCSubtargetInfo &STI) const;
197 
198   /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
199   /// operand.
200   uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
201                                    SmallVectorImpl<MCFixup> &Fixups,
202                                    const MCSubtargetInfo &STI) const;
203 
204   /// getT2ScaledImmOpValue - Return encoding info for '+/- immX<<Y'
205   /// operand.
206   template<unsigned Bits, unsigned Shift>
207   uint32_t getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
208                                  SmallVectorImpl<MCFixup> &Fixups,
209                                  const MCSubtargetInfo &STI) const;
210 
211   /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
212   /// operand.
213   uint32_t getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
214                                    SmallVectorImpl<MCFixup> &Fixups,
215                                    const MCSubtargetInfo &STI) const;
216 
217   /// getMveAddrModeQOpValue - Return encoding info for 'reg +/- imm7<<{shift}'
218   /// operand.
219   template<int shift>
220   uint32_t getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
221                                   SmallVectorImpl<MCFixup> &Fixups,
222                                   const MCSubtargetInfo &STI) const;
223 
224   /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
225   /// operand as needed by load/store instructions.
226   uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
227                                SmallVectorImpl<MCFixup> &Fixups,
228                                const MCSubtargetInfo &STI) const;
229 
230   /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
231   uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
232                                SmallVectorImpl<MCFixup> &Fixups,
233                                const MCSubtargetInfo &STI) const {
234     ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
235     switch (Mode) {
236     default: llvm_unreachable("Unknown addressing sub-mode!");
237     case ARM_AM::da: return 0;
238     case ARM_AM::ia: return 1;
239     case ARM_AM::db: return 2;
240     case ARM_AM::ib: return 3;
241     }
242   }
243 
244   /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
245   ///
246   unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
247     switch (ShOpc) {
248     case ARM_AM::no_shift:
249     case ARM_AM::lsl: return 0;
250     case ARM_AM::lsr: return 1;
251     case ARM_AM::asr: return 2;
252     case ARM_AM::ror:
253     case ARM_AM::rrx: return 3;
254     default:
255       llvm_unreachable("Invalid ShiftOpc!");
256     }
257   }
258 
259   /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
260   uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
261                                      SmallVectorImpl<MCFixup> &Fixups,
262                                      const MCSubtargetInfo &STI) const;
263 
264   /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
265   uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
266                                 SmallVectorImpl<MCFixup> &Fixups,
267                                 const MCSubtargetInfo &STI) const;
268 
269   /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
270   uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
271                                      SmallVectorImpl<MCFixup> &Fixups,
272                                      const MCSubtargetInfo &STI) const;
273 
274   /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
275   uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
276                                SmallVectorImpl<MCFixup> &Fixups,
277                                const MCSubtargetInfo &STI) const;
278 
279   /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
280   /// operand.
281   uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
282                                      SmallVectorImpl<MCFixup> &Fixups,
283                                      const MCSubtargetInfo &STI) const;
284 
285   /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
286   uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
287                                 SmallVectorImpl<MCFixup> &Fixups,
288                                 const MCSubtargetInfo &STI) const;
289 
290   /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
291   uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
292                                 SmallVectorImpl<MCFixup> &Fixups,
293                                 const MCSubtargetInfo &STI) const;
294 
295   /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
296   uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
297                                SmallVectorImpl<MCFixup> &Fixups,
298                                const MCSubtargetInfo &STI) const;
299 
300   /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
301   uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
302                                SmallVectorImpl<MCFixup> &Fixups,
303                                const MCSubtargetInfo &STI) const;
304 
305   /// getCCOutOpValue - Return encoding of the 's' bit.
306   unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
307                            SmallVectorImpl<MCFixup> &Fixups,
308                            const MCSubtargetInfo &STI) const {
309     // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
310     // '1' respectively.
311     return MI.getOperand(Op).getReg() == ARM::CPSR;
312   }
313 
314   unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
315                             SmallVectorImpl<MCFixup> &Fixups,
316                             const MCSubtargetInfo &ST) const {
317     const MCOperand &MO = MI.getOperand(Op);
318 
319     // Support for fixups (MCFixup)
320     if (MO.isExpr()) {
321       const MCExpr *Expr = MO.getExpr();
322       // Fixups resolve to plain values that need to be encoded.
323       MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_mod_imm);
324       Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
325       return 0;
326     }
327 
328     // Immediate is already in its encoded format
329     return MO.getImm();
330   }
331 
332   /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
333   unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
334                            SmallVectorImpl<MCFixup> &Fixups,
335                            const MCSubtargetInfo &STI) const {
336     const MCOperand &MO = MI.getOperand(Op);
337 
338     // Support for fixups (MCFixup)
339     if (MO.isExpr()) {
340       const MCExpr *Expr = MO.getExpr();
341       // Fixups resolve to plain values that need to be encoded.
342       MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_so_imm);
343       Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
344       return 0;
345     }
346     unsigned SoImm = MO.getImm();
347     unsigned Encoded =  ARM_AM::getT2SOImmVal(SoImm);
348     assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
349     return Encoded;
350   }
351 
352   unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
353     SmallVectorImpl<MCFixup> &Fixups,
354     const MCSubtargetInfo &STI) const;
355   template<unsigned Bits, unsigned Shift>
356   unsigned getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
357     SmallVectorImpl<MCFixup> &Fixups,
358     const MCSubtargetInfo &STI) const;
359   unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
360     SmallVectorImpl<MCFixup> &Fixups,
361     const MCSubtargetInfo &STI) const;
362 
363   /// getSORegOpValue - Return an encoded so_reg shifted register value.
364   unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
365                            SmallVectorImpl<MCFixup> &Fixups,
366                            const MCSubtargetInfo &STI) const;
367   unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
368                            SmallVectorImpl<MCFixup> &Fixups,
369                            const MCSubtargetInfo &STI) const;
370   unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
371                              SmallVectorImpl<MCFixup> &Fixups,
372                              const MCSubtargetInfo &STI) const;
373 
374   unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
375                                    SmallVectorImpl<MCFixup> &Fixups,
376                                    const MCSubtargetInfo &STI) const {
377     return 64 - MI.getOperand(Op).getImm();
378   }
379 
380   unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
381                                       SmallVectorImpl<MCFixup> &Fixups,
382                                       const MCSubtargetInfo &STI) const;
383 
384   unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
385                                   SmallVectorImpl<MCFixup> &Fixups,
386                                   const MCSubtargetInfo &STI) const;
387   unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
388                                       SmallVectorImpl<MCFixup> &Fixups,
389                                       const MCSubtargetInfo &STI) const;
390   unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
391                                         SmallVectorImpl<MCFixup> &Fixups,
392                                         const MCSubtargetInfo &STI) const;
393   unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
394                                         SmallVectorImpl<MCFixup> &Fixups,
395                                         const MCSubtargetInfo &STI) const;
396   unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
397                                      SmallVectorImpl<MCFixup> &Fixups,
398                                      const MCSubtargetInfo &STI) const;
399 
400   unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
401                              SmallVectorImpl<MCFixup> &Fixups,
402                              const MCSubtargetInfo &STI) const;
403   unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
404                               SmallVectorImpl<MCFixup> &Fixups,
405                               const MCSubtargetInfo &STI) const;
406   unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
407                               SmallVectorImpl<MCFixup> &Fixups,
408                               const MCSubtargetInfo &STI) const;
409   unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
410                               SmallVectorImpl<MCFixup> &Fixups,
411                               const MCSubtargetInfo &STI) const;
412 
413   unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
414                                  SmallVectorImpl<MCFixup> &Fixups,
415                                  const MCSubtargetInfo &STI) const;
416 
417   unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
418                                       unsigned EncodedValue,
419                                       const MCSubtargetInfo &STI) const;
420   unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
421                                           unsigned EncodedValue,
422                                           const MCSubtargetInfo &STI) const;
423   unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
424                                     unsigned EncodedValue,
425                                     const MCSubtargetInfo &STI) const;
426   unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
427                                    unsigned EncodedValue,
428                                    const MCSubtargetInfo &STI) const;
429 
430   unsigned VFPThumb2PostEncoder(const MCInst &MI,
431                                 unsigned EncodedValue,
432                                 const MCSubtargetInfo &STI) const;
433 
434   uint32_t getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
435                               SmallVectorImpl<MCFixup> &Fixups,
436                               const MCSubtargetInfo &STI) const;
437 
438   void EmitByte(unsigned char C, raw_ostream &OS) const {
439     OS << (char)C;
440   }
441 
442   void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
443     // Output the constant in little endian byte order.
444     for (unsigned i = 0; i != Size; ++i) {
445       unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
446       EmitByte((Val >> Shift) & 0xff, OS);
447     }
448   }
449 
450   void encodeInstruction(const MCInst &MI, raw_ostream &OS,
451                          SmallVectorImpl<MCFixup> &Fixups,
452                          const MCSubtargetInfo &STI) const override;
453 
454   template <bool isNeg, ARM::Fixups fixup>
455   uint32_t getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
456                               SmallVectorImpl<MCFixup> &Fixups,
457                               const MCSubtargetInfo &STI) const;
458 
459   uint32_t getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
460                                    SmallVectorImpl<MCFixup> &Fixups,
461                                    const MCSubtargetInfo &STI) const;
462 
463   uint32_t getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
464                              SmallVectorImpl<MCFixup> &Fixups,
465                              const MCSubtargetInfo &STI) const;
466   uint32_t getRestrictedCondCodeOpValue(const MCInst &MI, unsigned OpIdx,
467                                         SmallVectorImpl<MCFixup> &Fixups,
468                                         const MCSubtargetInfo &STI) const;
469   template <unsigned size>
470   uint32_t getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
471                                         SmallVectorImpl<MCFixup> &Fixups,
472                                         const MCSubtargetInfo &STI) const;
473 };
474 
475 } // end anonymous namespace
476 
477 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
478 /// instructions, and rewrite them to their Thumb2 form if we are currently in
479 /// Thumb2 mode.
480 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
481                                                  unsigned EncodedValue,
482                                                  const MCSubtargetInfo &STI) const {
483   if (isThumb2(STI)) {
484     // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
485     // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
486     // set to 1111.
487     unsigned Bit24 = EncodedValue & 0x01000000;
488     unsigned Bit28 = Bit24 << 4;
489     EncodedValue &= 0xEFFFFFFF;
490     EncodedValue |= Bit28;
491     EncodedValue |= 0x0F000000;
492   }
493 
494   return EncodedValue;
495 }
496 
497 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
498 /// instructions, and rewrite them to their Thumb2 form if we are currently in
499 /// Thumb2 mode.
500 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
501                                                  unsigned EncodedValue,
502                                                  const MCSubtargetInfo &STI) const {
503   if (isThumb2(STI)) {
504     EncodedValue &= 0xF0FFFFFF;
505     EncodedValue |= 0x09000000;
506   }
507 
508   return EncodedValue;
509 }
510 
511 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
512 /// instructions, and rewrite them to their Thumb2 form if we are currently in
513 /// Thumb2 mode.
514 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
515                                                  unsigned EncodedValue,
516                                                  const MCSubtargetInfo &STI) const {
517   if (isThumb2(STI)) {
518     EncodedValue &= 0x00FFFFFF;
519     EncodedValue |= 0xEE000000;
520   }
521 
522   return EncodedValue;
523 }
524 
525 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
526 /// if we are in Thumb2.
527 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
528                                                  unsigned EncodedValue,
529                                                  const MCSubtargetInfo &STI) const {
530   if (isThumb2(STI)) {
531     EncodedValue |= 0xC000000; // Set bits 27-26
532   }
533 
534   return EncodedValue;
535 }
536 
537 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
538 /// them to their Thumb2 form if we are currently in Thumb2 mode.
539 unsigned ARMMCCodeEmitter::
540 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
541                      const MCSubtargetInfo &STI) const {
542   if (isThumb2(STI)) {
543     EncodedValue &= 0x0FFFFFFF;
544     EncodedValue |= 0xE0000000;
545   }
546   return EncodedValue;
547 }
548 
549 /// getMachineOpValue - Return binary encoding of operand. If the machine
550 /// operand requires relocation, record the relocation and return zero.
551 unsigned ARMMCCodeEmitter::
552 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
553                   SmallVectorImpl<MCFixup> &Fixups,
554                   const MCSubtargetInfo &STI) const {
555   if (MO.isReg()) {
556     unsigned Reg = MO.getReg();
557     unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
558 
559     // In NEON, Q registers are encoded as 2x their register number,
560     // because they're using the same indices as the D registers they
561     // overlap. In MVE, there are no 64-bit vector instructions, so
562     // the encodings all refer to Q-registers by their literal
563     // register number.
564 
565     if (STI.getFeatureBits()[ARM::HasMVEIntegerOps])
566       return RegNo;
567 
568     switch (Reg) {
569     default:
570       return RegNo;
571     case ARM::Q0:  case ARM::Q1:  case ARM::Q2:  case ARM::Q3:
572     case ARM::Q4:  case ARM::Q5:  case ARM::Q6:  case ARM::Q7:
573     case ARM::Q8:  case ARM::Q9:  case ARM::Q10: case ARM::Q11:
574     case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
575       return 2 * RegNo;
576     }
577   } else if (MO.isImm()) {
578     return static_cast<unsigned>(MO.getImm());
579   } else if (MO.isDFPImm()) {
580     return static_cast<unsigned>(APFloat(bit_cast<double>(MO.getDFPImm()))
581                                      .bitcastToAPInt()
582                                      .getHiBits(32)
583                                      .getLimitedValue());
584   }
585 
586   llvm_unreachable("Unable to encode MCOperand!");
587 }
588 
589 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
590 bool ARMMCCodeEmitter::
591 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
592                        unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
593                        const MCSubtargetInfo &STI) const {
594   const MCOperand &MO  = MI.getOperand(OpIdx);
595   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
596 
597   Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
598 
599   int32_t SImm = MO1.getImm();
600   bool isAdd = true;
601 
602   // Special value for #-0
603   if (SImm == INT32_MIN) {
604     SImm = 0;
605     isAdd = false;
606   }
607 
608   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
609   if (SImm < 0) {
610     SImm = -SImm;
611     isAdd = false;
612   }
613 
614   Imm = SImm;
615   return isAdd;
616 }
617 
618 /// getBranchTargetOpValue - Helper function to get the branch target operand,
619 /// which is either an immediate or requires a fixup.
620 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
621                                        unsigned FixupKind,
622                                        SmallVectorImpl<MCFixup> &Fixups,
623                                        const MCSubtargetInfo &STI) {
624   const MCOperand &MO = MI.getOperand(OpIdx);
625 
626   // If the destination is an immediate, we have nothing to do.
627   if (MO.isImm()) return MO.getImm();
628   assert(MO.isExpr() && "Unexpected branch target type!");
629   const MCExpr *Expr = MO.getExpr();
630   MCFixupKind Kind = MCFixupKind(FixupKind);
631   Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
632 
633   // All of the information is in the fixup.
634   return 0;
635 }
636 
637 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
638 // determined by negating them and XOR'ing them with bit 23.
639 static int32_t encodeThumbBLOffset(int32_t offset) {
640   offset >>= 1;
641   uint32_t S  = (offset & 0x800000) >> 23;
642   uint32_t J1 = (offset & 0x400000) >> 22;
643   uint32_t J2 = (offset & 0x200000) >> 21;
644   J1 = (~J1 & 0x1);
645   J2 = (~J2 & 0x1);
646   J1 ^= S;
647   J2 ^= S;
648 
649   offset &= ~0x600000;
650   offset |= J1 << 22;
651   offset |= J2 << 21;
652 
653   return offset;
654 }
655 
656 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
657 uint32_t ARMMCCodeEmitter::
658 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
659                         SmallVectorImpl<MCFixup> &Fixups,
660                         const MCSubtargetInfo &STI) const {
661   const MCOperand MO = MI.getOperand(OpIdx);
662   if (MO.isExpr())
663     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
664                                     Fixups, STI);
665   return encodeThumbBLOffset(MO.getImm());
666 }
667 
668 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
669 /// BLX branch target.
670 uint32_t ARMMCCodeEmitter::
671 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
672                          SmallVectorImpl<MCFixup> &Fixups,
673                          const MCSubtargetInfo &STI) const {
674   const MCOperand MO = MI.getOperand(OpIdx);
675   if (MO.isExpr())
676     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
677                                     Fixups, STI);
678   return encodeThumbBLOffset(MO.getImm());
679 }
680 
681 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
682 uint32_t ARMMCCodeEmitter::
683 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
684                         SmallVectorImpl<MCFixup> &Fixups,
685                         const MCSubtargetInfo &STI) const {
686   const MCOperand MO = MI.getOperand(OpIdx);
687   if (MO.isExpr())
688     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
689                                     Fixups, STI);
690   return (MO.getImm() >> 1);
691 }
692 
693 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
694 uint32_t ARMMCCodeEmitter::
695 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
696                          SmallVectorImpl<MCFixup> &Fixups,
697                          const MCSubtargetInfo &STI) const {
698   const MCOperand MO = MI.getOperand(OpIdx);
699   if (MO.isExpr())
700     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
701                                     Fixups, STI);
702   return (MO.getImm() >> 1);
703 }
704 
705 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
706 uint32_t ARMMCCodeEmitter::
707 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
708                         SmallVectorImpl<MCFixup> &Fixups,
709                         const MCSubtargetInfo &STI) const {
710   const MCOperand MO = MI.getOperand(OpIdx);
711   if (MO.isExpr())
712     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI);
713   return (MO.getImm() >> 1);
714 }
715 
716 /// Return true if this branch has a non-always predication
717 static bool HasConditionalBranch(const MCInst &MI) {
718   int NumOp = MI.getNumOperands();
719   if (NumOp >= 2) {
720     for (int i = 0; i < NumOp-1; ++i) {
721       const MCOperand &MCOp1 = MI.getOperand(i);
722       const MCOperand &MCOp2 = MI.getOperand(i + 1);
723       if (MCOp1.isImm() && MCOp2.isReg() &&
724           (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
725         if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
726           return true;
727       }
728     }
729   }
730   return false;
731 }
732 
733 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
734 /// target.
735 uint32_t ARMMCCodeEmitter::
736 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
737                        SmallVectorImpl<MCFixup> &Fixups,
738                        const MCSubtargetInfo &STI) const {
739   // FIXME: This really, really shouldn't use TargetMachine. We don't want
740   // coupling between MC and TM anywhere we can help it.
741   if (isThumb2(STI))
742     return
743       ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI);
744   return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
745 }
746 
747 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
748 /// target.
749 uint32_t ARMMCCodeEmitter::
750 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
751                           SmallVectorImpl<MCFixup> &Fixups,
752                           const MCSubtargetInfo &STI) const {
753   const MCOperand MO = MI.getOperand(OpIdx);
754   if (MO.isExpr()) {
755     if (HasConditionalBranch(MI))
756       return ::getBranchTargetOpValue(MI, OpIdx,
757                                       ARM::fixup_arm_condbranch, Fixups, STI);
758     return ::getBranchTargetOpValue(MI, OpIdx,
759                                     ARM::fixup_arm_uncondbranch, Fixups, STI);
760   }
761 
762   return MO.getImm() >> 2;
763 }
764 
765 uint32_t ARMMCCodeEmitter::
766 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
767                           SmallVectorImpl<MCFixup> &Fixups,
768                           const MCSubtargetInfo &STI) const {
769   const MCOperand MO = MI.getOperand(OpIdx);
770   if (MO.isExpr()) {
771     if (HasConditionalBranch(MI))
772       return ::getBranchTargetOpValue(MI, OpIdx,
773                                       ARM::fixup_arm_condbl, Fixups, STI);
774     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI);
775   }
776 
777   return MO.getImm() >> 2;
778 }
779 
780 uint32_t ARMMCCodeEmitter::
781 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
782                           SmallVectorImpl<MCFixup> &Fixups,
783                           const MCSubtargetInfo &STI) const {
784   const MCOperand MO = MI.getOperand(OpIdx);
785   if (MO.isExpr())
786     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI);
787 
788   return MO.getImm() >> 1;
789 }
790 
791 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
792 /// immediate branch target.
793 uint32_t ARMMCCodeEmitter::getThumbBranchTargetOpValue(
794     const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
795     const MCSubtargetInfo &STI) const {
796   unsigned Val = 0;
797   const MCOperand MO = MI.getOperand(OpIdx);
798 
799   if(MO.isExpr())
800     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI);
801   else
802     Val = MO.getImm() >> 1;
803 
804   bool I  = (Val & 0x800000);
805   bool J1 = (Val & 0x400000);
806   bool J2 = (Val & 0x200000);
807   if (I ^ J1)
808     Val &= ~0x400000;
809   else
810     Val |= 0x400000;
811 
812   if (I ^ J2)
813     Val &= ~0x200000;
814   else
815     Val |= 0x200000;
816 
817   return Val;
818 }
819 
820 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
821 /// ADR label target.
822 uint32_t ARMMCCodeEmitter::
823 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
824                    SmallVectorImpl<MCFixup> &Fixups,
825                    const MCSubtargetInfo &STI) const {
826   const MCOperand MO = MI.getOperand(OpIdx);
827   if (MO.isExpr())
828     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
829                                     Fixups, STI);
830   int64_t offset = MO.getImm();
831   uint32_t Val = 0x2000;
832 
833   int SoImmVal;
834   if (offset == INT32_MIN) {
835     Val = 0x1000;
836     SoImmVal = 0;
837   } else if (offset < 0) {
838     Val = 0x1000;
839     offset *= -1;
840     SoImmVal = ARM_AM::getSOImmVal(offset);
841     if(SoImmVal == -1) {
842       Val = 0x2000;
843       offset *= -1;
844       SoImmVal = ARM_AM::getSOImmVal(offset);
845     }
846   } else {
847     SoImmVal = ARM_AM::getSOImmVal(offset);
848     if(SoImmVal == -1) {
849       Val = 0x1000;
850       offset *= -1;
851       SoImmVal = ARM_AM::getSOImmVal(offset);
852     }
853   }
854 
855   assert(SoImmVal != -1 && "Not a valid so_imm value!");
856 
857   Val |= SoImmVal;
858   return Val;
859 }
860 
861 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
862 /// target.
863 uint32_t ARMMCCodeEmitter::
864 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
865                    SmallVectorImpl<MCFixup> &Fixups,
866                    const MCSubtargetInfo &STI) const {
867   const MCOperand MO = MI.getOperand(OpIdx);
868   if (MO.isExpr())
869     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
870                                     Fixups, STI);
871   int32_t Val = MO.getImm();
872   if (Val == INT32_MIN)
873     Val = 0x1000;
874   else if (Val < 0) {
875     Val *= -1;
876     Val |= 0x1000;
877   }
878   return Val;
879 }
880 
881 /// getITMaskOpValue - Return the architectural encoding of an IT
882 /// predication mask, given the MCOperand format.
883 uint32_t ARMMCCodeEmitter::
884 getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
885                  SmallVectorImpl<MCFixup> &Fixups,
886                  const MCSubtargetInfo &STI) const {
887   const MCOperand MaskMO = MI.getOperand(OpIdx);
888   assert(MaskMO.isImm() && "Unexpected operand type!");
889 
890   unsigned Mask = MaskMO.getImm();
891 
892   // IT masks are encoded as a sequence of replacement low-order bits
893   // for the condition code. So if the low bit of the starting
894   // condition code is 1, then we have to flip all the bits above the
895   // terminating bit (which is the lowest 1 bit).
896   assert(OpIdx > 0 && "IT mask appears first!");
897   const MCOperand CondMO = MI.getOperand(OpIdx-1);
898   assert(CondMO.isImm() && "Unexpected operand type!");
899   if (CondMO.getImm() & 1) {
900     unsigned LowBit = Mask & -Mask;
901     unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
902     Mask ^= BitsAboveLowBit;
903   }
904 
905   return Mask;
906 }
907 
908 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
909 /// target.
910 uint32_t ARMMCCodeEmitter::
911 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
912                    SmallVectorImpl<MCFixup> &Fixups,
913                    const MCSubtargetInfo &STI) const {
914   const MCOperand MO = MI.getOperand(OpIdx);
915   if (MO.isExpr())
916     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
917                                     Fixups, STI);
918   return MO.getImm();
919 }
920 
921 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
922 /// operand.
923 uint32_t ARMMCCodeEmitter::
924 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
925                               SmallVectorImpl<MCFixup> &,
926                               const MCSubtargetInfo &STI) const {
927   // [Rn, Rm]
928   //   {5-3} = Rm
929   //   {2-0} = Rn
930   const MCOperand &MO1 = MI.getOperand(OpIdx);
931   const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
932   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
933   unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
934   return (Rm << 3) | Rn;
935 }
936 
937 /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
938 /// operand.
939 uint32_t
940 ARMMCCodeEmitter::getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
941                                         SmallVectorImpl<MCFixup> &Fixups,
942                                         const MCSubtargetInfo &STI) const {
943   // {4-0} = szimm5
944   // The value we are trying to encode is an immediate between either the
945   // range of [1-7] or [1-15] depending on whether we are dealing with the
946   // u8/s8 or the u16/s16 variants respectively.
947   // This value is encoded as follows, if ShiftImm is the value within those
948   // ranges then the encoding szimm5 = ShiftImm + size, where size is either 8
949   // or 16.
950 
951   unsigned Size, ShiftImm;
952   switch(MI.getOpcode()) {
953     case ARM::MVE_VSHLL_imms16bh:
954     case ARM::MVE_VSHLL_imms16th:
955     case ARM::MVE_VSHLL_immu16bh:
956     case ARM::MVE_VSHLL_immu16th:
957       Size = 16;
958       break;
959     case ARM::MVE_VSHLL_imms8bh:
960     case ARM::MVE_VSHLL_imms8th:
961     case ARM::MVE_VSHLL_immu8bh:
962     case ARM::MVE_VSHLL_immu8th:
963       Size = 8;
964       break;
965     default:
966       llvm_unreachable("Use of operand not supported by this instruction");
967   }
968   ShiftImm = MI.getOperand(OpIdx).getImm();
969   return Size + ShiftImm;
970 }
971 
972 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
973 uint32_t ARMMCCodeEmitter::
974 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
975                         SmallVectorImpl<MCFixup> &Fixups,
976                         const MCSubtargetInfo &STI) const {
977   // {17-13} = reg
978   // {12}    = (U)nsigned (add == '1', sub == '0')
979   // {11-0}  = imm12
980   unsigned Reg, Imm12;
981   bool isAdd = true;
982   // If The first operand isn't a register, we have a label reference.
983   const MCOperand &MO = MI.getOperand(OpIdx);
984   if (!MO.isReg()) {
985     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
986     Imm12 = 0;
987 
988     if (MO.isExpr()) {
989       const MCExpr *Expr = MO.getExpr();
990       isAdd = false ; // 'U' bit is set as part of the fixup.
991 
992       MCFixupKind Kind;
993       if (isThumb2(STI))
994         Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
995       else
996         Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
997       Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
998 
999       ++MCNumCPRelocations;
1000     } else {
1001       Reg = ARM::PC;
1002       int32_t Offset = MO.getImm();
1003       if (Offset == INT32_MIN) {
1004         Offset = 0;
1005         isAdd = false;
1006       } else if (Offset < 0) {
1007         Offset *= -1;
1008         isAdd = false;
1009       }
1010       Imm12 = Offset;
1011     }
1012   } else
1013     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
1014 
1015   uint32_t Binary = Imm12 & 0xfff;
1016   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1017   if (isAdd)
1018     Binary |= (1 << 12);
1019   Binary |= (Reg << 13);
1020   return Binary;
1021 }
1022 
1023 template<unsigned Bits, unsigned Shift>
1024 uint32_t ARMMCCodeEmitter::
1025 getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
1026                       SmallVectorImpl<MCFixup> &Fixups,
1027                       const MCSubtargetInfo &STI) const {
1028   // FIXME: The immediate operand should have already been encoded like this
1029   // before ever getting here. The encoder method should just need to combine
1030   // the MI operands for the register and the offset into a single
1031   // representation for the complex operand in the .td file. This isn't just
1032   // style, unfortunately. As-is, we can't represent the distinct encoding
1033   // for #-0.
1034 
1035   // {Bits}    = (U)nsigned (add == '1', sub == '0')
1036   // {(Bits-1)-0}  = immediate
1037   int32_t Imm = MI.getOperand(OpIdx).getImm();
1038   bool isAdd = Imm >= 0;
1039 
1040   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1041   if (Imm < 0)
1042     Imm = -(uint32_t)Imm;
1043 
1044   Imm >>= Shift;
1045 
1046   uint32_t Binary = Imm & ((1U << Bits) - 1);
1047   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1048   if (isAdd)
1049     Binary |= (1U << Bits);
1050   return Binary;
1051 }
1052 
1053 /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
1054 /// operand.
1055 uint32_t ARMMCCodeEmitter::
1056 getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
1057                         SmallVectorImpl<MCFixup> &Fixups,
1058                         const MCSubtargetInfo &STI) const {
1059     // {6-3} Rn
1060     // {2-0} Qm
1061     const MCOperand &M0 = MI.getOperand(OpIdx);
1062     const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1063 
1064     unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
1065     unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M1.getReg());
1066 
1067     assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
1068 
1069     return (Rn << 3) | Qm;
1070 }
1071 
1072 /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
1073 /// operand.
1074 template<int shift>
1075 uint32_t ARMMCCodeEmitter::
1076 getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
1077                         SmallVectorImpl<MCFixup> &Fixups,
1078                         const MCSubtargetInfo &STI) const {
1079     // {10-8} Qm
1080     // {7-0} Imm
1081     const MCOperand &M0 = MI.getOperand(OpIdx);
1082     const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1083 
1084     unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
1085     int32_t Imm = M1.getImm();
1086 
1087     bool isAdd = Imm >= 0;
1088 
1089     Imm >>= shift;
1090 
1091     if (!isAdd)
1092       Imm = -(uint32_t)Imm;
1093 
1094     Imm &= 0x7f;
1095 
1096     if (isAdd)
1097       Imm |= 0x80;
1098 
1099     assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
1100 
1101     return (Qm << 8) | Imm;
1102 }
1103 
1104 /// getT2AddrModeImm8s4OpValue - Return encoding info for
1105 /// 'reg +/- imm8<<2' operand.
1106 uint32_t ARMMCCodeEmitter::
1107 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
1108                         SmallVectorImpl<MCFixup> &Fixups,
1109                         const MCSubtargetInfo &STI) const {
1110   // {12-9} = reg
1111   // {8}    = (U)nsigned (add == '1', sub == '0')
1112   // {7-0}  = imm8
1113   unsigned Reg, Imm8;
1114   bool isAdd = true;
1115   // If The first operand isn't a register, we have a label reference.
1116   const MCOperand &MO = MI.getOperand(OpIdx);
1117   if (!MO.isReg()) {
1118     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1119     Imm8 = 0;
1120     isAdd = false ; // 'U' bit is set as part of the fixup.
1121 
1122     assert(MO.isExpr() && "Unexpected machine operand type!");
1123     const MCExpr *Expr = MO.getExpr();
1124     MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1125     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1126 
1127     ++MCNumCPRelocations;
1128   } else
1129     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1130 
1131   // FIXME: The immediate operand should have already been encoded like this
1132   // before ever getting here. The encoder method should just need to combine
1133   // the MI operands for the register and the offset into a single
1134   // representation for the complex operand in the .td file. This isn't just
1135   // style, unfortunately. As-is, we can't represent the distinct encoding
1136   // for #-0.
1137   uint32_t Binary = (Imm8 >> 2) & 0xff;
1138   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1139   if (isAdd)
1140     Binary |= (1 << 8);
1141   Binary |= (Reg << 9);
1142   return Binary;
1143 }
1144 
1145 /// getT2AddrModeImm7s4OpValue - Return encoding info for
1146 /// 'reg +/- imm7<<2' operand.
1147 uint32_t
1148 ARMMCCodeEmitter::getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
1149                                              SmallVectorImpl<MCFixup> &Fixups,
1150                                              const MCSubtargetInfo &STI) const {
1151   // {11-8} = reg
1152   // {7}    = (A)dd (add == '1', sub == '0')
1153   // {6-0}  = imm7
1154   unsigned Reg, Imm7;
1155   // If The first operand isn't a register, we have a label reference.
1156   bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm7, Fixups, STI);
1157 
1158   // FIXME: The immediate operand should have already been encoded like this
1159   // before ever getting here. The encoder method should just need to combine
1160   // the MI operands for the register and the offset into a single
1161   // representation for the complex operand in the .td file. This isn't just
1162   // style, unfortunately. As-is, we can't represent the distinct encoding
1163   // for #-0.
1164   uint32_t Binary = (Imm7 >> 2) & 0xff;
1165   // Immediate is always encoded as positive. The 'A' bit controls add vs sub.
1166   if (isAdd)
1167     Binary |= (1 << 7);
1168   Binary |= (Reg << 8);
1169   return Binary;
1170 }
1171 
1172 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
1173 /// 'reg + imm8<<2' operand.
1174 uint32_t ARMMCCodeEmitter::
1175 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
1176                         SmallVectorImpl<MCFixup> &Fixups,
1177                         const MCSubtargetInfo &STI) const {
1178   // {11-8} = reg
1179   // {7-0}  = imm8
1180   const MCOperand &MO = MI.getOperand(OpIdx);
1181   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1182   unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1183   unsigned Imm8 = MO1.getImm();
1184   return (Reg << 8) | Imm8;
1185 }
1186 
1187 uint32_t
1188 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
1189                                       SmallVectorImpl<MCFixup> &Fixups,
1190                                       const MCSubtargetInfo &STI) const {
1191   // {20-16} = imm{15-12}
1192   // {11-0}  = imm{11-0}
1193   const MCOperand &MO = MI.getOperand(OpIdx);
1194   if (MO.isImm())
1195     // Hi / lo 16 bits already extracted during earlier passes.
1196     return static_cast<unsigned>(MO.getImm());
1197 
1198   // Handle :upper16: and :lower16: assembly prefixes.
1199   const MCExpr *E = MO.getExpr();
1200   MCFixupKind Kind;
1201   if (E->getKind() == MCExpr::Target) {
1202     const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
1203     E = ARM16Expr->getSubExpr();
1204 
1205     if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) {
1206       const int64_t Value = MCE->getValue();
1207       if (Value > UINT32_MAX)
1208         report_fatal_error("constant value truncated (limited to 32-bit)");
1209 
1210       switch (ARM16Expr->getKind()) {
1211       case ARMMCExpr::VK_ARM_HI16:
1212         return (int32_t(Value) & 0xffff0000) >> 16;
1213       case ARMMCExpr::VK_ARM_LO16:
1214         return (int32_t(Value) & 0x0000ffff);
1215       default: llvm_unreachable("Unsupported ARMFixup");
1216       }
1217     }
1218 
1219     switch (ARM16Expr->getKind()) {
1220     default: llvm_unreachable("Unsupported ARMFixup");
1221     case ARMMCExpr::VK_ARM_HI16:
1222       Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movt_hi16
1223                                       : ARM::fixup_arm_movt_hi16);
1224       break;
1225     case ARMMCExpr::VK_ARM_LO16:
1226       Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movw_lo16
1227                                       : ARM::fixup_arm_movw_lo16);
1228       break;
1229     }
1230 
1231     Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc()));
1232     return 0;
1233   }
1234   // If the expression doesn't have :upper16: or :lower16: on it,
1235   // it's just a plain immediate expression, previously those evaluated to
1236   // the lower 16 bits of the expression regardless of whether
1237   // we have a movt or a movw, but that led to misleadingly results.
1238   // This is disallowed in the AsmParser in validateInstruction()
1239   // so this should never happen.
1240   llvm_unreachable("expression without :upper16: or :lower16:");
1241 }
1242 
1243 uint32_t ARMMCCodeEmitter::
1244 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1245                     SmallVectorImpl<MCFixup> &Fixups,
1246                     const MCSubtargetInfo &STI) const {
1247   const MCOperand &MO = MI.getOperand(OpIdx);
1248   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1249   const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1250   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1251   unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1252   unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
1253   bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
1254   ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
1255   unsigned SBits = getShiftOp(ShOp);
1256 
1257   // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1258   // amount. However, it would be an easy mistake to make so check here.
1259   assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
1260 
1261   // {16-13} = Rn
1262   // {12}    = isAdd
1263   // {11-0}  = shifter
1264   //  {3-0}  = Rm
1265   //  {4}    = 0
1266   //  {6-5}  = type
1267   //  {11-7} = imm
1268   uint32_t Binary = Rm;
1269   Binary |= Rn << 13;
1270   Binary |= SBits << 5;
1271   Binary |= ShImm << 7;
1272   if (isAdd)
1273     Binary |= 1 << 12;
1274   return Binary;
1275 }
1276 
1277 uint32_t ARMMCCodeEmitter::
1278 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1279                           SmallVectorImpl<MCFixup> &Fixups,
1280                           const MCSubtargetInfo &STI) const {
1281   // {13}     1 == imm12, 0 == Rm
1282   // {12}     isAdd
1283   // {11-0}   imm12/Rm
1284   const MCOperand &MO = MI.getOperand(OpIdx);
1285   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1286   unsigned Imm = MO1.getImm();
1287   bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1288   bool isReg = MO.getReg() != 0;
1289   uint32_t Binary = ARM_AM::getAM2Offset(Imm);
1290   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
1291   if (isReg) {
1292     ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
1293     Binary <<= 7;                    // Shift amount is bits [11:7]
1294     Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1295     Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1296   }
1297   return Binary | (isAdd << 12) | (isReg << 13);
1298 }
1299 
1300 uint32_t ARMMCCodeEmitter::
1301 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1302                      SmallVectorImpl<MCFixup> &Fixups,
1303                      const MCSubtargetInfo &STI) const {
1304   // {4}      isAdd
1305   // {3-0}    Rm
1306   const MCOperand &MO = MI.getOperand(OpIdx);
1307   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1308   bool isAdd = MO1.getImm() != 0;
1309   return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
1310 }
1311 
1312 uint32_t ARMMCCodeEmitter::
1313 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1314                           SmallVectorImpl<MCFixup> &Fixups,
1315                           const MCSubtargetInfo &STI) const {
1316   // {9}      1 == imm8, 0 == Rm
1317   // {8}      isAdd
1318   // {7-4}    imm7_4/zero
1319   // {3-0}    imm3_0/Rm
1320   const MCOperand &MO = MI.getOperand(OpIdx);
1321   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1322   unsigned Imm = MO1.getImm();
1323   bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1324   bool isImm = MO.getReg() == 0;
1325   uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1326   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1327   if (!isImm)
1328     Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1329   return Imm8 | (isAdd << 8) | (isImm << 9);
1330 }
1331 
1332 uint32_t ARMMCCodeEmitter::
1333 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1334                     SmallVectorImpl<MCFixup> &Fixups,
1335                     const MCSubtargetInfo &STI) const {
1336   // {13}     1 == imm8, 0 == Rm
1337   // {12-9}   Rn
1338   // {8}      isAdd
1339   // {7-4}    imm7_4/zero
1340   // {3-0}    imm3_0/Rm
1341   const MCOperand &MO = MI.getOperand(OpIdx);
1342   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1343   const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1344 
1345   // If The first operand isn't a register, we have a label reference.
1346   if (!MO.isReg()) {
1347     unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1348 
1349     assert(MO.isExpr() && "Unexpected machine operand type!");
1350     const MCExpr *Expr = MO.getExpr();
1351     MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1352     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1353 
1354     ++MCNumCPRelocations;
1355     return (Rn << 9) | (1 << 13);
1356   }
1357   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1358   unsigned Imm = MO2.getImm();
1359   bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1360   bool isImm = MO1.getReg() == 0;
1361   uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1362   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1363   if (!isImm)
1364     Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1365   return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1366 }
1367 
1368 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1369 uint32_t ARMMCCodeEmitter::
1370 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1371                           SmallVectorImpl<MCFixup> &Fixups,
1372                           const MCSubtargetInfo &STI) const {
1373   // [SP, #imm]
1374   //   {7-0} = imm8
1375   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1376   assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1377          "Unexpected base register!");
1378 
1379   // The immediate is already shifted for the implicit zeroes, so no change
1380   // here.
1381   return MO1.getImm() & 0xff;
1382 }
1383 
1384 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1385 uint32_t ARMMCCodeEmitter::
1386 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1387                      SmallVectorImpl<MCFixup> &Fixups,
1388                      const MCSubtargetInfo &STI) const {
1389   // [Rn, #imm]
1390   //   {7-3} = imm5
1391   //   {2-0} = Rn
1392   const MCOperand &MO = MI.getOperand(OpIdx);
1393   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1394   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1395   unsigned Imm5 = MO1.getImm();
1396   return ((Imm5 & 0x1f) << 3) | Rn;
1397 }
1398 
1399 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1400 uint32_t ARMMCCodeEmitter::
1401 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1402                      SmallVectorImpl<MCFixup> &Fixups,
1403                      const MCSubtargetInfo &STI) const {
1404   const MCOperand MO = MI.getOperand(OpIdx);
1405   if (MO.isExpr())
1406     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI);
1407   return (MO.getImm() >> 2);
1408 }
1409 
1410 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
1411 uint32_t ARMMCCodeEmitter::
1412 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1413                     SmallVectorImpl<MCFixup> &Fixups,
1414                     const MCSubtargetInfo &STI) const {
1415   // {12-9} = reg
1416   // {8}    = (U)nsigned (add == '1', sub == '0')
1417   // {7-0}  = imm8
1418   unsigned Reg, Imm8;
1419   bool isAdd;
1420   // If The first operand isn't a register, we have a label reference.
1421   const MCOperand &MO = MI.getOperand(OpIdx);
1422   if (!MO.isReg()) {
1423     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1424     Imm8 = 0;
1425     isAdd = false; // 'U' bit is handled as part of the fixup.
1426 
1427     assert(MO.isExpr() && "Unexpected machine operand type!");
1428     const MCExpr *Expr = MO.getExpr();
1429     MCFixupKind Kind;
1430     if (isThumb2(STI))
1431       Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1432     else
1433       Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1434     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1435 
1436     ++MCNumCPRelocations;
1437   } else {
1438     EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1439     isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1440   }
1441 
1442   uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1443   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1444   if (isAdd)
1445     Binary |= (1 << 8);
1446   Binary |= (Reg << 9);
1447   return Binary;
1448 }
1449 
1450 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
1451 uint32_t ARMMCCodeEmitter::
1452 getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
1453                     SmallVectorImpl<MCFixup> &Fixups,
1454                     const MCSubtargetInfo &STI) const {
1455   // {12-9} = reg
1456   // {8}    = (U)nsigned (add == '1', sub == '0')
1457   // {7-0}  = imm8
1458   unsigned Reg, Imm8;
1459   bool isAdd;
1460   // If The first operand isn't a register, we have a label reference.
1461   const MCOperand &MO = MI.getOperand(OpIdx);
1462   if (!MO.isReg()) {
1463     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1464     Imm8 = 0;
1465     isAdd = false; // 'U' bit is handled as part of the fixup.
1466 
1467     assert(MO.isExpr() && "Unexpected machine operand type!");
1468     const MCExpr *Expr = MO.getExpr();
1469     MCFixupKind Kind;
1470     if (isThumb2(STI))
1471       Kind = MCFixupKind(ARM::fixup_t2_pcrel_9);
1472     else
1473       Kind = MCFixupKind(ARM::fixup_arm_pcrel_9);
1474     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1475 
1476     ++MCNumCPRelocations;
1477   } else {
1478     EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1479     isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1480   }
1481 
1482   uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1483   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1484   if (isAdd)
1485     Binary |= (1 << 8);
1486   Binary |= (Reg << 9);
1487   return Binary;
1488 }
1489 
1490 unsigned ARMMCCodeEmitter::
1491 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1492                 SmallVectorImpl<MCFixup> &Fixups,
1493                 const MCSubtargetInfo &STI) const {
1494   // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1495   // shifted. The second is Rs, the amount to shift by, and the third specifies
1496   // the type of the shift.
1497   //
1498   // {3-0} = Rm.
1499   // {4}   = 1
1500   // {6-5} = type
1501   // {11-8} = Rs
1502   // {7}    = 0
1503 
1504   const MCOperand &MO  = MI.getOperand(OpIdx);
1505   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1506   const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1507   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1508 
1509   // Encode Rm.
1510   unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1511 
1512   // Encode the shift opcode.
1513   unsigned SBits = 0;
1514   unsigned Rs = MO1.getReg();
1515   if (Rs) {
1516     // Set shift operand (bit[7:4]).
1517     // LSL - 0001
1518     // LSR - 0011
1519     // ASR - 0101
1520     // ROR - 0111
1521     switch (SOpc) {
1522     default: llvm_unreachable("Unknown shift opc!");
1523     case ARM_AM::lsl: SBits = 0x1; break;
1524     case ARM_AM::lsr: SBits = 0x3; break;
1525     case ARM_AM::asr: SBits = 0x5; break;
1526     case ARM_AM::ror: SBits = 0x7; break;
1527     }
1528   }
1529 
1530   Binary |= SBits << 4;
1531 
1532   // Encode the shift operation Rs.
1533   // Encode Rs bit[11:8].
1534   assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1535   return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
1536 }
1537 
1538 unsigned ARMMCCodeEmitter::
1539 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1540                 SmallVectorImpl<MCFixup> &Fixups,
1541                 const MCSubtargetInfo &STI) const {
1542   // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1543   // shifted. The second is the amount to shift by.
1544   //
1545   // {3-0} = Rm.
1546   // {4}   = 0
1547   // {6-5} = type
1548   // {11-7} = imm
1549 
1550   const MCOperand &MO  = MI.getOperand(OpIdx);
1551   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1552   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1553 
1554   // Encode Rm.
1555   unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1556 
1557   // Encode the shift opcode.
1558   unsigned SBits = 0;
1559 
1560   // Set shift operand (bit[6:4]).
1561   // LSL - 000
1562   // LSR - 010
1563   // ASR - 100
1564   // ROR - 110
1565   // RRX - 110 and bit[11:8] clear.
1566   switch (SOpc) {
1567   default: llvm_unreachable("Unknown shift opc!");
1568   case ARM_AM::lsl: SBits = 0x0; break;
1569   case ARM_AM::lsr: SBits = 0x2; break;
1570   case ARM_AM::asr: SBits = 0x4; break;
1571   case ARM_AM::ror: SBits = 0x6; break;
1572   case ARM_AM::rrx:
1573     Binary |= 0x60;
1574     return Binary;
1575   }
1576 
1577   // Encode shift_imm bit[11:7].
1578   Binary |= SBits << 4;
1579   unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1580   assert(Offset < 32 && "Offset must be in range 0-31!");
1581   return Binary | (Offset << 7);
1582 }
1583 
1584 
1585 unsigned ARMMCCodeEmitter::
1586 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1587                 SmallVectorImpl<MCFixup> &Fixups,
1588                 const MCSubtargetInfo &STI) const {
1589   const MCOperand &MO1 = MI.getOperand(OpNum);
1590   const MCOperand &MO2 = MI.getOperand(OpNum+1);
1591   const MCOperand &MO3 = MI.getOperand(OpNum+2);
1592 
1593   // Encoded as [Rn, Rm, imm].
1594   // FIXME: Needs fixup support.
1595   unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1596   Value <<= 4;
1597   Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1598   Value <<= 2;
1599   Value |= MO3.getImm();
1600 
1601   return Value;
1602 }
1603 
1604 template<unsigned Bits, unsigned Shift>
1605 unsigned ARMMCCodeEmitter::
1606 getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
1607                         SmallVectorImpl<MCFixup> &Fixups,
1608                         const MCSubtargetInfo &STI) const {
1609   const MCOperand &MO1 = MI.getOperand(OpNum);
1610   const MCOperand &MO2 = MI.getOperand(OpNum+1);
1611 
1612   // FIXME: Needs fixup support.
1613   unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1614 
1615   // If the immediate is B bits long, we need B+1 bits in order
1616   // to represent the (inverse of the) sign bit.
1617   Value <<= (Bits + 1);
1618   int32_t tmp = (int32_t)MO2.getImm();
1619   if (tmp == INT32_MIN) { // represents subtracting zero rather than adding it
1620     tmp = 0;
1621   } else if (tmp < 0) {
1622     tmp = abs(tmp);
1623   } else {
1624     Value |= (1U << Bits); // Set the ADD bit
1625   }
1626   Value |= (tmp >> Shift) & ((1U << Bits) - 1);
1627   return Value;
1628 }
1629 
1630 unsigned ARMMCCodeEmitter::
1631 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1632                          SmallVectorImpl<MCFixup> &Fixups,
1633                          const MCSubtargetInfo &STI) const {
1634   const MCOperand &MO1 = MI.getOperand(OpNum);
1635 
1636   // FIXME: Needs fixup support.
1637   unsigned Value = 0;
1638   int32_t tmp = (int32_t)MO1.getImm();
1639   if (tmp < 0)
1640     tmp = abs(tmp);
1641   else
1642     Value |= 256; // Set the ADD bit
1643   Value |= tmp & 255;
1644   return Value;
1645 }
1646 
1647 unsigned ARMMCCodeEmitter::
1648 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1649                 SmallVectorImpl<MCFixup> &Fixups,
1650                 const MCSubtargetInfo &STI) const {
1651   // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1652   // shifted. The second is the amount to shift by.
1653   //
1654   // {3-0} = Rm.
1655   // {4}   = 0
1656   // {6-5} = type
1657   // {11-7} = imm
1658 
1659   const MCOperand &MO  = MI.getOperand(OpIdx);
1660   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1661   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1662 
1663   // Encode Rm.
1664   unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1665 
1666   // Encode the shift opcode.
1667   unsigned SBits = 0;
1668   // Set shift operand (bit[6:4]).
1669   // LSL - 000
1670   // LSR - 010
1671   // ASR - 100
1672   // ROR - 110
1673   switch (SOpc) {
1674   default: llvm_unreachable("Unknown shift opc!");
1675   case ARM_AM::lsl: SBits = 0x0; break;
1676   case ARM_AM::lsr: SBits = 0x2; break;
1677   case ARM_AM::asr: SBits = 0x4; break;
1678   case ARM_AM::rrx: LLVM_FALLTHROUGH;
1679   case ARM_AM::ror: SBits = 0x6; break;
1680   }
1681 
1682   Binary |= SBits << 4;
1683   if (SOpc == ARM_AM::rrx)
1684     return Binary;
1685 
1686   // Encode shift_imm bit[11:7].
1687   return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1688 }
1689 
1690 unsigned ARMMCCodeEmitter::
1691 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1692                                SmallVectorImpl<MCFixup> &Fixups,
1693                                const MCSubtargetInfo &STI) const {
1694   // 10 bits. lower 5 bits are the lsb of the mask, high five bits are the
1695   // msb of the mask.
1696   const MCOperand &MO = MI.getOperand(Op);
1697   uint32_t v = ~MO.getImm();
1698   uint32_t lsb = countTrailingZeros(v);
1699   uint32_t msb = (32 - countLeadingZeros (v)) - 1;
1700   assert(v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1701   return lsb | (msb << 5);
1702 }
1703 
1704 unsigned ARMMCCodeEmitter::
1705 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1706                        SmallVectorImpl<MCFixup> &Fixups,
1707                        const MCSubtargetInfo &STI) const {
1708   // VLDM/VSTM/VSCCLRM:
1709   //   {12-8} = Vd
1710   //   {7-0}  = Number of registers
1711   //
1712   // LDM/STM:
1713   //   {15-0}  = Bitfield of GPRs.
1714   unsigned Reg = MI.getOperand(Op).getReg();
1715   bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1716   bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1717 
1718   unsigned Binary = 0;
1719 
1720   if (SPRRegs || DPRRegs) {
1721     // VLDM/VSTM/VSCCLRM
1722     unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1723     unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1724     Binary |= (RegNo & 0x1f) << 8;
1725 
1726     // Ignore VPR
1727     if (MI.getOpcode() == ARM::VSCCLRMD || MI.getOpcode() == ARM::VSCCLRMS)
1728       --NumRegs;
1729     if (SPRRegs)
1730       Binary |= NumRegs;
1731     else
1732       Binary |= NumRegs * 2;
1733   } else {
1734     const MCRegisterInfo &MRI = *CTX.getRegisterInfo();
1735     assert(is_sorted(drop_begin(MI, Op),
1736                      [&](const MCOperand &LHS, const MCOperand &RHS) {
1737                        return MRI.getEncodingValue(LHS.getReg()) <
1738                               MRI.getEncodingValue(RHS.getReg());
1739                      }));
1740     for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1741       unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
1742       Binary |= 1 << RegNo;
1743     }
1744   }
1745 
1746   return Binary;
1747 }
1748 
1749 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1750 /// with the alignment operand.
1751 unsigned ARMMCCodeEmitter::
1752 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1753                            SmallVectorImpl<MCFixup> &Fixups,
1754                            const MCSubtargetInfo &STI) const {
1755   const MCOperand &Reg = MI.getOperand(Op);
1756   const MCOperand &Imm = MI.getOperand(Op + 1);
1757 
1758   unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1759   unsigned Align = 0;
1760 
1761   switch (Imm.getImm()) {
1762   default: break;
1763   case 2:
1764   case 4:
1765   case 8:  Align = 0x01; break;
1766   case 16: Align = 0x02; break;
1767   case 32: Align = 0x03; break;
1768   }
1769 
1770   return RegNo | (Align << 4);
1771 }
1772 
1773 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1774 /// along  with the alignment operand for use in VST1 and VLD1 with size 32.
1775 unsigned ARMMCCodeEmitter::
1776 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1777                                     SmallVectorImpl<MCFixup> &Fixups,
1778                                     const MCSubtargetInfo &STI) const {
1779   const MCOperand &Reg = MI.getOperand(Op);
1780   const MCOperand &Imm = MI.getOperand(Op + 1);
1781 
1782   unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1783   unsigned Align = 0;
1784 
1785   switch (Imm.getImm()) {
1786   default: break;
1787   case 8:
1788   case 16:
1789   case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1790   case 2: Align = 0x00; break;
1791   case 4: Align = 0x03; break;
1792   }
1793 
1794   return RegNo | (Align << 4);
1795 }
1796 
1797 
1798 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1799 /// alignment operand for use in VLD-dup instructions.  This is the same as
1800 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1801 /// different for VLD4-dup.
1802 unsigned ARMMCCodeEmitter::
1803 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1804                               SmallVectorImpl<MCFixup> &Fixups,
1805                               const MCSubtargetInfo &STI) const {
1806   const MCOperand &Reg = MI.getOperand(Op);
1807   const MCOperand &Imm = MI.getOperand(Op + 1);
1808 
1809   unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1810   unsigned Align = 0;
1811 
1812   switch (Imm.getImm()) {
1813   default: break;
1814   case 2:
1815   case 4:
1816   case 8:  Align = 0x01; break;
1817   case 16: Align = 0x03; break;
1818   }
1819 
1820   return RegNo | (Align << 4);
1821 }
1822 
1823 unsigned ARMMCCodeEmitter::
1824 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1825                           SmallVectorImpl<MCFixup> &Fixups,
1826                           const MCSubtargetInfo &STI) const {
1827   const MCOperand &MO = MI.getOperand(Op);
1828   if (MO.getReg() == 0) return 0x0D;
1829   return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1830 }
1831 
1832 unsigned ARMMCCodeEmitter::
1833 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1834                   SmallVectorImpl<MCFixup> &Fixups,
1835                   const MCSubtargetInfo &STI) const {
1836   return 8 - MI.getOperand(Op).getImm();
1837 }
1838 
1839 unsigned ARMMCCodeEmitter::
1840 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1841                    SmallVectorImpl<MCFixup> &Fixups,
1842                    const MCSubtargetInfo &STI) const {
1843   return 16 - MI.getOperand(Op).getImm();
1844 }
1845 
1846 unsigned ARMMCCodeEmitter::
1847 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1848                    SmallVectorImpl<MCFixup> &Fixups,
1849                    const MCSubtargetInfo &STI) const {
1850   return 32 - MI.getOperand(Op).getImm();
1851 }
1852 
1853 unsigned ARMMCCodeEmitter::
1854 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1855                    SmallVectorImpl<MCFixup> &Fixups,
1856                    const MCSubtargetInfo &STI) const {
1857   return 64 - MI.getOperand(Op).getImm();
1858 }
1859 
1860 void ARMMCCodeEmitter::
1861 encodeInstruction(const MCInst &MI, raw_ostream &OS,
1862                   SmallVectorImpl<MCFixup> &Fixups,
1863                   const MCSubtargetInfo &STI) const {
1864   // Pseudo instructions don't get encoded.
1865   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1866   uint64_t TSFlags = Desc.TSFlags;
1867   if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1868     return;
1869 
1870   int Size;
1871   if (Desc.getSize() == 2 || Desc.getSize() == 4)
1872     Size = Desc.getSize();
1873   else
1874     llvm_unreachable("Unexpected instruction size!");
1875 
1876   uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1877   // Thumb 32-bit wide instructions need to emit the high order halfword
1878   // first.
1879   if (isThumb(STI) && Size == 4) {
1880     EmitConstant(Binary >> 16, 2, OS);
1881     EmitConstant(Binary & 0xffff, 2, OS);
1882   } else
1883     EmitConstant(Binary, Size, OS);
1884   ++MCNumEmitted;  // Keep track of the # of mi's emitted.
1885 }
1886 
1887 template <bool isNeg, ARM::Fixups fixup>
1888 uint32_t
1889 ARMMCCodeEmitter::getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
1890                                      SmallVectorImpl<MCFixup> &Fixups,
1891                                      const MCSubtargetInfo &STI) const {
1892   const MCOperand MO = MI.getOperand(OpIdx);
1893   if (MO.isExpr())
1894     return ::getBranchTargetOpValue(MI, OpIdx, fixup, Fixups, STI);
1895   return isNeg ? -(MO.getImm() >> 1) : (MO.getImm() >> 1);
1896 }
1897 
1898 uint32_t
1899 ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
1900                                           SmallVectorImpl<MCFixup> &Fixups,
1901                                           const MCSubtargetInfo &STI) const {
1902   const MCOperand MO = MI.getOperand(OpIdx);
1903   const MCOperand BranchMO = MI.getOperand(0);
1904 
1905   if (MO.isExpr()) {
1906     assert(BranchMO.isExpr());
1907     const MCExpr *DiffExpr = MCBinaryExpr::createSub(
1908         MO.getExpr(), BranchMO.getExpr(), CTX);
1909     MCFixupKind Kind = MCFixupKind(ARM::fixup_bfcsel_else_target);
1910     Fixups.push_back(llvm::MCFixup::create(0, DiffExpr, Kind, MI.getLoc()));
1911     return 0;
1912   }
1913 
1914   assert(MO.isImm() && BranchMO.isImm());
1915   int Diff = MO.getImm() - BranchMO.getImm();
1916   assert(Diff == 4 || Diff == 2);
1917 
1918   return Diff == 4;
1919 }
1920 
1921 uint32_t ARMMCCodeEmitter::getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
1922                                              SmallVectorImpl<MCFixup> &Fixups,
1923                                              const MCSubtargetInfo &STI)const {
1924   const MCOperand MO = MI.getOperand(OpIdx);
1925   assert(MO.isImm() && "Unexpected operand type!");
1926 
1927   int Value = MO.getImm();
1928   int Imm = 0;
1929 
1930   // VPT Masks are actually encoded as a series of invert/don't invert bits,
1931   // rather than true/false bits.
1932   unsigned PrevBit = 0;
1933   for (int i = 3; i >= 0; --i) {
1934     unsigned Bit = (Value >> i) & 1;
1935 
1936     // Check if we are at the end of the mask.
1937     if ((Value & ~(~0U << i)) == 0) {
1938       Imm |= (1 << i);
1939       break;
1940     }
1941 
1942     // Convert the bit in the mask based on the previous bit.
1943     if (Bit != PrevBit)
1944       Imm |= (1 << i);
1945 
1946     PrevBit = Bit;
1947   }
1948 
1949   return Imm;
1950 }
1951 
1952 uint32_t ARMMCCodeEmitter::getRestrictedCondCodeOpValue(
1953     const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
1954     const MCSubtargetInfo &STI) const {
1955 
1956   const MCOperand MO = MI.getOperand(OpIdx);
1957   assert(MO.isImm() && "Unexpected operand type!");
1958 
1959   switch (MO.getImm()) {
1960   default:
1961     assert(0 && "Unexpected Condition!");
1962     return 0;
1963   case ARMCC::HS:
1964   case ARMCC::EQ:
1965     return 0;
1966   case ARMCC::HI:
1967   case ARMCC::NE:
1968     return 1;
1969   case ARMCC::GE:
1970     return 4;
1971   case ARMCC::LT:
1972     return 5;
1973   case ARMCC::GT:
1974     return 6;
1975   case ARMCC::LE:
1976     return 7;
1977   }
1978 }
1979 
1980 uint32_t ARMMCCodeEmitter::
1981 getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
1982                    SmallVectorImpl<MCFixup> &Fixups,
1983                    const MCSubtargetInfo &STI) const {
1984   const MCOperand &MO = MI.getOperand(OpIdx);
1985   assert(MO.isImm() && "Unexpected operand type!");
1986   return countTrailingZeros((uint64_t)MO.getImm());
1987 }
1988 
1989 template <unsigned start>
1990 uint32_t ARMMCCodeEmitter::
1991 getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
1992                              SmallVectorImpl<MCFixup> &Fixups,
1993                              const MCSubtargetInfo &STI) const {
1994   const MCOperand MO = MI.getOperand(OpIdx);
1995   assert(MO.isImm() && "Unexpected operand type!");
1996 
1997   int Value = MO.getImm();
1998   return Value - start;
1999 }
2000 
2001 #include "ARMGenMCCodeEmitter.inc"
2002 
2003 MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
2004                                               const MCRegisterInfo &MRI,
2005                                               MCContext &Ctx) {
2006   return new ARMMCCodeEmitter(MCII, Ctx, true);
2007 }
2008 
2009 MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
2010                                               const MCRegisterInfo &MRI,
2011                                               MCContext &Ctx) {
2012   return new ARMMCCodeEmitter(MCII, Ctx, false);
2013 }
2014