1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARMMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MCTargetDesc/ARMMCTargetDesc.h"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMFixupKinds.h"
18 #include "MCTargetDesc/ARMMCExpr.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/MC/MCCodeEmitter.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCExpr.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/raw_ostream.h"
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "mccodeemitter"
34 
35 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
36 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
37 
38 namespace {
39 class ARMMCCodeEmitter : public MCCodeEmitter {
40   ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete;
41   void operator=(const ARMMCCodeEmitter &) = delete;
42   const MCInstrInfo &MCII;
43   const MCContext &CTX;
44   bool IsLittleEndian;
45 
46 public:
47   ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle)
48     : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
49   }
50 
51   ~ARMMCCodeEmitter() override {}
52 
53   bool isThumb(const MCSubtargetInfo &STI) const {
54     return STI.getFeatureBits()[ARM::ModeThumb];
55   }
56   bool isThumb2(const MCSubtargetInfo &STI) const {
57     return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
58   }
59   bool isTargetMachO(const MCSubtargetInfo &STI) const {
60     const Triple &TT = STI.getTargetTriple();
61     return TT.isOSBinFormatMachO();
62   }
63 
64   unsigned getMachineSoImmOpValue(unsigned SoImm) const;
65 
66   // getBinaryCodeForInstr - TableGen'erated function for getting the
67   // binary encoding for an instruction.
68   uint64_t getBinaryCodeForInstr(const MCInst &MI,
69                                  SmallVectorImpl<MCFixup> &Fixups,
70                                  const MCSubtargetInfo &STI) const;
71 
72   /// getMachineOpValue - Return binary encoding of operand. If the machine
73   /// operand requires relocation, record the relocation and return zero.
74   unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
75                              SmallVectorImpl<MCFixup> &Fixups,
76                              const MCSubtargetInfo &STI) const;
77 
78   /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
79   /// the specified operand. This is used for operands with :lower16: and
80   /// :upper16: prefixes.
81   uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
82                                SmallVectorImpl<MCFixup> &Fixups,
83                                const MCSubtargetInfo &STI) const;
84 
85   bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
86                               unsigned &Reg, unsigned &Imm,
87                               SmallVectorImpl<MCFixup> &Fixups,
88                               const MCSubtargetInfo &STI) const;
89 
90   /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
91   /// BL branch target.
92   uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
93                                    SmallVectorImpl<MCFixup> &Fixups,
94                                    const MCSubtargetInfo &STI) const;
95 
96   /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
97   /// BLX branch target.
98   uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
99                                     SmallVectorImpl<MCFixup> &Fixups,
100                                     const MCSubtargetInfo &STI) const;
101 
102   /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
103   uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
104                                    SmallVectorImpl<MCFixup> &Fixups,
105                                    const MCSubtargetInfo &STI) const;
106 
107   /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
108   uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
109                                     SmallVectorImpl<MCFixup> &Fixups,
110                                     const MCSubtargetInfo &STI) const;
111 
112   /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
113   uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
114                                    SmallVectorImpl<MCFixup> &Fixups,
115                                    const MCSubtargetInfo &STI) const;
116 
117   /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
118   /// branch target.
119   uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
120                                   SmallVectorImpl<MCFixup> &Fixups,
121                                   const MCSubtargetInfo &STI) const;
122 
123   /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
124   /// immediate Thumb2 direct branch target.
125   uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
126                                   SmallVectorImpl<MCFixup> &Fixups,
127                                   const MCSubtargetInfo &STI) const;
128 
129   /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
130   /// branch target.
131   uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
132                                      SmallVectorImpl<MCFixup> &Fixups,
133                                      const MCSubtargetInfo &STI) const;
134   uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
135                                  SmallVectorImpl<MCFixup> &Fixups,
136                                  const MCSubtargetInfo &STI) const;
137   uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
138                                   SmallVectorImpl<MCFixup> &Fixups,
139                                   const MCSubtargetInfo &STI) const;
140 
141   /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
142   /// ADR label target.
143   uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
144                               SmallVectorImpl<MCFixup> &Fixups,
145                               const MCSubtargetInfo &STI) const;
146   uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
147                               SmallVectorImpl<MCFixup> &Fixups,
148                               const MCSubtargetInfo &STI) const;
149   uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
150                               SmallVectorImpl<MCFixup> &Fixups,
151                               const MCSubtargetInfo &STI) const;
152 
153 
154   /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
155   /// operand.
156   uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
157                                    SmallVectorImpl<MCFixup> &Fixups,
158                                    const MCSubtargetInfo &STI) const;
159 
160   /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
161   uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
162                                          SmallVectorImpl<MCFixup> &Fixups,
163                                          const MCSubtargetInfo &STI) const;
164 
165   /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
166   /// operand.
167   uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
168                                    SmallVectorImpl<MCFixup> &Fixups,
169                                    const MCSubtargetInfo &STI) const;
170 
171   /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
172   /// operand.
173   uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
174                                    SmallVectorImpl<MCFixup> &Fixups,
175                                    const MCSubtargetInfo &STI) const;
176 
177   /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
178   /// operand.
179   uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
180                               SmallVectorImpl<MCFixup> &Fixups,
181                               const MCSubtargetInfo &STI) const;
182 
183 
184   /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
185   /// operand as needed by load/store instructions.
186   uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
187                                SmallVectorImpl<MCFixup> &Fixups,
188                                const MCSubtargetInfo &STI) const;
189 
190   /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
191   uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
192                                SmallVectorImpl<MCFixup> &Fixups,
193                                const MCSubtargetInfo &STI) const {
194     ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
195     switch (Mode) {
196     default: llvm_unreachable("Unknown addressing sub-mode!");
197     case ARM_AM::da: return 0;
198     case ARM_AM::ia: return 1;
199     case ARM_AM::db: return 2;
200     case ARM_AM::ib: return 3;
201     }
202   }
203   /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
204   ///
205   unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
206     switch (ShOpc) {
207     case ARM_AM::no_shift:
208     case ARM_AM::lsl: return 0;
209     case ARM_AM::lsr: return 1;
210     case ARM_AM::asr: return 2;
211     case ARM_AM::ror:
212     case ARM_AM::rrx: return 3;
213     }
214     llvm_unreachable("Invalid ShiftOpc!");
215   }
216 
217   /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
218   uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
219                                SmallVectorImpl<MCFixup> &Fixups,
220                                const MCSubtargetInfo &STI) const;
221 
222   /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
223   uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
224                                      SmallVectorImpl<MCFixup> &Fixups,
225                                      const MCSubtargetInfo &STI) const;
226 
227   /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
228   uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
229                                 SmallVectorImpl<MCFixup> &Fixups,
230                                 const MCSubtargetInfo &STI) const;
231 
232   /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
233   uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
234                                      SmallVectorImpl<MCFixup> &Fixups,
235                                      const MCSubtargetInfo &STI) const;
236 
237   /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
238   uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
239                                SmallVectorImpl<MCFixup> &Fixups,
240                                const MCSubtargetInfo &STI) const;
241 
242   /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
243   /// operand.
244   uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
245                                      SmallVectorImpl<MCFixup> &Fixups,
246                                      const MCSubtargetInfo &STI) const;
247 
248   /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
249   uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
250                                 SmallVectorImpl<MCFixup> &Fixups,
251                                 const MCSubtargetInfo &STI) const;
252 
253   /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
254   uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
255                                 SmallVectorImpl<MCFixup> &Fixups,
256                                 const MCSubtargetInfo &STI) const;
257 
258   /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
259   uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
260                                SmallVectorImpl<MCFixup> &Fixups,
261                                const MCSubtargetInfo &STI) const;
262 
263   /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
264   uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
265                                SmallVectorImpl<MCFixup> &Fixups,
266                                const MCSubtargetInfo &STI) const;
267 
268   /// getCCOutOpValue - Return encoding of the 's' bit.
269   unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
270                            SmallVectorImpl<MCFixup> &Fixups,
271                            const MCSubtargetInfo &STI) const {
272     // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
273     // '1' respectively.
274     return MI.getOperand(Op).getReg() == ARM::CPSR;
275   }
276 
277   /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
278   unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
279                            SmallVectorImpl<MCFixup> &Fixups,
280                            const MCSubtargetInfo &STI) const {
281 
282     const MCOperand &MO = MI.getOperand(Op);
283 
284     // We expect MO to be an immediate or an expression,
285     // if it is an immediate - that's fine, just encode the value.
286     // Otherwise - create a Fixup.
287     if (MO.isExpr()) {
288       const MCExpr *Expr = MO.getExpr();
289       // In instruction code this value always encoded as lowest 12 bits,
290       // so we don't have to perform any specific adjustments.
291       // Due to requirements of relocatable records we have to use FK_Data_4.
292       // See ARMELFObjectWriter::ExplicitRelSym and
293       //     ARMELFObjectWriter::GetRelocTypeInner for more details.
294       MCFixupKind Kind = MCFixupKind(FK_Data_4);
295       Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
296       return 0;
297     }
298 
299     unsigned SoImm = MO.getImm();
300     int SoImmVal = ARM_AM::getSOImmVal(SoImm);
301     assert(SoImmVal != -1 && "Not a valid so_imm value!");
302 
303     // Encode rotate_imm.
304     unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
305       << ARMII::SoRotImmShift;
306 
307     // Encode immed_8.
308     Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
309     return Binary;
310   }
311 
312   unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
313                             SmallVectorImpl<MCFixup> &Fixups,
314                             const MCSubtargetInfo &ST) const {
315     const MCOperand &MO = MI.getOperand(Op);
316 
317     // Support for fixups (MCFixup)
318     if (MO.isExpr()) {
319       const MCExpr *Expr = MO.getExpr();
320       // Fixups resolve to plain values that need to be encoded.
321       MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_mod_imm);
322       Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
323       return 0;
324     }
325 
326     // Immediate is already in its encoded format
327     return MO.getImm();
328   }
329 
330   /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
331   unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
332                            SmallVectorImpl<MCFixup> &Fixups,
333                            const MCSubtargetInfo &STI) const {
334     unsigned SoImm = MI.getOperand(Op).getImm();
335     unsigned Encoded =  ARM_AM::getT2SOImmVal(SoImm);
336     assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
337     return Encoded;
338   }
339 
340   unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
341     SmallVectorImpl<MCFixup> &Fixups,
342     const MCSubtargetInfo &STI) const;
343   unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
344     SmallVectorImpl<MCFixup> &Fixups,
345     const MCSubtargetInfo &STI) const;
346   unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
347     SmallVectorImpl<MCFixup> &Fixups,
348     const MCSubtargetInfo &STI) const;
349   unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
350     SmallVectorImpl<MCFixup> &Fixups,
351     const MCSubtargetInfo &STI) const;
352 
353   /// getSORegOpValue - Return an encoded so_reg shifted register value.
354   unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
355                            SmallVectorImpl<MCFixup> &Fixups,
356                            const MCSubtargetInfo &STI) const;
357   unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
358                            SmallVectorImpl<MCFixup> &Fixups,
359                            const MCSubtargetInfo &STI) const;
360   unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
361                              SmallVectorImpl<MCFixup> &Fixups,
362                              const MCSubtargetInfo &STI) const;
363 
364   unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
365                                    SmallVectorImpl<MCFixup> &Fixups,
366                                    const MCSubtargetInfo &STI) const {
367     return 64 - MI.getOperand(Op).getImm();
368   }
369 
370   unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
371                                       SmallVectorImpl<MCFixup> &Fixups,
372                                       const MCSubtargetInfo &STI) const;
373 
374   unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
375                                   SmallVectorImpl<MCFixup> &Fixups,
376                                   const MCSubtargetInfo &STI) const;
377   unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
378                                       SmallVectorImpl<MCFixup> &Fixups,
379                                       const MCSubtargetInfo &STI) const;
380   unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
381                                         SmallVectorImpl<MCFixup> &Fixups,
382                                         const MCSubtargetInfo &STI) const;
383   unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
384                                         SmallVectorImpl<MCFixup> &Fixups,
385                                         const MCSubtargetInfo &STI) const;
386   unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
387                                      SmallVectorImpl<MCFixup> &Fixups,
388                                      const MCSubtargetInfo &STI) const;
389 
390   unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
391                              SmallVectorImpl<MCFixup> &Fixups,
392                              const MCSubtargetInfo &STI) const;
393   unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
394                               SmallVectorImpl<MCFixup> &Fixups,
395                               const MCSubtargetInfo &STI) const;
396   unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
397                               SmallVectorImpl<MCFixup> &Fixups,
398                               const MCSubtargetInfo &STI) const;
399   unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
400                               SmallVectorImpl<MCFixup> &Fixups,
401                               const MCSubtargetInfo &STI) const;
402 
403   unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
404                                  SmallVectorImpl<MCFixup> &Fixups,
405                                  const MCSubtargetInfo &STI) const;
406 
407   unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
408                                       unsigned EncodedValue,
409                                       const MCSubtargetInfo &STI) const;
410   unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
411                                           unsigned EncodedValue,
412                                           const MCSubtargetInfo &STI) const;
413   unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
414                                     unsigned EncodedValue,
415                                     const MCSubtargetInfo &STI) const;
416   unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
417                                    unsigned EncodedValue,
418                                    const MCSubtargetInfo &STI) const;
419 
420   unsigned VFPThumb2PostEncoder(const MCInst &MI,
421                                 unsigned EncodedValue,
422                                 const MCSubtargetInfo &STI) const;
423 
424   void EmitByte(unsigned char C, raw_ostream &OS) const {
425     OS << (char)C;
426   }
427 
428   void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
429     // Output the constant in little endian byte order.
430     for (unsigned i = 0; i != Size; ++i) {
431       unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
432       EmitByte((Val >> Shift) & 0xff, OS);
433     }
434   }
435 
436   void encodeInstruction(const MCInst &MI, raw_ostream &OS,
437                          SmallVectorImpl<MCFixup> &Fixups,
438                          const MCSubtargetInfo &STI) const override;
439 };
440 
441 } // end anonymous namespace
442 
443 MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
444                                               const MCRegisterInfo &MRI,
445                                               MCContext &Ctx) {
446   return new ARMMCCodeEmitter(MCII, Ctx, true);
447 }
448 
449 MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
450                                               const MCRegisterInfo &MRI,
451                                               MCContext &Ctx) {
452   return new ARMMCCodeEmitter(MCII, Ctx, false);
453 }
454 
455 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
456 /// instructions, and rewrite them to their Thumb2 form if we are currently in
457 /// Thumb2 mode.
458 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
459                                                  unsigned EncodedValue,
460                                                  const MCSubtargetInfo &STI) const {
461   if (isThumb2(STI)) {
462     // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
463     // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
464     // set to 1111.
465     unsigned Bit24 = EncodedValue & 0x01000000;
466     unsigned Bit28 = Bit24 << 4;
467     EncodedValue &= 0xEFFFFFFF;
468     EncodedValue |= Bit28;
469     EncodedValue |= 0x0F000000;
470   }
471 
472   return EncodedValue;
473 }
474 
475 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
476 /// instructions, and rewrite them to their Thumb2 form if we are currently in
477 /// Thumb2 mode.
478 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
479                                                  unsigned EncodedValue,
480                                                  const MCSubtargetInfo &STI) const {
481   if (isThumb2(STI)) {
482     EncodedValue &= 0xF0FFFFFF;
483     EncodedValue |= 0x09000000;
484   }
485 
486   return EncodedValue;
487 }
488 
489 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
490 /// instructions, and rewrite them to their Thumb2 form if we are currently in
491 /// Thumb2 mode.
492 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
493                                                  unsigned EncodedValue,
494                                                  const MCSubtargetInfo &STI) const {
495   if (isThumb2(STI)) {
496     EncodedValue &= 0x00FFFFFF;
497     EncodedValue |= 0xEE000000;
498   }
499 
500   return EncodedValue;
501 }
502 
503 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
504 /// if we are in Thumb2.
505 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
506                                                  unsigned EncodedValue,
507                                                  const MCSubtargetInfo &STI) const {
508   if (isThumb2(STI)) {
509     EncodedValue |= 0xC000000; // Set bits 27-26
510   }
511 
512   return EncodedValue;
513 }
514 
515 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
516 /// them to their Thumb2 form if we are currently in Thumb2 mode.
517 unsigned ARMMCCodeEmitter::
518 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
519                      const MCSubtargetInfo &STI) const {
520   if (isThumb2(STI)) {
521     EncodedValue &= 0x0FFFFFFF;
522     EncodedValue |= 0xE0000000;
523   }
524   return EncodedValue;
525 }
526 
527 /// getMachineOpValue - Return binary encoding of operand. If the machine
528 /// operand requires relocation, record the relocation and return zero.
529 unsigned ARMMCCodeEmitter::
530 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
531                   SmallVectorImpl<MCFixup> &Fixups,
532                   const MCSubtargetInfo &STI) const {
533   if (MO.isReg()) {
534     unsigned Reg = MO.getReg();
535     unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
536 
537     // Q registers are encoded as 2x their register number.
538     switch (Reg) {
539     default:
540       return RegNo;
541     case ARM::Q0:  case ARM::Q1:  case ARM::Q2:  case ARM::Q3:
542     case ARM::Q4:  case ARM::Q5:  case ARM::Q6:  case ARM::Q7:
543     case ARM::Q8:  case ARM::Q9:  case ARM::Q10: case ARM::Q11:
544     case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
545       return 2 * RegNo;
546     }
547   } else if (MO.isImm()) {
548     return static_cast<unsigned>(MO.getImm());
549   } else if (MO.isFPImm()) {
550     return static_cast<unsigned>(APFloat(MO.getFPImm())
551                      .bitcastToAPInt().getHiBits(32).getLimitedValue());
552   }
553 
554   llvm_unreachable("Unable to encode MCOperand!");
555 }
556 
557 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
558 bool ARMMCCodeEmitter::
559 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
560                        unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
561  const MCSubtargetInfo &STI) const {
562   const MCOperand &MO  = MI.getOperand(OpIdx);
563   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
564 
565   Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
566 
567   int32_t SImm = MO1.getImm();
568   bool isAdd = true;
569 
570   // Special value for #-0
571   if (SImm == INT32_MIN) {
572     SImm = 0;
573     isAdd = false;
574   }
575 
576   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
577   if (SImm < 0) {
578     SImm = -SImm;
579     isAdd = false;
580   }
581 
582   Imm = SImm;
583   return isAdd;
584 }
585 
586 /// getBranchTargetOpValue - Helper function to get the branch target operand,
587 /// which is either an immediate or requires a fixup.
588 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
589                                        unsigned FixupKind,
590                                        SmallVectorImpl<MCFixup> &Fixups,
591                                        const MCSubtargetInfo &STI) {
592   const MCOperand &MO = MI.getOperand(OpIdx);
593 
594   // If the destination is an immediate, we have nothing to do.
595   if (MO.isImm()) return MO.getImm();
596   assert(MO.isExpr() && "Unexpected branch target type!");
597   const MCExpr *Expr = MO.getExpr();
598   MCFixupKind Kind = MCFixupKind(FixupKind);
599   Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
600 
601   // All of the information is in the fixup.
602   return 0;
603 }
604 
605 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
606 // determined by negating them and XOR'ing them with bit 23.
607 static int32_t encodeThumbBLOffset(int32_t offset) {
608   offset >>= 1;
609   uint32_t S  = (offset & 0x800000) >> 23;
610   uint32_t J1 = (offset & 0x400000) >> 22;
611   uint32_t J2 = (offset & 0x200000) >> 21;
612   J1 = (~J1 & 0x1);
613   J2 = (~J2 & 0x1);
614   J1 ^= S;
615   J2 ^= S;
616 
617   offset &= ~0x600000;
618   offset |= J1 << 22;
619   offset |= J2 << 21;
620 
621   return offset;
622 }
623 
624 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
625 uint32_t ARMMCCodeEmitter::
626 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
627                         SmallVectorImpl<MCFixup> &Fixups,
628                         const MCSubtargetInfo &STI) const {
629   const MCOperand MO = MI.getOperand(OpIdx);
630   if (MO.isExpr())
631     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
632                                     Fixups, STI);
633   return encodeThumbBLOffset(MO.getImm());
634 }
635 
636 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
637 /// BLX branch target.
638 uint32_t ARMMCCodeEmitter::
639 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
640                          SmallVectorImpl<MCFixup> &Fixups,
641                          const MCSubtargetInfo &STI) const {
642   const MCOperand MO = MI.getOperand(OpIdx);
643   if (MO.isExpr())
644     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
645                                     Fixups, STI);
646   return encodeThumbBLOffset(MO.getImm());
647 }
648 
649 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
650 uint32_t ARMMCCodeEmitter::
651 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
652                         SmallVectorImpl<MCFixup> &Fixups,
653                         const MCSubtargetInfo &STI) const {
654   const MCOperand MO = MI.getOperand(OpIdx);
655   if (MO.isExpr())
656     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
657                                     Fixups, STI);
658   return (MO.getImm() >> 1);
659 }
660 
661 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
662 uint32_t ARMMCCodeEmitter::
663 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
664                          SmallVectorImpl<MCFixup> &Fixups,
665                          const MCSubtargetInfo &STI) const {
666   const MCOperand MO = MI.getOperand(OpIdx);
667   if (MO.isExpr())
668     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
669                                     Fixups, STI);
670   return (MO.getImm() >> 1);
671 }
672 
673 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
674 uint32_t ARMMCCodeEmitter::
675 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
676                         SmallVectorImpl<MCFixup> &Fixups,
677                         const MCSubtargetInfo &STI) const {
678   const MCOperand MO = MI.getOperand(OpIdx);
679   if (MO.isExpr())
680     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI);
681   return (MO.getImm() >> 1);
682 }
683 
684 /// Return true if this branch has a non-always predication
685 static bool HasConditionalBranch(const MCInst &MI) {
686   int NumOp = MI.getNumOperands();
687   if (NumOp >= 2) {
688     for (int i = 0; i < NumOp-1; ++i) {
689       const MCOperand &MCOp1 = MI.getOperand(i);
690       const MCOperand &MCOp2 = MI.getOperand(i + 1);
691       if (MCOp1.isImm() && MCOp2.isReg() &&
692           (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
693         if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
694           return true;
695       }
696     }
697   }
698   return false;
699 }
700 
701 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
702 /// target.
703 uint32_t ARMMCCodeEmitter::
704 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
705                        SmallVectorImpl<MCFixup> &Fixups,
706                        const MCSubtargetInfo &STI) const {
707   // FIXME: This really, really shouldn't use TargetMachine. We don't want
708   // coupling between MC and TM anywhere we can help it.
709   if (isThumb2(STI))
710     return
711       ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI);
712   return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
713 }
714 
715 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
716 /// target.
717 uint32_t ARMMCCodeEmitter::
718 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
719                           SmallVectorImpl<MCFixup> &Fixups,
720                           const MCSubtargetInfo &STI) const {
721   const MCOperand MO = MI.getOperand(OpIdx);
722   if (MO.isExpr()) {
723     if (HasConditionalBranch(MI))
724       return ::getBranchTargetOpValue(MI, OpIdx,
725                                       ARM::fixup_arm_condbranch, Fixups, STI);
726     return ::getBranchTargetOpValue(MI, OpIdx,
727                                     ARM::fixup_arm_uncondbranch, Fixups, STI);
728   }
729 
730   return MO.getImm() >> 2;
731 }
732 
733 uint32_t ARMMCCodeEmitter::
734 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
735                           SmallVectorImpl<MCFixup> &Fixups,
736                           const MCSubtargetInfo &STI) const {
737   const MCOperand MO = MI.getOperand(OpIdx);
738   if (MO.isExpr()) {
739     if (HasConditionalBranch(MI))
740       return ::getBranchTargetOpValue(MI, OpIdx,
741                                       ARM::fixup_arm_condbl, Fixups, STI);
742     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI);
743   }
744 
745   return MO.getImm() >> 2;
746 }
747 
748 uint32_t ARMMCCodeEmitter::
749 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
750                           SmallVectorImpl<MCFixup> &Fixups,
751                           const MCSubtargetInfo &STI) const {
752   const MCOperand MO = MI.getOperand(OpIdx);
753   if (MO.isExpr())
754     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI);
755 
756   return MO.getImm() >> 1;
757 }
758 
759 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
760 /// immediate branch target.
761 uint32_t ARMMCCodeEmitter::
762 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
763                        SmallVectorImpl<MCFixup> &Fixups,
764                        const MCSubtargetInfo &STI) const {
765   unsigned Val = 0;
766   const MCOperand MO = MI.getOperand(OpIdx);
767 
768   if(MO.isExpr())
769     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI);
770   else
771     Val = MO.getImm() >> 1;
772 
773   bool I  = (Val & 0x800000);
774   bool J1 = (Val & 0x400000);
775   bool J2 = (Val & 0x200000);
776   if (I ^ J1)
777     Val &= ~0x400000;
778   else
779     Val |= 0x400000;
780 
781   if (I ^ J2)
782     Val &= ~0x200000;
783   else
784     Val |= 0x200000;
785 
786   return Val;
787 }
788 
789 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
790 /// ADR label target.
791 uint32_t ARMMCCodeEmitter::
792 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
793                    SmallVectorImpl<MCFixup> &Fixups,
794                    const MCSubtargetInfo &STI) const {
795   const MCOperand MO = MI.getOperand(OpIdx);
796   if (MO.isExpr())
797     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
798                                     Fixups, STI);
799   int64_t offset = MO.getImm();
800   uint32_t Val = 0x2000;
801 
802   int SoImmVal;
803   if (offset == INT32_MIN) {
804     Val = 0x1000;
805     SoImmVal = 0;
806   } else if (offset < 0) {
807     Val = 0x1000;
808     offset *= -1;
809     SoImmVal = ARM_AM::getSOImmVal(offset);
810     if(SoImmVal == -1) {
811       Val = 0x2000;
812       offset *= -1;
813       SoImmVal = ARM_AM::getSOImmVal(offset);
814     }
815   } else {
816     SoImmVal = ARM_AM::getSOImmVal(offset);
817     if(SoImmVal == -1) {
818       Val = 0x1000;
819       offset *= -1;
820       SoImmVal = ARM_AM::getSOImmVal(offset);
821     }
822   }
823 
824   assert(SoImmVal != -1 && "Not a valid so_imm value!");
825 
826   Val |= SoImmVal;
827   return Val;
828 }
829 
830 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
831 /// target.
832 uint32_t ARMMCCodeEmitter::
833 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
834                    SmallVectorImpl<MCFixup> &Fixups,
835                    const MCSubtargetInfo &STI) const {
836   const MCOperand MO = MI.getOperand(OpIdx);
837   if (MO.isExpr())
838     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
839                                     Fixups, STI);
840   int32_t Val = MO.getImm();
841   if (Val == INT32_MIN)
842     Val = 0x1000;
843   else if (Val < 0) {
844     Val *= -1;
845     Val |= 0x1000;
846   }
847   return Val;
848 }
849 
850 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
851 /// target.
852 uint32_t ARMMCCodeEmitter::
853 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
854                    SmallVectorImpl<MCFixup> &Fixups,
855                    const MCSubtargetInfo &STI) const {
856   const MCOperand MO = MI.getOperand(OpIdx);
857   if (MO.isExpr())
858     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
859                                     Fixups, STI);
860   return MO.getImm();
861 }
862 
863 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
864 /// operand.
865 uint32_t ARMMCCodeEmitter::
866 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
867                               SmallVectorImpl<MCFixup> &,
868                               const MCSubtargetInfo &STI) const {
869   // [Rn, Rm]
870   //   {5-3} = Rm
871   //   {2-0} = Rn
872   const MCOperand &MO1 = MI.getOperand(OpIdx);
873   const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
874   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
875   unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
876   return (Rm << 3) | Rn;
877 }
878 
879 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
880 uint32_t ARMMCCodeEmitter::
881 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
882                         SmallVectorImpl<MCFixup> &Fixups,
883                         const MCSubtargetInfo &STI) const {
884   // {17-13} = reg
885   // {12}    = (U)nsigned (add == '1', sub == '0')
886   // {11-0}  = imm12
887   unsigned Reg, Imm12;
888   bool isAdd = true;
889   // If The first operand isn't a register, we have a label reference.
890   const MCOperand &MO = MI.getOperand(OpIdx);
891   if (!MO.isReg()) {
892     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
893     Imm12 = 0;
894 
895     if (MO.isExpr()) {
896       const MCExpr *Expr = MO.getExpr();
897       isAdd = false ; // 'U' bit is set as part of the fixup.
898 
899       MCFixupKind Kind;
900       if (isThumb2(STI))
901         Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
902       else
903         Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
904       Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
905 
906       ++MCNumCPRelocations;
907     } else {
908       Reg = ARM::PC;
909       int32_t Offset = MO.getImm();
910       if (Offset == INT32_MIN) {
911         Offset = 0;
912         isAdd = false;
913       } else if (Offset < 0) {
914         Offset *= -1;
915         isAdd = false;
916       }
917       Imm12 = Offset;
918     }
919   } else
920     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
921 
922   uint32_t Binary = Imm12 & 0xfff;
923   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
924   if (isAdd)
925     Binary |= (1 << 12);
926   Binary |= (Reg << 13);
927   return Binary;
928 }
929 
930 /// getT2Imm8s4OpValue - Return encoding info for
931 /// '+/- imm8<<2' operand.
932 uint32_t ARMMCCodeEmitter::
933 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
934                    SmallVectorImpl<MCFixup> &Fixups,
935                    const MCSubtargetInfo &STI) const {
936   // FIXME: The immediate operand should have already been encoded like this
937   // before ever getting here. The encoder method should just need to combine
938   // the MI operands for the register and the offset into a single
939   // representation for the complex operand in the .td file. This isn't just
940   // style, unfortunately. As-is, we can't represent the distinct encoding
941   // for #-0.
942 
943   // {8}    = (U)nsigned (add == '1', sub == '0')
944   // {7-0}  = imm8
945   int32_t Imm8 = MI.getOperand(OpIdx).getImm();
946   bool isAdd = Imm8 >= 0;
947 
948   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
949   if (Imm8 < 0)
950     Imm8 = -(uint32_t)Imm8;
951 
952   // Scaled by 4.
953   Imm8 /= 4;
954 
955   uint32_t Binary = Imm8 & 0xff;
956   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
957   if (isAdd)
958     Binary |= (1 << 8);
959   return Binary;
960 }
961 
962 /// getT2AddrModeImm8s4OpValue - Return encoding info for
963 /// 'reg +/- imm8<<2' operand.
964 uint32_t ARMMCCodeEmitter::
965 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
966                         SmallVectorImpl<MCFixup> &Fixups,
967                         const MCSubtargetInfo &STI) const {
968   // {12-9} = reg
969   // {8}    = (U)nsigned (add == '1', sub == '0')
970   // {7-0}  = imm8
971   unsigned Reg, Imm8;
972   bool isAdd = true;
973   // If The first operand isn't a register, we have a label reference.
974   const MCOperand &MO = MI.getOperand(OpIdx);
975   if (!MO.isReg()) {
976     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
977     Imm8 = 0;
978     isAdd = false ; // 'U' bit is set as part of the fixup.
979 
980     assert(MO.isExpr() && "Unexpected machine operand type!");
981     const MCExpr *Expr = MO.getExpr();
982     MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
983     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
984 
985     ++MCNumCPRelocations;
986   } else
987     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
988 
989   // FIXME: The immediate operand should have already been encoded like this
990   // before ever getting here. The encoder method should just need to combine
991   // the MI operands for the register and the offset into a single
992   // representation for the complex operand in the .td file. This isn't just
993   // style, unfortunately. As-is, we can't represent the distinct encoding
994   // for #-0.
995   uint32_t Binary = (Imm8 >> 2) & 0xff;
996   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
997   if (isAdd)
998     Binary |= (1 << 8);
999   Binary |= (Reg << 9);
1000   return Binary;
1001 }
1002 
1003 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
1004 /// 'reg + imm8<<2' operand.
1005 uint32_t ARMMCCodeEmitter::
1006 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
1007                         SmallVectorImpl<MCFixup> &Fixups,
1008                         const MCSubtargetInfo &STI) const {
1009   // {11-8} = reg
1010   // {7-0}  = imm8
1011   const MCOperand &MO = MI.getOperand(OpIdx);
1012   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1013   unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1014   unsigned Imm8 = MO1.getImm();
1015   return (Reg << 8) | Imm8;
1016 }
1017 
1018 uint32_t
1019 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
1020                                       SmallVectorImpl<MCFixup> &Fixups,
1021                                       const MCSubtargetInfo &STI) const {
1022   // {20-16} = imm{15-12}
1023   // {11-0}  = imm{11-0}
1024   const MCOperand &MO = MI.getOperand(OpIdx);
1025   if (MO.isImm())
1026     // Hi / lo 16 bits already extracted during earlier passes.
1027     return static_cast<unsigned>(MO.getImm());
1028 
1029   // Handle :upper16: and :lower16: assembly prefixes.
1030   const MCExpr *E = MO.getExpr();
1031   MCFixupKind Kind;
1032   if (E->getKind() == MCExpr::Target) {
1033     const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
1034     E = ARM16Expr->getSubExpr();
1035 
1036     if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) {
1037       const int64_t Value = MCE->getValue();
1038       if (Value > UINT32_MAX)
1039         report_fatal_error("constant value truncated (limited to 32-bit)");
1040 
1041       switch (ARM16Expr->getKind()) {
1042       case ARMMCExpr::VK_ARM_HI16:
1043         return (int32_t(Value) & 0xffff0000) >> 16;
1044       case ARMMCExpr::VK_ARM_LO16:
1045         return (int32_t(Value) & 0x0000ffff);
1046       default: llvm_unreachable("Unsupported ARMFixup");
1047       }
1048     }
1049 
1050     switch (ARM16Expr->getKind()) {
1051     default: llvm_unreachable("Unsupported ARMFixup");
1052     case ARMMCExpr::VK_ARM_HI16:
1053       Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movt_hi16
1054                                       : ARM::fixup_arm_movt_hi16);
1055       break;
1056     case ARMMCExpr::VK_ARM_LO16:
1057       Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movw_lo16
1058                                       : ARM::fixup_arm_movw_lo16);
1059       break;
1060     }
1061 
1062     Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc()));
1063     return 0;
1064   }
1065   // If the expression doesn't have :upper16: or :lower16: on it,
1066   // it's just a plain immediate expression, previously those evaluated to
1067   // the lower 16 bits of the expression regardless of whether
1068   // we have a movt or a movw, but that led to misleadingly results.
1069   // This is disallowed in the AsmParser in validateInstruction()
1070   // so this should never happen.
1071   llvm_unreachable("expression without :upper16: or :lower16:");
1072 }
1073 
1074 uint32_t ARMMCCodeEmitter::
1075 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1076                     SmallVectorImpl<MCFixup> &Fixups,
1077                     const MCSubtargetInfo &STI) const {
1078   const MCOperand &MO = MI.getOperand(OpIdx);
1079   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1080   const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1081   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1082   unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1083   unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
1084   bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
1085   ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
1086   unsigned SBits = getShiftOp(ShOp);
1087 
1088   // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1089   // amount. However, it would be an easy mistake to make so check here.
1090   assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
1091 
1092   // {16-13} = Rn
1093   // {12}    = isAdd
1094   // {11-0}  = shifter
1095   //  {3-0}  = Rm
1096   //  {4}    = 0
1097   //  {6-5}  = type
1098   //  {11-7} = imm
1099   uint32_t Binary = Rm;
1100   Binary |= Rn << 13;
1101   Binary |= SBits << 5;
1102   Binary |= ShImm << 7;
1103   if (isAdd)
1104     Binary |= 1 << 12;
1105   return Binary;
1106 }
1107 
1108 uint32_t ARMMCCodeEmitter::
1109 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
1110                     SmallVectorImpl<MCFixup> &Fixups,
1111                     const MCSubtargetInfo &STI) const {
1112   // {17-14}  Rn
1113   // {13}     1 == imm12, 0 == Rm
1114   // {12}     isAdd
1115   // {11-0}   imm12/Rm
1116   const MCOperand &MO = MI.getOperand(OpIdx);
1117   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1118   uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups, STI);
1119   Binary |= Rn << 14;
1120   return Binary;
1121 }
1122 
1123 uint32_t ARMMCCodeEmitter::
1124 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1125                           SmallVectorImpl<MCFixup> &Fixups,
1126                           const MCSubtargetInfo &STI) const {
1127   // {13}     1 == imm12, 0 == Rm
1128   // {12}     isAdd
1129   // {11-0}   imm12/Rm
1130   const MCOperand &MO = MI.getOperand(OpIdx);
1131   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1132   unsigned Imm = MO1.getImm();
1133   bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1134   bool isReg = MO.getReg() != 0;
1135   uint32_t Binary = ARM_AM::getAM2Offset(Imm);
1136   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
1137   if (isReg) {
1138     ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
1139     Binary <<= 7;                    // Shift amount is bits [11:7]
1140     Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1141     Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1142   }
1143   return Binary | (isAdd << 12) | (isReg << 13);
1144 }
1145 
1146 uint32_t ARMMCCodeEmitter::
1147 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1148                      SmallVectorImpl<MCFixup> &Fixups,
1149                      const MCSubtargetInfo &STI) const {
1150   // {4}      isAdd
1151   // {3-0}    Rm
1152   const MCOperand &MO = MI.getOperand(OpIdx);
1153   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1154   bool isAdd = MO1.getImm() != 0;
1155   return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
1156 }
1157 
1158 uint32_t ARMMCCodeEmitter::
1159 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1160                           SmallVectorImpl<MCFixup> &Fixups,
1161                           const MCSubtargetInfo &STI) const {
1162   // {9}      1 == imm8, 0 == Rm
1163   // {8}      isAdd
1164   // {7-4}    imm7_4/zero
1165   // {3-0}    imm3_0/Rm
1166   const MCOperand &MO = MI.getOperand(OpIdx);
1167   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1168   unsigned Imm = MO1.getImm();
1169   bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1170   bool isImm = MO.getReg() == 0;
1171   uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1172   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1173   if (!isImm)
1174     Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1175   return Imm8 | (isAdd << 8) | (isImm << 9);
1176 }
1177 
1178 uint32_t ARMMCCodeEmitter::
1179 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1180                     SmallVectorImpl<MCFixup> &Fixups,
1181                     const MCSubtargetInfo &STI) const {
1182   // {13}     1 == imm8, 0 == Rm
1183   // {12-9}   Rn
1184   // {8}      isAdd
1185   // {7-4}    imm7_4/zero
1186   // {3-0}    imm3_0/Rm
1187   const MCOperand &MO = MI.getOperand(OpIdx);
1188   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1189   const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1190 
1191   // If The first operand isn't a register, we have a label reference.
1192   if (!MO.isReg()) {
1193     unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1194 
1195     assert(MO.isExpr() && "Unexpected machine operand type!");
1196     const MCExpr *Expr = MO.getExpr();
1197     MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1198     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1199 
1200     ++MCNumCPRelocations;
1201     return (Rn << 9) | (1 << 13);
1202   }
1203   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1204   unsigned Imm = MO2.getImm();
1205   bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1206   bool isImm = MO1.getReg() == 0;
1207   uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1208   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1209   if (!isImm)
1210     Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1211   return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1212 }
1213 
1214 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1215 uint32_t ARMMCCodeEmitter::
1216 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1217                           SmallVectorImpl<MCFixup> &Fixups,
1218                           const MCSubtargetInfo &STI) const {
1219   // [SP, #imm]
1220   //   {7-0} = imm8
1221   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1222   assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1223          "Unexpected base register!");
1224 
1225   // The immediate is already shifted for the implicit zeroes, so no change
1226   // here.
1227   return MO1.getImm() & 0xff;
1228 }
1229 
1230 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1231 uint32_t ARMMCCodeEmitter::
1232 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1233                      SmallVectorImpl<MCFixup> &Fixups,
1234                      const MCSubtargetInfo &STI) const {
1235   // [Rn, #imm]
1236   //   {7-3} = imm5
1237   //   {2-0} = Rn
1238   const MCOperand &MO = MI.getOperand(OpIdx);
1239   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1240   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1241   unsigned Imm5 = MO1.getImm();
1242   return ((Imm5 & 0x1f) << 3) | Rn;
1243 }
1244 
1245 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1246 uint32_t ARMMCCodeEmitter::
1247 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1248                      SmallVectorImpl<MCFixup> &Fixups,
1249                      const MCSubtargetInfo &STI) const {
1250   const MCOperand MO = MI.getOperand(OpIdx);
1251   if (MO.isExpr())
1252     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI);
1253   return (MO.getImm() >> 2);
1254 }
1255 
1256 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
1257 uint32_t ARMMCCodeEmitter::
1258 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1259                     SmallVectorImpl<MCFixup> &Fixups,
1260                     const MCSubtargetInfo &STI) const {
1261   // {12-9} = reg
1262   // {8}    = (U)nsigned (add == '1', sub == '0')
1263   // {7-0}  = imm8
1264   unsigned Reg, Imm8;
1265   bool isAdd;
1266   // If The first operand isn't a register, we have a label reference.
1267   const MCOperand &MO = MI.getOperand(OpIdx);
1268   if (!MO.isReg()) {
1269     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1270     Imm8 = 0;
1271     isAdd = false; // 'U' bit is handled as part of the fixup.
1272 
1273     assert(MO.isExpr() && "Unexpected machine operand type!");
1274     const MCExpr *Expr = MO.getExpr();
1275     MCFixupKind Kind;
1276     if (isThumb2(STI))
1277       Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1278     else
1279       Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1280     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1281 
1282     ++MCNumCPRelocations;
1283   } else {
1284     EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1285     isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1286   }
1287 
1288   uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1289   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1290   if (isAdd)
1291     Binary |= (1 << 8);
1292   Binary |= (Reg << 9);
1293   return Binary;
1294 }
1295 
1296 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
1297 uint32_t ARMMCCodeEmitter::
1298 getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
1299                     SmallVectorImpl<MCFixup> &Fixups,
1300                     const MCSubtargetInfo &STI) const {
1301   // {12-9} = reg
1302   // {8}    = (U)nsigned (add == '1', sub == '0')
1303   // {7-0}  = imm8
1304   unsigned Reg, Imm8;
1305   bool isAdd;
1306   // If The first operand isn't a register, we have a label reference.
1307   const MCOperand &MO = MI.getOperand(OpIdx);
1308   if (!MO.isReg()) {
1309     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1310     Imm8 = 0;
1311     isAdd = false; // 'U' bit is handled as part of the fixup.
1312 
1313     assert(MO.isExpr() && "Unexpected machine operand type!");
1314     const MCExpr *Expr = MO.getExpr();
1315     MCFixupKind Kind;
1316     if (isThumb2(STI))
1317       Kind = MCFixupKind(ARM::fixup_t2_pcrel_9);
1318     else
1319       Kind = MCFixupKind(ARM::fixup_arm_pcrel_9);
1320     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1321 
1322     ++MCNumCPRelocations;
1323   } else {
1324     EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1325     isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1326   }
1327 
1328   uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1329   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1330   if (isAdd)
1331     Binary |= (1 << 8);
1332   Binary |= (Reg << 9);
1333   return Binary;
1334 }
1335 
1336 unsigned ARMMCCodeEmitter::
1337 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1338                 SmallVectorImpl<MCFixup> &Fixups,
1339                 const MCSubtargetInfo &STI) const {
1340   // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1341   // shifted. The second is Rs, the amount to shift by, and the third specifies
1342   // the type of the shift.
1343   //
1344   // {3-0} = Rm.
1345   // {4}   = 1
1346   // {6-5} = type
1347   // {11-8} = Rs
1348   // {7}    = 0
1349 
1350   const MCOperand &MO  = MI.getOperand(OpIdx);
1351   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1352   const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1353   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1354 
1355   // Encode Rm.
1356   unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1357 
1358   // Encode the shift opcode.
1359   unsigned SBits = 0;
1360   unsigned Rs = MO1.getReg();
1361   if (Rs) {
1362     // Set shift operand (bit[7:4]).
1363     // LSL - 0001
1364     // LSR - 0011
1365     // ASR - 0101
1366     // ROR - 0111
1367     switch (SOpc) {
1368     default: llvm_unreachable("Unknown shift opc!");
1369     case ARM_AM::lsl: SBits = 0x1; break;
1370     case ARM_AM::lsr: SBits = 0x3; break;
1371     case ARM_AM::asr: SBits = 0x5; break;
1372     case ARM_AM::ror: SBits = 0x7; break;
1373     }
1374   }
1375 
1376   Binary |= SBits << 4;
1377 
1378   // Encode the shift operation Rs.
1379   // Encode Rs bit[11:8].
1380   assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1381   return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
1382 }
1383 
1384 unsigned ARMMCCodeEmitter::
1385 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1386                 SmallVectorImpl<MCFixup> &Fixups,
1387                 const MCSubtargetInfo &STI) const {
1388   // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1389   // shifted. The second is the amount to shift by.
1390   //
1391   // {3-0} = Rm.
1392   // {4}   = 0
1393   // {6-5} = type
1394   // {11-7} = imm
1395 
1396   const MCOperand &MO  = MI.getOperand(OpIdx);
1397   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1398   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1399 
1400   // Encode Rm.
1401   unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1402 
1403   // Encode the shift opcode.
1404   unsigned SBits = 0;
1405 
1406   // Set shift operand (bit[6:4]).
1407   // LSL - 000
1408   // LSR - 010
1409   // ASR - 100
1410   // ROR - 110
1411   // RRX - 110 and bit[11:8] clear.
1412   switch (SOpc) {
1413   default: llvm_unreachable("Unknown shift opc!");
1414   case ARM_AM::lsl: SBits = 0x0; break;
1415   case ARM_AM::lsr: SBits = 0x2; break;
1416   case ARM_AM::asr: SBits = 0x4; break;
1417   case ARM_AM::ror: SBits = 0x6; break;
1418   case ARM_AM::rrx:
1419     Binary |= 0x60;
1420     return Binary;
1421   }
1422 
1423   // Encode shift_imm bit[11:7].
1424   Binary |= SBits << 4;
1425   unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1426   assert(Offset < 32 && "Offset must be in range 0-31!");
1427   return Binary | (Offset << 7);
1428 }
1429 
1430 
1431 unsigned ARMMCCodeEmitter::
1432 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1433                 SmallVectorImpl<MCFixup> &Fixups,
1434                 const MCSubtargetInfo &STI) const {
1435   const MCOperand &MO1 = MI.getOperand(OpNum);
1436   const MCOperand &MO2 = MI.getOperand(OpNum+1);
1437   const MCOperand &MO3 = MI.getOperand(OpNum+2);
1438 
1439   // Encoded as [Rn, Rm, imm].
1440   // FIXME: Needs fixup support.
1441   unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1442   Value <<= 4;
1443   Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1444   Value <<= 2;
1445   Value |= MO3.getImm();
1446 
1447   return Value;
1448 }
1449 
1450 unsigned ARMMCCodeEmitter::
1451 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1452                          SmallVectorImpl<MCFixup> &Fixups,
1453                          const MCSubtargetInfo &STI) const {
1454   const MCOperand &MO1 = MI.getOperand(OpNum);
1455   const MCOperand &MO2 = MI.getOperand(OpNum+1);
1456 
1457   // FIXME: Needs fixup support.
1458   unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1459 
1460   // Even though the immediate is 8 bits long, we need 9 bits in order
1461   // to represent the (inverse of the) sign bit.
1462   Value <<= 9;
1463   int32_t tmp = (int32_t)MO2.getImm();
1464   if (tmp < 0)
1465     tmp = abs(tmp);
1466   else
1467     Value |= 256; // Set the ADD bit
1468   Value |= tmp & 255;
1469   return Value;
1470 }
1471 
1472 unsigned ARMMCCodeEmitter::
1473 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1474                          SmallVectorImpl<MCFixup> &Fixups,
1475                          const MCSubtargetInfo &STI) const {
1476   const MCOperand &MO1 = MI.getOperand(OpNum);
1477 
1478   // FIXME: Needs fixup support.
1479   unsigned Value = 0;
1480   int32_t tmp = (int32_t)MO1.getImm();
1481   if (tmp < 0)
1482     tmp = abs(tmp);
1483   else
1484     Value |= 256; // Set the ADD bit
1485   Value |= tmp & 255;
1486   return Value;
1487 }
1488 
1489 unsigned ARMMCCodeEmitter::
1490 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1491                          SmallVectorImpl<MCFixup> &Fixups,
1492                          const MCSubtargetInfo &STI) const {
1493   const MCOperand &MO1 = MI.getOperand(OpNum);
1494 
1495   // FIXME: Needs fixup support.
1496   unsigned Value = 0;
1497   int32_t tmp = (int32_t)MO1.getImm();
1498   if (tmp < 0)
1499     tmp = abs(tmp);
1500   else
1501     Value |= 4096; // Set the ADD bit
1502   Value |= tmp & 4095;
1503   return Value;
1504 }
1505 
1506 unsigned ARMMCCodeEmitter::
1507 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1508                 SmallVectorImpl<MCFixup> &Fixups,
1509                 const MCSubtargetInfo &STI) const {
1510   // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1511   // shifted. The second is the amount to shift by.
1512   //
1513   // {3-0} = Rm.
1514   // {4}   = 0
1515   // {6-5} = type
1516   // {11-7} = imm
1517 
1518   const MCOperand &MO  = MI.getOperand(OpIdx);
1519   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1520   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1521 
1522   // Encode Rm.
1523   unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1524 
1525   // Encode the shift opcode.
1526   unsigned SBits = 0;
1527   // Set shift operand (bit[6:4]).
1528   // LSL - 000
1529   // LSR - 010
1530   // ASR - 100
1531   // ROR - 110
1532   switch (SOpc) {
1533   default: llvm_unreachable("Unknown shift opc!");
1534   case ARM_AM::lsl: SBits = 0x0; break;
1535   case ARM_AM::lsr: SBits = 0x2; break;
1536   case ARM_AM::asr: SBits = 0x4; break;
1537   case ARM_AM::rrx: // FALLTHROUGH
1538   case ARM_AM::ror: SBits = 0x6; break;
1539   }
1540 
1541   Binary |= SBits << 4;
1542   if (SOpc == ARM_AM::rrx)
1543     return Binary;
1544 
1545   // Encode shift_imm bit[11:7].
1546   return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1547 }
1548 
1549 unsigned ARMMCCodeEmitter::
1550 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1551                                SmallVectorImpl<MCFixup> &Fixups,
1552                                const MCSubtargetInfo &STI) const {
1553   // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1554   // msb of the mask.
1555   const MCOperand &MO = MI.getOperand(Op);
1556   uint32_t v = ~MO.getImm();
1557   uint32_t lsb = countTrailingZeros(v);
1558   uint32_t msb = (32 - countLeadingZeros (v)) - 1;
1559   assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1560   return lsb | (msb << 5);
1561 }
1562 
1563 unsigned ARMMCCodeEmitter::
1564 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1565                        SmallVectorImpl<MCFixup> &Fixups,
1566                        const MCSubtargetInfo &STI) const {
1567   // VLDM/VSTM:
1568   //   {12-8} = Vd
1569   //   {7-0}  = Number of registers
1570   //
1571   // LDM/STM:
1572   //   {15-0}  = Bitfield of GPRs.
1573   unsigned Reg = MI.getOperand(Op).getReg();
1574   bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1575   bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1576 
1577   unsigned Binary = 0;
1578 
1579   if (SPRRegs || DPRRegs) {
1580     // VLDM/VSTM
1581     unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1582     unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1583     Binary |= (RegNo & 0x1f) << 8;
1584     if (SPRRegs)
1585       Binary |= NumRegs;
1586     else
1587       Binary |= NumRegs * 2;
1588   } else {
1589     for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1590       unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(MI.getOperand(I).getReg());
1591       Binary |= 1 << RegNo;
1592     }
1593   }
1594 
1595   return Binary;
1596 }
1597 
1598 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1599 /// with the alignment operand.
1600 unsigned ARMMCCodeEmitter::
1601 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1602                            SmallVectorImpl<MCFixup> &Fixups,
1603                            const MCSubtargetInfo &STI) const {
1604   const MCOperand &Reg = MI.getOperand(Op);
1605   const MCOperand &Imm = MI.getOperand(Op + 1);
1606 
1607   unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1608   unsigned Align = 0;
1609 
1610   switch (Imm.getImm()) {
1611   default: break;
1612   case 2:
1613   case 4:
1614   case 8:  Align = 0x01; break;
1615   case 16: Align = 0x02; break;
1616   case 32: Align = 0x03; break;
1617   }
1618 
1619   return RegNo | (Align << 4);
1620 }
1621 
1622 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1623 /// along  with the alignment operand for use in VST1 and VLD1 with size 32.
1624 unsigned ARMMCCodeEmitter::
1625 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1626                                     SmallVectorImpl<MCFixup> &Fixups,
1627                                     const MCSubtargetInfo &STI) const {
1628   const MCOperand &Reg = MI.getOperand(Op);
1629   const MCOperand &Imm = MI.getOperand(Op + 1);
1630 
1631   unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1632   unsigned Align = 0;
1633 
1634   switch (Imm.getImm()) {
1635   default: break;
1636   case 8:
1637   case 16:
1638   case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1639   case 2: Align = 0x00; break;
1640   case 4: Align = 0x03; break;
1641   }
1642 
1643   return RegNo | (Align << 4);
1644 }
1645 
1646 
1647 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1648 /// alignment operand for use in VLD-dup instructions.  This is the same as
1649 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1650 /// different for VLD4-dup.
1651 unsigned ARMMCCodeEmitter::
1652 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1653                               SmallVectorImpl<MCFixup> &Fixups,
1654                               const MCSubtargetInfo &STI) const {
1655   const MCOperand &Reg = MI.getOperand(Op);
1656   const MCOperand &Imm = MI.getOperand(Op + 1);
1657 
1658   unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1659   unsigned Align = 0;
1660 
1661   switch (Imm.getImm()) {
1662   default: break;
1663   case 2:
1664   case 4:
1665   case 8:  Align = 0x01; break;
1666   case 16: Align = 0x03; break;
1667   }
1668 
1669   return RegNo | (Align << 4);
1670 }
1671 
1672 unsigned ARMMCCodeEmitter::
1673 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1674                           SmallVectorImpl<MCFixup> &Fixups,
1675                           const MCSubtargetInfo &STI) const {
1676   const MCOperand &MO = MI.getOperand(Op);
1677   if (MO.getReg() == 0) return 0x0D;
1678   return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1679 }
1680 
1681 unsigned ARMMCCodeEmitter::
1682 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1683                   SmallVectorImpl<MCFixup> &Fixups,
1684                   const MCSubtargetInfo &STI) const {
1685   return 8 - MI.getOperand(Op).getImm();
1686 }
1687 
1688 unsigned ARMMCCodeEmitter::
1689 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1690                    SmallVectorImpl<MCFixup> &Fixups,
1691                    const MCSubtargetInfo &STI) const {
1692   return 16 - MI.getOperand(Op).getImm();
1693 }
1694 
1695 unsigned ARMMCCodeEmitter::
1696 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1697                    SmallVectorImpl<MCFixup> &Fixups,
1698                    const MCSubtargetInfo &STI) const {
1699   return 32 - MI.getOperand(Op).getImm();
1700 }
1701 
1702 unsigned ARMMCCodeEmitter::
1703 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1704                    SmallVectorImpl<MCFixup> &Fixups,
1705                    const MCSubtargetInfo &STI) const {
1706   return 64 - MI.getOperand(Op).getImm();
1707 }
1708 
1709 void ARMMCCodeEmitter::
1710 encodeInstruction(const MCInst &MI, raw_ostream &OS,
1711                   SmallVectorImpl<MCFixup> &Fixups,
1712                   const MCSubtargetInfo &STI) const {
1713   // Pseudo instructions don't get encoded.
1714   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1715   uint64_t TSFlags = Desc.TSFlags;
1716   if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1717     return;
1718 
1719   int Size;
1720   if (Desc.getSize() == 2 || Desc.getSize() == 4)
1721     Size = Desc.getSize();
1722   else
1723     llvm_unreachable("Unexpected instruction size!");
1724 
1725   uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1726   // Thumb 32-bit wide instructions need to emit the high order halfword
1727   // first.
1728   if (isThumb(STI) && Size == 4) {
1729     EmitConstant(Binary >> 16, 2, OS);
1730     EmitConstant(Binary & 0xffff, 2, OS);
1731   } else
1732     EmitConstant(Binary, Size, OS);
1733   ++MCNumEmitted;  // Keep track of the # of mi's emitted.
1734 }
1735 
1736 #include "ARMGenMCCodeEmitter.inc"
1737