1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARMMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/ARMMCTargetDesc.h"
16 #include "MCTargetDesc/ARMAddressingModes.h"
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "MCTargetDesc/ARMFixupKinds.h"
19 #include "MCTargetDesc/ARMMCExpr.h"
20 #include "llvm/ADT/APFloat.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/raw_ostream.h"
31 
32 using namespace llvm;
33 
34 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
35 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
36 
37 namespace {
38 class ARMMCCodeEmitter : public MCCodeEmitter {
39   ARMMCCodeEmitter(const ARMMCCodeEmitter &) LLVM_DELETED_FUNCTION;
40   void operator=(const ARMMCCodeEmitter &) LLVM_DELETED_FUNCTION;
41   const MCInstrInfo &MCII;
42   const MCContext &CTX;
43 
44 public:
45   ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
46     : MCII(mcii), CTX(ctx) {
47   }
48 
49   ~ARMMCCodeEmitter() {}
50 
51   bool isThumb(const MCSubtargetInfo &STI) const {
52     return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
53   }
54   bool isThumb2(const MCSubtargetInfo &STI) const {
55     return isThumb(STI) && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
56   }
57   bool isTargetMachO(const MCSubtargetInfo &STI) const {
58     Triple TT(STI.getTargetTriple());
59     return TT.isOSBinFormatMachO();
60   }
61 
62   unsigned getMachineSoImmOpValue(unsigned SoImm) const;
63 
64   // getBinaryCodeForInstr - TableGen'erated function for getting the
65   // binary encoding for an instruction.
66   uint64_t getBinaryCodeForInstr(const MCInst &MI,
67                                  SmallVectorImpl<MCFixup> &Fixups,
68                                  const MCSubtargetInfo &STI) const;
69 
70   /// getMachineOpValue - Return binary encoding of operand. If the machine
71   /// operand requires relocation, record the relocation and return zero.
72   unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
73                              SmallVectorImpl<MCFixup> &Fixups,
74                              const MCSubtargetInfo &STI) const;
75 
76   /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
77   /// the specified operand. This is used for operands with :lower16: and
78   /// :upper16: prefixes.
79   uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
80                                SmallVectorImpl<MCFixup> &Fixups,
81                                const MCSubtargetInfo &STI) const;
82 
83   bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
84                               unsigned &Reg, unsigned &Imm,
85                               SmallVectorImpl<MCFixup> &Fixups,
86                               const MCSubtargetInfo &STI) const;
87 
88   /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
89   /// BL branch target.
90   uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
91                                    SmallVectorImpl<MCFixup> &Fixups,
92                                    const MCSubtargetInfo &STI) const;
93 
94   /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
95   /// BLX branch target.
96   uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
97                                     SmallVectorImpl<MCFixup> &Fixups,
98                                     const MCSubtargetInfo &STI) const;
99 
100   /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
101   uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
102                                    SmallVectorImpl<MCFixup> &Fixups,
103                                    const MCSubtargetInfo &STI) const;
104 
105   /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
106   uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
107                                     SmallVectorImpl<MCFixup> &Fixups,
108                                     const MCSubtargetInfo &STI) const;
109 
110   /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
111   uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
112                                    SmallVectorImpl<MCFixup> &Fixups,
113                                    const MCSubtargetInfo &STI) const;
114 
115   /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
116   /// branch target.
117   uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
118                                   SmallVectorImpl<MCFixup> &Fixups,
119                                   const MCSubtargetInfo &STI) const;
120 
121   /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
122   /// immediate Thumb2 direct branch target.
123   uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
124                                   SmallVectorImpl<MCFixup> &Fixups,
125                                   const MCSubtargetInfo &STI) const;
126 
127   /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
128   /// branch target.
129   uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
130                                      SmallVectorImpl<MCFixup> &Fixups,
131                                      const MCSubtargetInfo &STI) const;
132   uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
133                                  SmallVectorImpl<MCFixup> &Fixups,
134                                  const MCSubtargetInfo &STI) const;
135   uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
136                                   SmallVectorImpl<MCFixup> &Fixups,
137                                   const MCSubtargetInfo &STI) const;
138 
139   /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
140   /// ADR label target.
141   uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
142                               SmallVectorImpl<MCFixup> &Fixups,
143                               const MCSubtargetInfo &STI) const;
144   uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
145                               SmallVectorImpl<MCFixup> &Fixups,
146                               const MCSubtargetInfo &STI) const;
147   uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
148                               SmallVectorImpl<MCFixup> &Fixups,
149                               const MCSubtargetInfo &STI) const;
150 
151 
152   /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
153   /// operand.
154   uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
155                                    SmallVectorImpl<MCFixup> &Fixups,
156                                    const MCSubtargetInfo &STI) const;
157 
158   /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
159   uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
160                                          SmallVectorImpl<MCFixup> &Fixups,
161                                          const MCSubtargetInfo &STI) const;
162 
163   /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
164   /// operand.
165   uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
166                                    SmallVectorImpl<MCFixup> &Fixups,
167                                    const MCSubtargetInfo &STI) const;
168 
169   /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
170   /// operand.
171   uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
172                                    SmallVectorImpl<MCFixup> &Fixups,
173                                    const MCSubtargetInfo &STI) const;
174 
175   /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
176   /// operand.
177   uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
178                               SmallVectorImpl<MCFixup> &Fixups,
179                               const MCSubtargetInfo &STI) const;
180 
181 
182   /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
183   /// operand as needed by load/store instructions.
184   uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
185                                SmallVectorImpl<MCFixup> &Fixups,
186                                const MCSubtargetInfo &STI) const;
187 
188   /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
189   uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
190                                SmallVectorImpl<MCFixup> &Fixups,
191                                const MCSubtargetInfo &STI) const {
192     ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
193     switch (Mode) {
194     default: llvm_unreachable("Unknown addressing sub-mode!");
195     case ARM_AM::da: return 0;
196     case ARM_AM::ia: return 1;
197     case ARM_AM::db: return 2;
198     case ARM_AM::ib: return 3;
199     }
200   }
201   /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
202   ///
203   unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
204     switch (ShOpc) {
205     case ARM_AM::no_shift:
206     case ARM_AM::lsl: return 0;
207     case ARM_AM::lsr: return 1;
208     case ARM_AM::asr: return 2;
209     case ARM_AM::ror:
210     case ARM_AM::rrx: return 3;
211     }
212     llvm_unreachable("Invalid ShiftOpc!");
213   }
214 
215   /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
216   uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
217                                SmallVectorImpl<MCFixup> &Fixups,
218                                const MCSubtargetInfo &STI) const;
219 
220   /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
221   uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
222                                      SmallVectorImpl<MCFixup> &Fixups,
223                                      const MCSubtargetInfo &STI) const;
224 
225   /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
226   uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
227                                 SmallVectorImpl<MCFixup> &Fixups,
228                                 const MCSubtargetInfo &STI) const;
229 
230   /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
231   uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
232                                      SmallVectorImpl<MCFixup> &Fixups,
233                                      const MCSubtargetInfo &STI) const;
234 
235   /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
236   uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
237                                SmallVectorImpl<MCFixup> &Fixups,
238                                const MCSubtargetInfo &STI) const;
239 
240   /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
241   /// operand.
242   uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
243                                      SmallVectorImpl<MCFixup> &Fixups,
244                                      const MCSubtargetInfo &STI) const;
245 
246   /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
247   uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
248                                 SmallVectorImpl<MCFixup> &Fixups,
249                                 const MCSubtargetInfo &STI) const;
250 
251   /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
252   uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
253                                 SmallVectorImpl<MCFixup> &Fixups,
254                                 const MCSubtargetInfo &STI) const;
255 
256   /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
257   uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
258                                SmallVectorImpl<MCFixup> &Fixups,
259                                const MCSubtargetInfo &STI) const;
260 
261   /// getCCOutOpValue - Return encoding of the 's' bit.
262   unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
263                            SmallVectorImpl<MCFixup> &Fixups,
264                            const MCSubtargetInfo &STI) const {
265     // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
266     // '1' respectively.
267     return MI.getOperand(Op).getReg() == ARM::CPSR;
268   }
269 
270   /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
271   unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
272                            SmallVectorImpl<MCFixup> &Fixups,
273                            const MCSubtargetInfo &STI) const {
274     unsigned SoImm = MI.getOperand(Op).getImm();
275     int SoImmVal = ARM_AM::getSOImmVal(SoImm);
276     assert(SoImmVal != -1 && "Not a valid so_imm value!");
277 
278     // Encode rotate_imm.
279     unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
280       << ARMII::SoRotImmShift;
281 
282     // Encode immed_8.
283     Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
284     return Binary;
285   }
286 
287   /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
288   unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
289                            SmallVectorImpl<MCFixup> &Fixups,
290                            const MCSubtargetInfo &STI) const {
291     unsigned SoImm = MI.getOperand(Op).getImm();
292     unsigned Encoded =  ARM_AM::getT2SOImmVal(SoImm);
293     assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
294     return Encoded;
295   }
296 
297   unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
298     SmallVectorImpl<MCFixup> &Fixups,
299     const MCSubtargetInfo &STI) const;
300   unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
301     SmallVectorImpl<MCFixup> &Fixups,
302     const MCSubtargetInfo &STI) const;
303   unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
304     SmallVectorImpl<MCFixup> &Fixups,
305     const MCSubtargetInfo &STI) const;
306   unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
307     SmallVectorImpl<MCFixup> &Fixups,
308     const MCSubtargetInfo &STI) const;
309 
310   /// getSORegOpValue - Return an encoded so_reg shifted register value.
311   unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
312                            SmallVectorImpl<MCFixup> &Fixups,
313                            const MCSubtargetInfo &STI) const;
314   unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
315                            SmallVectorImpl<MCFixup> &Fixups,
316                            const MCSubtargetInfo &STI) const;
317   unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
318                              SmallVectorImpl<MCFixup> &Fixups,
319                              const MCSubtargetInfo &STI) const;
320 
321   unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
322                                    SmallVectorImpl<MCFixup> &Fixups,
323                                    const MCSubtargetInfo &STI) const {
324     return 64 - MI.getOperand(Op).getImm();
325   }
326 
327   unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
328                                       SmallVectorImpl<MCFixup> &Fixups,
329                                       const MCSubtargetInfo &STI) const;
330 
331   unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
332                                   SmallVectorImpl<MCFixup> &Fixups,
333                                   const MCSubtargetInfo &STI) const;
334   unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
335                                       SmallVectorImpl<MCFixup> &Fixups,
336                                       const MCSubtargetInfo &STI) const;
337   unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
338                                         SmallVectorImpl<MCFixup> &Fixups,
339                                         const MCSubtargetInfo &STI) const;
340   unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
341                                         SmallVectorImpl<MCFixup> &Fixups,
342                                         const MCSubtargetInfo &STI) const;
343   unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
344                                      SmallVectorImpl<MCFixup> &Fixups,
345                                      const MCSubtargetInfo &STI) const;
346 
347   unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
348                              SmallVectorImpl<MCFixup> &Fixups,
349                              const MCSubtargetInfo &STI) const;
350   unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
351                               SmallVectorImpl<MCFixup> &Fixups,
352                               const MCSubtargetInfo &STI) const;
353   unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
354                               SmallVectorImpl<MCFixup> &Fixups,
355                               const MCSubtargetInfo &STI) const;
356   unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
357                               SmallVectorImpl<MCFixup> &Fixups,
358                               const MCSubtargetInfo &STI) const;
359 
360   unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
361                                  SmallVectorImpl<MCFixup> &Fixups,
362                                  const MCSubtargetInfo &STI) const;
363 
364   unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
365                                       unsigned EncodedValue,
366                                       const MCSubtargetInfo &STI) const;
367   unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
368                                           unsigned EncodedValue,
369                                           const MCSubtargetInfo &STI) const;
370   unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
371                                     unsigned EncodedValue,
372                                     const MCSubtargetInfo &STI) const;
373   unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
374                                    unsigned EncodedValue,
375                                    const MCSubtargetInfo &STI) const;
376 
377   unsigned VFPThumb2PostEncoder(const MCInst &MI,
378                                 unsigned EncodedValue,
379                                 const MCSubtargetInfo &STI) const;
380 
381   void EmitByte(unsigned char C, raw_ostream &OS) const {
382     OS << (char)C;
383   }
384 
385   void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
386     // Output the constant in little endian byte order.
387     for (unsigned i = 0; i != Size; ++i) {
388       EmitByte(Val & 255, OS);
389       Val >>= 8;
390     }
391   }
392 
393   void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
394                          SmallVectorImpl<MCFixup> &Fixups,
395                          const MCSubtargetInfo &STI) const;
396 };
397 
398 } // end anonymous namespace
399 
400 MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
401                                             const MCRegisterInfo &MRI,
402                                             const MCSubtargetInfo &STI,
403                                             MCContext &Ctx) {
404   return new ARMMCCodeEmitter(MCII, Ctx);
405 }
406 
407 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
408 /// instructions, and rewrite them to their Thumb2 form if we are currently in
409 /// Thumb2 mode.
410 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
411                                                  unsigned EncodedValue,
412                                                  const MCSubtargetInfo &STI) const {
413   if (isThumb2(STI)) {
414     // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
415     // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
416     // set to 1111.
417     unsigned Bit24 = EncodedValue & 0x01000000;
418     unsigned Bit28 = Bit24 << 4;
419     EncodedValue &= 0xEFFFFFFF;
420     EncodedValue |= Bit28;
421     EncodedValue |= 0x0F000000;
422   }
423 
424   return EncodedValue;
425 }
426 
427 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
428 /// instructions, and rewrite them to their Thumb2 form if we are currently in
429 /// Thumb2 mode.
430 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
431                                                  unsigned EncodedValue,
432                                                  const MCSubtargetInfo &STI) const {
433   if (isThumb2(STI)) {
434     EncodedValue &= 0xF0FFFFFF;
435     EncodedValue |= 0x09000000;
436   }
437 
438   return EncodedValue;
439 }
440 
441 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
442 /// instructions, and rewrite them to their Thumb2 form if we are currently in
443 /// Thumb2 mode.
444 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
445                                                  unsigned EncodedValue,
446                                                  const MCSubtargetInfo &STI) const {
447   if (isThumb2(STI)) {
448     EncodedValue &= 0x00FFFFFF;
449     EncodedValue |= 0xEE000000;
450   }
451 
452   return EncodedValue;
453 }
454 
455 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
456 /// if we are in Thumb2.
457 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
458                                                  unsigned EncodedValue,
459                                                  const MCSubtargetInfo &STI) const {
460   if (isThumb2(STI)) {
461     EncodedValue |= 0xC000000; // Set bits 27-26
462   }
463 
464   return EncodedValue;
465 }
466 
467 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
468 /// them to their Thumb2 form if we are currently in Thumb2 mode.
469 unsigned ARMMCCodeEmitter::
470 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
471                      const MCSubtargetInfo &STI) const {
472   if (isThumb2(STI)) {
473     EncodedValue &= 0x0FFFFFFF;
474     EncodedValue |= 0xE0000000;
475   }
476   return EncodedValue;
477 }
478 
479 /// getMachineOpValue - Return binary encoding of operand. If the machine
480 /// operand requires relocation, record the relocation and return zero.
481 unsigned ARMMCCodeEmitter::
482 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
483                   SmallVectorImpl<MCFixup> &Fixups,
484                   const MCSubtargetInfo &STI) const {
485   if (MO.isReg()) {
486     unsigned Reg = MO.getReg();
487     unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
488 
489     // Q registers are encoded as 2x their register number.
490     switch (Reg) {
491     default:
492       return RegNo;
493     case ARM::Q0:  case ARM::Q1:  case ARM::Q2:  case ARM::Q3:
494     case ARM::Q4:  case ARM::Q5:  case ARM::Q6:  case ARM::Q7:
495     case ARM::Q8:  case ARM::Q9:  case ARM::Q10: case ARM::Q11:
496     case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
497       return 2 * RegNo;
498     }
499   } else if (MO.isImm()) {
500     return static_cast<unsigned>(MO.getImm());
501   } else if (MO.isFPImm()) {
502     return static_cast<unsigned>(APFloat(MO.getFPImm())
503                      .bitcastToAPInt().getHiBits(32).getLimitedValue());
504   }
505 
506   llvm_unreachable("Unable to encode MCOperand!");
507 }
508 
509 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
510 bool ARMMCCodeEmitter::
511 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
512                        unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
513  const MCSubtargetInfo &STI) const {
514   const MCOperand &MO  = MI.getOperand(OpIdx);
515   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
516 
517   Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
518 
519   int32_t SImm = MO1.getImm();
520   bool isAdd = true;
521 
522   // Special value for #-0
523   if (SImm == INT32_MIN) {
524     SImm = 0;
525     isAdd = false;
526   }
527 
528   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
529   if (SImm < 0) {
530     SImm = -SImm;
531     isAdd = false;
532   }
533 
534   Imm = SImm;
535   return isAdd;
536 }
537 
538 /// getBranchTargetOpValue - Helper function to get the branch target operand,
539 /// which is either an immediate or requires a fixup.
540 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
541                                        unsigned FixupKind,
542                                        SmallVectorImpl<MCFixup> &Fixups,
543                                        const MCSubtargetInfo &STI) {
544   const MCOperand &MO = MI.getOperand(OpIdx);
545 
546   // If the destination is an immediate, we have nothing to do.
547   if (MO.isImm()) return MO.getImm();
548   assert(MO.isExpr() && "Unexpected branch target type!");
549   const MCExpr *Expr = MO.getExpr();
550   MCFixupKind Kind = MCFixupKind(FixupKind);
551   Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
552 
553   // All of the information is in the fixup.
554   return 0;
555 }
556 
557 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
558 // determined by negating them and XOR'ing them with bit 23.
559 static int32_t encodeThumbBLOffset(int32_t offset) {
560   offset >>= 1;
561   uint32_t S  = (offset & 0x800000) >> 23;
562   uint32_t J1 = (offset & 0x400000) >> 22;
563   uint32_t J2 = (offset & 0x200000) >> 21;
564   J1 = (~J1 & 0x1);
565   J2 = (~J2 & 0x1);
566   J1 ^= S;
567   J2 ^= S;
568 
569   offset &= ~0x600000;
570   offset |= J1 << 22;
571   offset |= J2 << 21;
572 
573   return offset;
574 }
575 
576 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
577 uint32_t ARMMCCodeEmitter::
578 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
579                         SmallVectorImpl<MCFixup> &Fixups,
580                         const MCSubtargetInfo &STI) const {
581   const MCOperand MO = MI.getOperand(OpIdx);
582   if (MO.isExpr())
583     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
584                                     Fixups, STI);
585   return encodeThumbBLOffset(MO.getImm());
586 }
587 
588 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
589 /// BLX branch target.
590 uint32_t ARMMCCodeEmitter::
591 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
592                          SmallVectorImpl<MCFixup> &Fixups,
593                          const MCSubtargetInfo &STI) const {
594   const MCOperand MO = MI.getOperand(OpIdx);
595   if (MO.isExpr())
596     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
597                                     Fixups, STI);
598   return encodeThumbBLOffset(MO.getImm());
599 }
600 
601 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
602 uint32_t ARMMCCodeEmitter::
603 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
604                         SmallVectorImpl<MCFixup> &Fixups,
605                         const MCSubtargetInfo &STI) const {
606   const MCOperand MO = MI.getOperand(OpIdx);
607   if (MO.isExpr())
608     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
609                                     Fixups, STI);
610   return (MO.getImm() >> 1);
611 }
612 
613 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
614 uint32_t ARMMCCodeEmitter::
615 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
616                          SmallVectorImpl<MCFixup> &Fixups,
617                          const MCSubtargetInfo &STI) const {
618   const MCOperand MO = MI.getOperand(OpIdx);
619   if (MO.isExpr())
620     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
621                                     Fixups, STI);
622   return (MO.getImm() >> 1);
623 }
624 
625 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
626 uint32_t ARMMCCodeEmitter::
627 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
628                         SmallVectorImpl<MCFixup> &Fixups,
629                         const MCSubtargetInfo &STI) const {
630   const MCOperand MO = MI.getOperand(OpIdx);
631   if (MO.isExpr())
632     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI);
633   return (MO.getImm() >> 1);
634 }
635 
636 /// Return true if this branch has a non-always predication
637 static bool HasConditionalBranch(const MCInst &MI) {
638   int NumOp = MI.getNumOperands();
639   if (NumOp >= 2) {
640     for (int i = 0; i < NumOp-1; ++i) {
641       const MCOperand &MCOp1 = MI.getOperand(i);
642       const MCOperand &MCOp2 = MI.getOperand(i + 1);
643       if (MCOp1.isImm() && MCOp2.isReg() &&
644           (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
645         if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
646           return true;
647       }
648     }
649   }
650   return false;
651 }
652 
653 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
654 /// target.
655 uint32_t ARMMCCodeEmitter::
656 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
657                        SmallVectorImpl<MCFixup> &Fixups,
658                        const MCSubtargetInfo &STI) const {
659   // FIXME: This really, really shouldn't use TargetMachine. We don't want
660   // coupling between MC and TM anywhere we can help it.
661   if (isThumb2(STI))
662     return
663       ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI);
664   return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
665 }
666 
667 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
668 /// target.
669 uint32_t ARMMCCodeEmitter::
670 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
671                           SmallVectorImpl<MCFixup> &Fixups,
672                           const MCSubtargetInfo &STI) const {
673   const MCOperand MO = MI.getOperand(OpIdx);
674   if (MO.isExpr()) {
675     if (HasConditionalBranch(MI))
676       return ::getBranchTargetOpValue(MI, OpIdx,
677                                       ARM::fixup_arm_condbranch, Fixups, STI);
678     return ::getBranchTargetOpValue(MI, OpIdx,
679                                     ARM::fixup_arm_uncondbranch, Fixups, STI);
680   }
681 
682   return MO.getImm() >> 2;
683 }
684 
685 uint32_t ARMMCCodeEmitter::
686 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
687                           SmallVectorImpl<MCFixup> &Fixups,
688                           const MCSubtargetInfo &STI) const {
689   const MCOperand MO = MI.getOperand(OpIdx);
690   if (MO.isExpr()) {
691     if (HasConditionalBranch(MI))
692       return ::getBranchTargetOpValue(MI, OpIdx,
693                                       ARM::fixup_arm_condbl, Fixups, STI);
694     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI);
695   }
696 
697   return MO.getImm() >> 2;
698 }
699 
700 uint32_t ARMMCCodeEmitter::
701 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
702                           SmallVectorImpl<MCFixup> &Fixups,
703                           const MCSubtargetInfo &STI) const {
704   const MCOperand MO = MI.getOperand(OpIdx);
705   if (MO.isExpr())
706     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI);
707 
708   return MO.getImm() >> 1;
709 }
710 
711 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
712 /// immediate branch target.
713 uint32_t ARMMCCodeEmitter::
714 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
715                        SmallVectorImpl<MCFixup> &Fixups,
716                        const MCSubtargetInfo &STI) const {
717   unsigned Val = 0;
718   const MCOperand MO = MI.getOperand(OpIdx);
719 
720   if(MO.isExpr())
721     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI);
722   else
723     Val = MO.getImm() >> 1;
724 
725   bool I  = (Val & 0x800000);
726   bool J1 = (Val & 0x400000);
727   bool J2 = (Val & 0x200000);
728   if (I ^ J1)
729     Val &= ~0x400000;
730   else
731     Val |= 0x400000;
732 
733   if (I ^ J2)
734     Val &= ~0x200000;
735   else
736     Val |= 0x200000;
737 
738   return Val;
739 }
740 
741 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
742 /// ADR label target.
743 uint32_t ARMMCCodeEmitter::
744 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
745                    SmallVectorImpl<MCFixup> &Fixups,
746                    const MCSubtargetInfo &STI) const {
747   const MCOperand MO = MI.getOperand(OpIdx);
748   if (MO.isExpr())
749     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
750                                     Fixups, STI);
751   int64_t offset = MO.getImm();
752   uint32_t Val = 0x2000;
753 
754   int SoImmVal;
755   if (offset == INT32_MIN) {
756     Val = 0x1000;
757     SoImmVal = 0;
758   } else if (offset < 0) {
759     Val = 0x1000;
760     offset *= -1;
761     SoImmVal = ARM_AM::getSOImmVal(offset);
762     if(SoImmVal == -1) {
763       Val = 0x2000;
764       offset *= -1;
765       SoImmVal = ARM_AM::getSOImmVal(offset);
766     }
767   } else {
768     SoImmVal = ARM_AM::getSOImmVal(offset);
769     if(SoImmVal == -1) {
770       Val = 0x1000;
771       offset *= -1;
772       SoImmVal = ARM_AM::getSOImmVal(offset);
773     }
774   }
775 
776   assert(SoImmVal != -1 && "Not a valid so_imm value!");
777 
778   Val |= SoImmVal;
779   return Val;
780 }
781 
782 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
783 /// target.
784 uint32_t ARMMCCodeEmitter::
785 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
786                    SmallVectorImpl<MCFixup> &Fixups,
787                    const MCSubtargetInfo &STI) const {
788   const MCOperand MO = MI.getOperand(OpIdx);
789   if (MO.isExpr())
790     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
791                                     Fixups, STI);
792   int32_t Val = MO.getImm();
793   if (Val == INT32_MIN)
794     Val = 0x1000;
795   else if (Val < 0) {
796     Val *= -1;
797     Val |= 0x1000;
798   }
799   return Val;
800 }
801 
802 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
803 /// target.
804 uint32_t ARMMCCodeEmitter::
805 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
806                    SmallVectorImpl<MCFixup> &Fixups,
807                    const MCSubtargetInfo &STI) const {
808   const MCOperand MO = MI.getOperand(OpIdx);
809   if (MO.isExpr())
810     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
811                                     Fixups, STI);
812   return MO.getImm();
813 }
814 
815 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
816 /// operand.
817 uint32_t ARMMCCodeEmitter::
818 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
819                               SmallVectorImpl<MCFixup> &,
820                               const MCSubtargetInfo &STI) const {
821   // [Rn, Rm]
822   //   {5-3} = Rm
823   //   {2-0} = Rn
824   const MCOperand &MO1 = MI.getOperand(OpIdx);
825   const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
826   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
827   unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
828   return (Rm << 3) | Rn;
829 }
830 
831 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
832 uint32_t ARMMCCodeEmitter::
833 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
834                         SmallVectorImpl<MCFixup> &Fixups,
835                         const MCSubtargetInfo &STI) const {
836   // {17-13} = reg
837   // {12}    = (U)nsigned (add == '1', sub == '0')
838   // {11-0}  = imm12
839   unsigned Reg, Imm12;
840   bool isAdd = true;
841   // If The first operand isn't a register, we have a label reference.
842   const MCOperand &MO = MI.getOperand(OpIdx);
843   if (!MO.isReg()) {
844     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
845     Imm12 = 0;
846 
847     if (MO.isExpr()) {
848       const MCExpr *Expr = MO.getExpr();
849       isAdd = false ; // 'U' bit is set as part of the fixup.
850 
851       MCFixupKind Kind;
852       if (isThumb2(STI))
853         Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
854       else
855         Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
856       Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
857 
858       ++MCNumCPRelocations;
859     } else {
860       Reg = ARM::PC;
861       int32_t Offset = MO.getImm();
862       if (Offset == INT32_MIN) {
863         Offset = 0;
864         isAdd = false;
865       } else if (Offset < 0) {
866         Offset *= -1;
867         isAdd = false;
868       }
869       Imm12 = Offset;
870     }
871   } else
872     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
873 
874   uint32_t Binary = Imm12 & 0xfff;
875   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
876   if (isAdd)
877     Binary |= (1 << 12);
878   Binary |= (Reg << 13);
879   return Binary;
880 }
881 
882 /// getT2Imm8s4OpValue - Return encoding info for
883 /// '+/- imm8<<2' operand.
884 uint32_t ARMMCCodeEmitter::
885 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
886                    SmallVectorImpl<MCFixup> &Fixups,
887                    const MCSubtargetInfo &STI) const {
888   // FIXME: The immediate operand should have already been encoded like this
889   // before ever getting here. The encoder method should just need to combine
890   // the MI operands for the register and the offset into a single
891   // representation for the complex operand in the .td file. This isn't just
892   // style, unfortunately. As-is, we can't represent the distinct encoding
893   // for #-0.
894 
895   // {8}    = (U)nsigned (add == '1', sub == '0')
896   // {7-0}  = imm8
897   int32_t Imm8 = MI.getOperand(OpIdx).getImm();
898   bool isAdd = Imm8 >= 0;
899 
900   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
901   if (Imm8 < 0)
902     Imm8 = -(uint32_t)Imm8;
903 
904   // Scaled by 4.
905   Imm8 /= 4;
906 
907   uint32_t Binary = Imm8 & 0xff;
908   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
909   if (isAdd)
910     Binary |= (1 << 8);
911   return Binary;
912 }
913 
914 /// getT2AddrModeImm8s4OpValue - Return encoding info for
915 /// 'reg +/- imm8<<2' operand.
916 uint32_t ARMMCCodeEmitter::
917 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
918                         SmallVectorImpl<MCFixup> &Fixups,
919                         const MCSubtargetInfo &STI) const {
920   // {12-9} = reg
921   // {8}    = (U)nsigned (add == '1', sub == '0')
922   // {7-0}  = imm8
923   unsigned Reg, Imm8;
924   bool isAdd = true;
925   // If The first operand isn't a register, we have a label reference.
926   const MCOperand &MO = MI.getOperand(OpIdx);
927   if (!MO.isReg()) {
928     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
929     Imm8 = 0;
930     isAdd = false ; // 'U' bit is set as part of the fixup.
931 
932     assert(MO.isExpr() && "Unexpected machine operand type!");
933     const MCExpr *Expr = MO.getExpr();
934     MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
935     Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
936 
937     ++MCNumCPRelocations;
938   } else
939     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
940 
941   // FIXME: The immediate operand should have already been encoded like this
942   // before ever getting here. The encoder method should just need to combine
943   // the MI operands for the register and the offset into a single
944   // representation for the complex operand in the .td file. This isn't just
945   // style, unfortunately. As-is, we can't represent the distinct encoding
946   // for #-0.
947   uint32_t Binary = (Imm8 >> 2) & 0xff;
948   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
949   if (isAdd)
950     Binary |= (1 << 8);
951   Binary |= (Reg << 9);
952   return Binary;
953 }
954 
955 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
956 /// 'reg + imm8<<2' operand.
957 uint32_t ARMMCCodeEmitter::
958 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
959                         SmallVectorImpl<MCFixup> &Fixups,
960                         const MCSubtargetInfo &STI) const {
961   // {11-8} = reg
962   // {7-0}  = imm8
963   const MCOperand &MO = MI.getOperand(OpIdx);
964   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
965   unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
966   unsigned Imm8 = MO1.getImm();
967   return (Reg << 8) | Imm8;
968 }
969 
970 // FIXME: This routine assumes that a binary
971 // expression will always result in a PCRel expression
972 // In reality, its only true if one or more subexpressions
973 // is itself a PCRel (i.e. "." in asm or some other pcrel construct)
974 // but this is good enough for now.
975 static bool EvaluateAsPCRel(const MCExpr *Expr) {
976   switch (Expr->getKind()) {
977   default: llvm_unreachable("Unexpected expression type");
978   case MCExpr::SymbolRef: return false;
979   case MCExpr::Binary: return true;
980   }
981 }
982 
983 uint32_t
984 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
985                                       SmallVectorImpl<MCFixup> &Fixups,
986                                       const MCSubtargetInfo &STI) const {
987   // {20-16} = imm{15-12}
988   // {11-0}  = imm{11-0}
989   const MCOperand &MO = MI.getOperand(OpIdx);
990   if (MO.isImm())
991     // Hi / lo 16 bits already extracted during earlier passes.
992     return static_cast<unsigned>(MO.getImm());
993 
994   // Handle :upper16: and :lower16: assembly prefixes.
995   const MCExpr *E = MO.getExpr();
996   MCFixupKind Kind;
997   if (E->getKind() == MCExpr::Target) {
998     const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
999     E = ARM16Expr->getSubExpr();
1000 
1001     if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) {
1002       const int64_t Value = MCE->getValue();
1003       if (Value > UINT32_MAX)
1004         report_fatal_error("constant value truncated (limited to 32-bit)");
1005 
1006       switch (ARM16Expr->getKind()) {
1007       case ARMMCExpr::VK_ARM_HI16:
1008         return (int32_t(Value) & 0xffff0000) >> 16;
1009       case ARMMCExpr::VK_ARM_LO16:
1010         return (int32_t(Value) & 0x0000ffff);
1011       default: llvm_unreachable("Unsupported ARMFixup");
1012       }
1013     }
1014 
1015     switch (ARM16Expr->getKind()) {
1016     default: llvm_unreachable("Unsupported ARMFixup");
1017     case ARMMCExpr::VK_ARM_HI16:
1018       if (!isTargetMachO(STI) && EvaluateAsPCRel(E))
1019         Kind = MCFixupKind(isThumb2(STI)
1020                            ? ARM::fixup_t2_movt_hi16_pcrel
1021                            : ARM::fixup_arm_movt_hi16_pcrel);
1022       else
1023         Kind = MCFixupKind(isThumb2(STI)
1024                            ? ARM::fixup_t2_movt_hi16
1025                            : ARM::fixup_arm_movt_hi16);
1026       break;
1027     case ARMMCExpr::VK_ARM_LO16:
1028       if (!isTargetMachO(STI) && EvaluateAsPCRel(E))
1029         Kind = MCFixupKind(isThumb2(STI)
1030                            ? ARM::fixup_t2_movw_lo16_pcrel
1031                            : ARM::fixup_arm_movw_lo16_pcrel);
1032       else
1033         Kind = MCFixupKind(isThumb2(STI)
1034                            ? ARM::fixup_t2_movw_lo16
1035                            : ARM::fixup_arm_movw_lo16);
1036       break;
1037     }
1038     Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
1039     return 0;
1040   }
1041   // If the expression doesn't have :upper16: or :lower16: on it,
1042   // it's just a plain immediate expression, and those evaluate to
1043   // the lower 16 bits of the expression regardless of whether
1044   // we have a movt or a movw.
1045   if (!isTargetMachO(STI) && EvaluateAsPCRel(E))
1046     Kind = MCFixupKind(isThumb2(STI)
1047                        ? ARM::fixup_t2_movw_lo16_pcrel
1048                        : ARM::fixup_arm_movw_lo16_pcrel);
1049   else
1050     Kind = MCFixupKind(isThumb2(STI)
1051                        ? ARM::fixup_t2_movw_lo16
1052                        : ARM::fixup_arm_movw_lo16);
1053   Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
1054   return 0;
1055 }
1056 
1057 uint32_t ARMMCCodeEmitter::
1058 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1059                     SmallVectorImpl<MCFixup> &Fixups,
1060                     const MCSubtargetInfo &STI) const {
1061   const MCOperand &MO = MI.getOperand(OpIdx);
1062   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1063   const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1064   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1065   unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1066   unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
1067   bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
1068   ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
1069   unsigned SBits = getShiftOp(ShOp);
1070 
1071   // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1072   // amount. However, it would be an easy mistake to make so check here.
1073   assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
1074 
1075   // {16-13} = Rn
1076   // {12}    = isAdd
1077   // {11-0}  = shifter
1078   //  {3-0}  = Rm
1079   //  {4}    = 0
1080   //  {6-5}  = type
1081   //  {11-7} = imm
1082   uint32_t Binary = Rm;
1083   Binary |= Rn << 13;
1084   Binary |= SBits << 5;
1085   Binary |= ShImm << 7;
1086   if (isAdd)
1087     Binary |= 1 << 12;
1088   return Binary;
1089 }
1090 
1091 uint32_t ARMMCCodeEmitter::
1092 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
1093                     SmallVectorImpl<MCFixup> &Fixups,
1094                     const MCSubtargetInfo &STI) const {
1095   // {17-14}  Rn
1096   // {13}     1 == imm12, 0 == Rm
1097   // {12}     isAdd
1098   // {11-0}   imm12/Rm
1099   const MCOperand &MO = MI.getOperand(OpIdx);
1100   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1101   uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups, STI);
1102   Binary |= Rn << 14;
1103   return Binary;
1104 }
1105 
1106 uint32_t ARMMCCodeEmitter::
1107 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1108                           SmallVectorImpl<MCFixup> &Fixups,
1109                           const MCSubtargetInfo &STI) const {
1110   // {13}     1 == imm12, 0 == Rm
1111   // {12}     isAdd
1112   // {11-0}   imm12/Rm
1113   const MCOperand &MO = MI.getOperand(OpIdx);
1114   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1115   unsigned Imm = MO1.getImm();
1116   bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1117   bool isReg = MO.getReg() != 0;
1118   uint32_t Binary = ARM_AM::getAM2Offset(Imm);
1119   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
1120   if (isReg) {
1121     ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
1122     Binary <<= 7;                    // Shift amount is bits [11:7]
1123     Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1124     Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1125   }
1126   return Binary | (isAdd << 12) | (isReg << 13);
1127 }
1128 
1129 uint32_t ARMMCCodeEmitter::
1130 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1131                      SmallVectorImpl<MCFixup> &Fixups,
1132                      const MCSubtargetInfo &STI) const {
1133   // {4}      isAdd
1134   // {3-0}    Rm
1135   const MCOperand &MO = MI.getOperand(OpIdx);
1136   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1137   bool isAdd = MO1.getImm() != 0;
1138   return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
1139 }
1140 
1141 uint32_t ARMMCCodeEmitter::
1142 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1143                           SmallVectorImpl<MCFixup> &Fixups,
1144                           const MCSubtargetInfo &STI) const {
1145   // {9}      1 == imm8, 0 == Rm
1146   // {8}      isAdd
1147   // {7-4}    imm7_4/zero
1148   // {3-0}    imm3_0/Rm
1149   const MCOperand &MO = MI.getOperand(OpIdx);
1150   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1151   unsigned Imm = MO1.getImm();
1152   bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1153   bool isImm = MO.getReg() == 0;
1154   uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1155   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1156   if (!isImm)
1157     Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1158   return Imm8 | (isAdd << 8) | (isImm << 9);
1159 }
1160 
1161 uint32_t ARMMCCodeEmitter::
1162 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1163                     SmallVectorImpl<MCFixup> &Fixups,
1164                     const MCSubtargetInfo &STI) const {
1165   // {13}     1 == imm8, 0 == Rm
1166   // {12-9}   Rn
1167   // {8}      isAdd
1168   // {7-4}    imm7_4/zero
1169   // {3-0}    imm3_0/Rm
1170   const MCOperand &MO = MI.getOperand(OpIdx);
1171   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1172   const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1173 
1174   // If The first operand isn't a register, we have a label reference.
1175   if (!MO.isReg()) {
1176     unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1177 
1178     assert(MO.isExpr() && "Unexpected machine operand type!");
1179     const MCExpr *Expr = MO.getExpr();
1180     MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1181     Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1182 
1183     ++MCNumCPRelocations;
1184     return (Rn << 9) | (1 << 13);
1185   }
1186   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1187   unsigned Imm = MO2.getImm();
1188   bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1189   bool isImm = MO1.getReg() == 0;
1190   uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1191   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1192   if (!isImm)
1193     Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1194   return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1195 }
1196 
1197 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1198 uint32_t ARMMCCodeEmitter::
1199 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1200                           SmallVectorImpl<MCFixup> &Fixups,
1201                           const MCSubtargetInfo &STI) const {
1202   // [SP, #imm]
1203   //   {7-0} = imm8
1204   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1205   assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1206          "Unexpected base register!");
1207 
1208   // The immediate is already shifted for the implicit zeroes, so no change
1209   // here.
1210   return MO1.getImm() & 0xff;
1211 }
1212 
1213 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1214 uint32_t ARMMCCodeEmitter::
1215 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1216                      SmallVectorImpl<MCFixup> &Fixups,
1217                      const MCSubtargetInfo &STI) const {
1218   // [Rn, #imm]
1219   //   {7-3} = imm5
1220   //   {2-0} = Rn
1221   const MCOperand &MO = MI.getOperand(OpIdx);
1222   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1223   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1224   unsigned Imm5 = MO1.getImm();
1225   return ((Imm5 & 0x1f) << 3) | Rn;
1226 }
1227 
1228 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1229 uint32_t ARMMCCodeEmitter::
1230 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1231                      SmallVectorImpl<MCFixup> &Fixups,
1232                      const MCSubtargetInfo &STI) const {
1233   const MCOperand MO = MI.getOperand(OpIdx);
1234   if (MO.isExpr())
1235     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI);
1236   return (MO.getImm() >> 2);
1237 }
1238 
1239 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
1240 uint32_t ARMMCCodeEmitter::
1241 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1242                     SmallVectorImpl<MCFixup> &Fixups,
1243                     const MCSubtargetInfo &STI) const {
1244   // {12-9} = reg
1245   // {8}    = (U)nsigned (add == '1', sub == '0')
1246   // {7-0}  = imm8
1247   unsigned Reg, Imm8;
1248   bool isAdd;
1249   // If The first operand isn't a register, we have a label reference.
1250   const MCOperand &MO = MI.getOperand(OpIdx);
1251   if (!MO.isReg()) {
1252     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1253     Imm8 = 0;
1254     isAdd = false; // 'U' bit is handled as part of the fixup.
1255 
1256     assert(MO.isExpr() && "Unexpected machine operand type!");
1257     const MCExpr *Expr = MO.getExpr();
1258     MCFixupKind Kind;
1259     if (isThumb2(STI))
1260       Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1261     else
1262       Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1263     Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1264 
1265     ++MCNumCPRelocations;
1266   } else {
1267     EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1268     isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1269   }
1270 
1271   uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1272   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1273   if (isAdd)
1274     Binary |= (1 << 8);
1275   Binary |= (Reg << 9);
1276   return Binary;
1277 }
1278 
1279 unsigned ARMMCCodeEmitter::
1280 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1281                 SmallVectorImpl<MCFixup> &Fixups,
1282                 const MCSubtargetInfo &STI) const {
1283   // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1284   // shifted. The second is Rs, the amount to shift by, and the third specifies
1285   // the type of the shift.
1286   //
1287   // {3-0} = Rm.
1288   // {4}   = 1
1289   // {6-5} = type
1290   // {11-8} = Rs
1291   // {7}    = 0
1292 
1293   const MCOperand &MO  = MI.getOperand(OpIdx);
1294   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1295   const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1296   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1297 
1298   // Encode Rm.
1299   unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1300 
1301   // Encode the shift opcode.
1302   unsigned SBits = 0;
1303   unsigned Rs = MO1.getReg();
1304   if (Rs) {
1305     // Set shift operand (bit[7:4]).
1306     // LSL - 0001
1307     // LSR - 0011
1308     // ASR - 0101
1309     // ROR - 0111
1310     switch (SOpc) {
1311     default: llvm_unreachable("Unknown shift opc!");
1312     case ARM_AM::lsl: SBits = 0x1; break;
1313     case ARM_AM::lsr: SBits = 0x3; break;
1314     case ARM_AM::asr: SBits = 0x5; break;
1315     case ARM_AM::ror: SBits = 0x7; break;
1316     }
1317   }
1318 
1319   Binary |= SBits << 4;
1320 
1321   // Encode the shift operation Rs.
1322   // Encode Rs bit[11:8].
1323   assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1324   return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
1325 }
1326 
1327 unsigned ARMMCCodeEmitter::
1328 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1329                 SmallVectorImpl<MCFixup> &Fixups,
1330                 const MCSubtargetInfo &STI) const {
1331   // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1332   // shifted. The second is the amount to shift by.
1333   //
1334   // {3-0} = Rm.
1335   // {4}   = 0
1336   // {6-5} = type
1337   // {11-7} = imm
1338 
1339   const MCOperand &MO  = MI.getOperand(OpIdx);
1340   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1341   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1342 
1343   // Encode Rm.
1344   unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1345 
1346   // Encode the shift opcode.
1347   unsigned SBits = 0;
1348 
1349   // Set shift operand (bit[6:4]).
1350   // LSL - 000
1351   // LSR - 010
1352   // ASR - 100
1353   // ROR - 110
1354   // RRX - 110 and bit[11:8] clear.
1355   switch (SOpc) {
1356   default: llvm_unreachable("Unknown shift opc!");
1357   case ARM_AM::lsl: SBits = 0x0; break;
1358   case ARM_AM::lsr: SBits = 0x2; break;
1359   case ARM_AM::asr: SBits = 0x4; break;
1360   case ARM_AM::ror: SBits = 0x6; break;
1361   case ARM_AM::rrx:
1362     Binary |= 0x60;
1363     return Binary;
1364   }
1365 
1366   // Encode shift_imm bit[11:7].
1367   Binary |= SBits << 4;
1368   unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1369   assert(Offset < 32 && "Offset must be in range 0-31!");
1370   return Binary | (Offset << 7);
1371 }
1372 
1373 
1374 unsigned ARMMCCodeEmitter::
1375 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1376                 SmallVectorImpl<MCFixup> &Fixups,
1377                 const MCSubtargetInfo &STI) const {
1378   const MCOperand &MO1 = MI.getOperand(OpNum);
1379   const MCOperand &MO2 = MI.getOperand(OpNum+1);
1380   const MCOperand &MO3 = MI.getOperand(OpNum+2);
1381 
1382   // Encoded as [Rn, Rm, imm].
1383   // FIXME: Needs fixup support.
1384   unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1385   Value <<= 4;
1386   Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1387   Value <<= 2;
1388   Value |= MO3.getImm();
1389 
1390   return Value;
1391 }
1392 
1393 unsigned ARMMCCodeEmitter::
1394 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1395                          SmallVectorImpl<MCFixup> &Fixups,
1396                          const MCSubtargetInfo &STI) const {
1397   const MCOperand &MO1 = MI.getOperand(OpNum);
1398   const MCOperand &MO2 = MI.getOperand(OpNum+1);
1399 
1400   // FIXME: Needs fixup support.
1401   unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1402 
1403   // Even though the immediate is 8 bits long, we need 9 bits in order
1404   // to represent the (inverse of the) sign bit.
1405   Value <<= 9;
1406   int32_t tmp = (int32_t)MO2.getImm();
1407   if (tmp < 0)
1408     tmp = abs(tmp);
1409   else
1410     Value |= 256; // Set the ADD bit
1411   Value |= tmp & 255;
1412   return Value;
1413 }
1414 
1415 unsigned ARMMCCodeEmitter::
1416 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1417                          SmallVectorImpl<MCFixup> &Fixups,
1418                          const MCSubtargetInfo &STI) const {
1419   const MCOperand &MO1 = MI.getOperand(OpNum);
1420 
1421   // FIXME: Needs fixup support.
1422   unsigned Value = 0;
1423   int32_t tmp = (int32_t)MO1.getImm();
1424   if (tmp < 0)
1425     tmp = abs(tmp);
1426   else
1427     Value |= 256; // Set the ADD bit
1428   Value |= tmp & 255;
1429   return Value;
1430 }
1431 
1432 unsigned ARMMCCodeEmitter::
1433 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1434                          SmallVectorImpl<MCFixup> &Fixups,
1435                          const MCSubtargetInfo &STI) const {
1436   const MCOperand &MO1 = MI.getOperand(OpNum);
1437 
1438   // FIXME: Needs fixup support.
1439   unsigned Value = 0;
1440   int32_t tmp = (int32_t)MO1.getImm();
1441   if (tmp < 0)
1442     tmp = abs(tmp);
1443   else
1444     Value |= 4096; // Set the ADD bit
1445   Value |= tmp & 4095;
1446   return Value;
1447 }
1448 
1449 unsigned ARMMCCodeEmitter::
1450 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1451                 SmallVectorImpl<MCFixup> &Fixups,
1452                 const MCSubtargetInfo &STI) const {
1453   // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1454   // shifted. The second is the amount to shift by.
1455   //
1456   // {3-0} = Rm.
1457   // {4}   = 0
1458   // {6-5} = type
1459   // {11-7} = imm
1460 
1461   const MCOperand &MO  = MI.getOperand(OpIdx);
1462   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1463   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1464 
1465   // Encode Rm.
1466   unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1467 
1468   // Encode the shift opcode.
1469   unsigned SBits = 0;
1470   // Set shift operand (bit[6:4]).
1471   // LSL - 000
1472   // LSR - 010
1473   // ASR - 100
1474   // ROR - 110
1475   switch (SOpc) {
1476   default: llvm_unreachable("Unknown shift opc!");
1477   case ARM_AM::lsl: SBits = 0x0; break;
1478   case ARM_AM::lsr: SBits = 0x2; break;
1479   case ARM_AM::asr: SBits = 0x4; break;
1480   case ARM_AM::rrx: // FALLTHROUGH
1481   case ARM_AM::ror: SBits = 0x6; break;
1482   }
1483 
1484   Binary |= SBits << 4;
1485   if (SOpc == ARM_AM::rrx)
1486     return Binary;
1487 
1488   // Encode shift_imm bit[11:7].
1489   return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1490 }
1491 
1492 unsigned ARMMCCodeEmitter::
1493 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1494                                SmallVectorImpl<MCFixup> &Fixups,
1495                                const MCSubtargetInfo &STI) const {
1496   // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1497   // msb of the mask.
1498   const MCOperand &MO = MI.getOperand(Op);
1499   uint32_t v = ~MO.getImm();
1500   uint32_t lsb = countTrailingZeros(v);
1501   uint32_t msb = (32 - countLeadingZeros (v)) - 1;
1502   assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1503   return lsb | (msb << 5);
1504 }
1505 
1506 unsigned ARMMCCodeEmitter::
1507 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1508                        SmallVectorImpl<MCFixup> &Fixups,
1509                        const MCSubtargetInfo &STI) const {
1510   // VLDM/VSTM:
1511   //   {12-8} = Vd
1512   //   {7-0}  = Number of registers
1513   //
1514   // LDM/STM:
1515   //   {15-0}  = Bitfield of GPRs.
1516   unsigned Reg = MI.getOperand(Op).getReg();
1517   bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1518   bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1519 
1520   unsigned Binary = 0;
1521 
1522   if (SPRRegs || DPRRegs) {
1523     // VLDM/VSTM
1524     unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1525     unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1526     Binary |= (RegNo & 0x1f) << 8;
1527     if (SPRRegs)
1528       Binary |= NumRegs;
1529     else
1530       Binary |= NumRegs * 2;
1531   } else {
1532     for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1533       unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(MI.getOperand(I).getReg());
1534       Binary |= 1 << RegNo;
1535     }
1536   }
1537 
1538   return Binary;
1539 }
1540 
1541 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1542 /// with the alignment operand.
1543 unsigned ARMMCCodeEmitter::
1544 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1545                            SmallVectorImpl<MCFixup> &Fixups,
1546                            const MCSubtargetInfo &STI) const {
1547   const MCOperand &Reg = MI.getOperand(Op);
1548   const MCOperand &Imm = MI.getOperand(Op + 1);
1549 
1550   unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1551   unsigned Align = 0;
1552 
1553   switch (Imm.getImm()) {
1554   default: break;
1555   case 2:
1556   case 4:
1557   case 8:  Align = 0x01; break;
1558   case 16: Align = 0x02; break;
1559   case 32: Align = 0x03; break;
1560   }
1561 
1562   return RegNo | (Align << 4);
1563 }
1564 
1565 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1566 /// along  with the alignment operand for use in VST1 and VLD1 with size 32.
1567 unsigned ARMMCCodeEmitter::
1568 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1569                                     SmallVectorImpl<MCFixup> &Fixups,
1570                                     const MCSubtargetInfo &STI) const {
1571   const MCOperand &Reg = MI.getOperand(Op);
1572   const MCOperand &Imm = MI.getOperand(Op + 1);
1573 
1574   unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1575   unsigned Align = 0;
1576 
1577   switch (Imm.getImm()) {
1578   default: break;
1579   case 8:
1580   case 16:
1581   case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1582   case 2: Align = 0x00; break;
1583   case 4: Align = 0x03; break;
1584   }
1585 
1586   return RegNo | (Align << 4);
1587 }
1588 
1589 
1590 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1591 /// alignment operand for use in VLD-dup instructions.  This is the same as
1592 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1593 /// different for VLD4-dup.
1594 unsigned ARMMCCodeEmitter::
1595 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1596                               SmallVectorImpl<MCFixup> &Fixups,
1597                               const MCSubtargetInfo &STI) const {
1598   const MCOperand &Reg = MI.getOperand(Op);
1599   const MCOperand &Imm = MI.getOperand(Op + 1);
1600 
1601   unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1602   unsigned Align = 0;
1603 
1604   switch (Imm.getImm()) {
1605   default: break;
1606   case 2:
1607   case 4:
1608   case 8:  Align = 0x01; break;
1609   case 16: Align = 0x03; break;
1610   }
1611 
1612   return RegNo | (Align << 4);
1613 }
1614 
1615 unsigned ARMMCCodeEmitter::
1616 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1617                           SmallVectorImpl<MCFixup> &Fixups,
1618                           const MCSubtargetInfo &STI) const {
1619   const MCOperand &MO = MI.getOperand(Op);
1620   if (MO.getReg() == 0) return 0x0D;
1621   return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1622 }
1623 
1624 unsigned ARMMCCodeEmitter::
1625 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1626                   SmallVectorImpl<MCFixup> &Fixups,
1627                   const MCSubtargetInfo &STI) const {
1628   return 8 - MI.getOperand(Op).getImm();
1629 }
1630 
1631 unsigned ARMMCCodeEmitter::
1632 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1633                    SmallVectorImpl<MCFixup> &Fixups,
1634                    const MCSubtargetInfo &STI) const {
1635   return 16 - MI.getOperand(Op).getImm();
1636 }
1637 
1638 unsigned ARMMCCodeEmitter::
1639 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1640                    SmallVectorImpl<MCFixup> &Fixups,
1641                    const MCSubtargetInfo &STI) const {
1642   return 32 - MI.getOperand(Op).getImm();
1643 }
1644 
1645 unsigned ARMMCCodeEmitter::
1646 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1647                    SmallVectorImpl<MCFixup> &Fixups,
1648                    const MCSubtargetInfo &STI) const {
1649   return 64 - MI.getOperand(Op).getImm();
1650 }
1651 
1652 void ARMMCCodeEmitter::
1653 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1654                   SmallVectorImpl<MCFixup> &Fixups,
1655                   const MCSubtargetInfo &STI) const {
1656   // Pseudo instructions don't get encoded.
1657   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1658   uint64_t TSFlags = Desc.TSFlags;
1659   if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1660     return;
1661 
1662   int Size;
1663   if (Desc.getSize() == 2 || Desc.getSize() == 4)
1664     Size = Desc.getSize();
1665   else
1666     llvm_unreachable("Unexpected instruction size!");
1667 
1668   uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1669   // Thumb 32-bit wide instructions need to emit the high order halfword
1670   // first.
1671   if (isThumb(STI) && Size == 4) {
1672     EmitConstant(Binary >> 16, 2, OS);
1673     EmitConstant(Binary & 0xffff, 2, OS);
1674   } else
1675     EmitConstant(Binary, Size, OS);
1676   ++MCNumEmitted;  // Keep track of the # of mi's emitted.
1677 }
1678 
1679 #include "ARMGenMCCodeEmitter.inc"
1680