1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARMMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMFixupKinds.h"
18 #include "MCTargetDesc/ARMMCExpr.h"
19 #include "MCTargetDesc/ARMMCTargetDesc.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/ADT/APFloat.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/raw_ostream.h"
29 
30 using namespace llvm;
31 
32 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
33 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
34 
35 namespace {
36 class ARMMCCodeEmitter : public MCCodeEmitter {
37   ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
38   void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
39   const MCInstrInfo &MCII;
40   const MCSubtargetInfo &STI;
41 
42 public:
43   ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
44                    MCContext &ctx)
45     : MCII(mcii), STI(sti) {
46   }
47 
48   ~ARMMCCodeEmitter() {}
49 
50   bool isThumb() const {
51     // FIXME: Can tablegen auto-generate this?
52     return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
53   }
54   bool isThumb2() const {
55     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
56   }
57   bool isTargetDarwin() const {
58     Triple TT(STI.getTargetTriple());
59     Triple::OSType OS = TT.getOS();
60     return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS;
61   }
62 
63   unsigned getMachineSoImmOpValue(unsigned SoImm) const;
64 
65   // getBinaryCodeForInstr - TableGen'erated function for getting the
66   // binary encoding for an instruction.
67   uint64_t getBinaryCodeForInstr(const MCInst &MI,
68                                  SmallVectorImpl<MCFixup> &Fixups) const;
69 
70   /// getMachineOpValue - Return binary encoding of operand. If the machine
71   /// operand requires relocation, record the relocation and return zero.
72   unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
73                              SmallVectorImpl<MCFixup> &Fixups) const;
74 
75   /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
76   /// the specified operand. This is used for operands with :lower16: and
77   /// :upper16: prefixes.
78   uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
79                                SmallVectorImpl<MCFixup> &Fixups) const;
80 
81   bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
82                               unsigned &Reg, unsigned &Imm,
83                               SmallVectorImpl<MCFixup> &Fixups) const;
84 
85   /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
86   /// BL branch target.
87   uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
88                                    SmallVectorImpl<MCFixup> &Fixups) const;
89 
90   /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
91   /// BLX branch target.
92   uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
93                                     SmallVectorImpl<MCFixup> &Fixups) const;
94 
95   /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
96   uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
97                                    SmallVectorImpl<MCFixup> &Fixups) const;
98 
99   /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
100   uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
101                                     SmallVectorImpl<MCFixup> &Fixups) const;
102 
103   /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
104   uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
105                                    SmallVectorImpl<MCFixup> &Fixups) const;
106 
107   /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
108   /// branch target.
109   uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
110                                   SmallVectorImpl<MCFixup> &Fixups) const;
111 
112   /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
113   /// immediate Thumb2 direct branch target.
114   uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
115                                   SmallVectorImpl<MCFixup> &Fixups) const;
116 
117   /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
118   /// branch target.
119   uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
120                                      SmallVectorImpl<MCFixup> &Fixups) const;
121   uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
122                                  SmallVectorImpl<MCFixup> &Fixups) const;
123   uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
124                                   SmallVectorImpl<MCFixup> &Fixups) const;
125 
126   /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
127   /// ADR label target.
128   uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
129                               SmallVectorImpl<MCFixup> &Fixups) const;
130   uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
131                               SmallVectorImpl<MCFixup> &Fixups) const;
132   uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
133                               SmallVectorImpl<MCFixup> &Fixups) const;
134 
135 
136   /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
137   /// operand.
138   uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
139                                    SmallVectorImpl<MCFixup> &Fixups) const;
140 
141   /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
142   uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
143                                          SmallVectorImpl<MCFixup> &Fixups)const;
144 
145   /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
146   /// operand.
147   uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
148                                    SmallVectorImpl<MCFixup> &Fixups) const;
149 
150   /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
151   /// operand.
152   uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
153                                    SmallVectorImpl<MCFixup> &Fixups) const;
154 
155   /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
156   /// operand.
157   uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
158                               SmallVectorImpl<MCFixup> &Fixups) const;
159 
160 
161   /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
162   /// operand as needed by load/store instructions.
163   uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
164                                SmallVectorImpl<MCFixup> &Fixups) const;
165 
166   /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
167   uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
168                                SmallVectorImpl<MCFixup> &Fixups) const {
169     ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
170     switch (Mode) {
171     default: llvm_unreachable("Unknown addressing sub-mode!");
172     case ARM_AM::da: return 0;
173     case ARM_AM::ia: return 1;
174     case ARM_AM::db: return 2;
175     case ARM_AM::ib: return 3;
176     }
177   }
178   /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
179   ///
180   unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
181     switch (ShOpc) {
182     case ARM_AM::no_shift:
183     case ARM_AM::lsl: return 0;
184     case ARM_AM::lsr: return 1;
185     case ARM_AM::asr: return 2;
186     case ARM_AM::ror:
187     case ARM_AM::rrx: return 3;
188     }
189     llvm_unreachable("Invalid ShiftOpc!");
190   }
191 
192   /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
193   uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
194                                SmallVectorImpl<MCFixup> &Fixups) const;
195 
196   /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
197   uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
198                                      SmallVectorImpl<MCFixup> &Fixups) const;
199 
200   /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
201   uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
202                                 SmallVectorImpl<MCFixup> &Fixups) const;
203 
204   /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
205   uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
206                                      SmallVectorImpl<MCFixup> &Fixups) const;
207 
208   /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
209   uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
210                                SmallVectorImpl<MCFixup> &Fixups) const;
211 
212   /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
213   /// operand.
214   uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
215                                      SmallVectorImpl<MCFixup> &Fixups) const;
216 
217   /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
218   uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
219                                 SmallVectorImpl<MCFixup> &Fixups) const;
220 
221   /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
222   uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
223                                 SmallVectorImpl<MCFixup> &Fixups) const;
224 
225   /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
226   uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
227                                SmallVectorImpl<MCFixup> &Fixups) const;
228 
229   /// getCCOutOpValue - Return encoding of the 's' bit.
230   unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
231                            SmallVectorImpl<MCFixup> &Fixups) const {
232     // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
233     // '1' respectively.
234     return MI.getOperand(Op).getReg() == ARM::CPSR;
235   }
236 
237   /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
238   unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
239                            SmallVectorImpl<MCFixup> &Fixups) const {
240     unsigned SoImm = MI.getOperand(Op).getImm();
241     int SoImmVal = ARM_AM::getSOImmVal(SoImm);
242     assert(SoImmVal != -1 && "Not a valid so_imm value!");
243 
244     // Encode rotate_imm.
245     unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
246       << ARMII::SoRotImmShift;
247 
248     // Encode immed_8.
249     Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
250     return Binary;
251   }
252 
253   /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
254   unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
255                            SmallVectorImpl<MCFixup> &Fixups) const {
256     unsigned SoImm = MI.getOperand(Op).getImm();
257     unsigned Encoded =  ARM_AM::getT2SOImmVal(SoImm);
258     assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
259     return Encoded;
260   }
261 
262   unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
263     SmallVectorImpl<MCFixup> &Fixups) const;
264   unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
265     SmallVectorImpl<MCFixup> &Fixups) const;
266   unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
267     SmallVectorImpl<MCFixup> &Fixups) const;
268   unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
269     SmallVectorImpl<MCFixup> &Fixups) const;
270 
271   /// getSORegOpValue - Return an encoded so_reg shifted register value.
272   unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
273                            SmallVectorImpl<MCFixup> &Fixups) const;
274   unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
275                            SmallVectorImpl<MCFixup> &Fixups) const;
276   unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
277                              SmallVectorImpl<MCFixup> &Fixups) const;
278 
279   unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
280                                    SmallVectorImpl<MCFixup> &Fixups) const {
281     return 64 - MI.getOperand(Op).getImm();
282   }
283 
284   unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
285                                       SmallVectorImpl<MCFixup> &Fixups) const;
286 
287   unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
288                                   SmallVectorImpl<MCFixup> &Fixups) const;
289   unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
290                                       SmallVectorImpl<MCFixup> &Fixups) const;
291   unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
292                                         SmallVectorImpl<MCFixup> &Fixups) const;
293   unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
294                                         SmallVectorImpl<MCFixup> &Fixups) const;
295   unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
296                                      SmallVectorImpl<MCFixup> &Fixups) const;
297 
298   unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
299                              SmallVectorImpl<MCFixup> &Fixups) const;
300   unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
301                               SmallVectorImpl<MCFixup> &Fixups) const;
302   unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
303                               SmallVectorImpl<MCFixup> &Fixups) const;
304   unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
305                               SmallVectorImpl<MCFixup> &Fixups) const;
306 
307   unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
308                                  SmallVectorImpl<MCFixup> &Fixups) const;
309 
310   unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
311                                       unsigned EncodedValue) const;
312   unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
313                                           unsigned EncodedValue) const;
314   unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
315                                     unsigned EncodedValue) const;
316 
317   unsigned VFPThumb2PostEncoder(const MCInst &MI,
318                                 unsigned EncodedValue) const;
319 
320   void EmitByte(unsigned char C, raw_ostream &OS) const {
321     OS << (char)C;
322   }
323 
324   void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
325     // Output the constant in little endian byte order.
326     for (unsigned i = 0; i != Size; ++i) {
327       EmitByte(Val & 255, OS);
328       Val >>= 8;
329     }
330   }
331 
332   void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
333                          SmallVectorImpl<MCFixup> &Fixups) const;
334 };
335 
336 } // end anonymous namespace
337 
338 MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
339                                             const MCRegisterInfo &MRI,
340                                             const MCSubtargetInfo &STI,
341                                             MCContext &Ctx) {
342   return new ARMMCCodeEmitter(MCII, STI, Ctx);
343 }
344 
345 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
346 /// instructions, and rewrite them to their Thumb2 form if we are currently in
347 /// Thumb2 mode.
348 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
349                                                  unsigned EncodedValue) const {
350   if (isThumb2()) {
351     // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
352     // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
353     // set to 1111.
354     unsigned Bit24 = EncodedValue & 0x01000000;
355     unsigned Bit28 = Bit24 << 4;
356     EncodedValue &= 0xEFFFFFFF;
357     EncodedValue |= Bit28;
358     EncodedValue |= 0x0F000000;
359   }
360 
361   return EncodedValue;
362 }
363 
364 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
365 /// instructions, and rewrite them to their Thumb2 form if we are currently in
366 /// Thumb2 mode.
367 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
368                                                  unsigned EncodedValue) const {
369   if (isThumb2()) {
370     EncodedValue &= 0xF0FFFFFF;
371     EncodedValue |= 0x09000000;
372   }
373 
374   return EncodedValue;
375 }
376 
377 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
378 /// instructions, and rewrite them to their Thumb2 form if we are currently in
379 /// Thumb2 mode.
380 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
381                                                  unsigned EncodedValue) const {
382   if (isThumb2()) {
383     EncodedValue &= 0x00FFFFFF;
384     EncodedValue |= 0xEE000000;
385   }
386 
387   return EncodedValue;
388 }
389 
390 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
391 /// them to their Thumb2 form if we are currently in Thumb2 mode.
392 unsigned ARMMCCodeEmitter::
393 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
394   if (isThumb2()) {
395     EncodedValue &= 0x0FFFFFFF;
396     EncodedValue |= 0xE0000000;
397   }
398   return EncodedValue;
399 }
400 
401 /// getMachineOpValue - Return binary encoding of operand. If the machine
402 /// operand requires relocation, record the relocation and return zero.
403 unsigned ARMMCCodeEmitter::
404 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
405                   SmallVectorImpl<MCFixup> &Fixups) const {
406   if (MO.isReg()) {
407     unsigned Reg = MO.getReg();
408     unsigned RegNo = getARMRegisterNumbering(Reg);
409 
410     // Q registers are encoded as 2x their register number.
411     switch (Reg) {
412     default:
413       return RegNo;
414     case ARM::Q0:  case ARM::Q1:  case ARM::Q2:  case ARM::Q3:
415     case ARM::Q4:  case ARM::Q5:  case ARM::Q6:  case ARM::Q7:
416     case ARM::Q8:  case ARM::Q9:  case ARM::Q10: case ARM::Q11:
417     case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
418       return 2 * RegNo;
419     }
420   } else if (MO.isImm()) {
421     return static_cast<unsigned>(MO.getImm());
422   } else if (MO.isFPImm()) {
423     return static_cast<unsigned>(APFloat(MO.getFPImm())
424                      .bitcastToAPInt().getHiBits(32).getLimitedValue());
425   }
426 
427   llvm_unreachable("Unable to encode MCOperand!");
428 }
429 
430 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
431 bool ARMMCCodeEmitter::
432 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
433                        unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
434   const MCOperand &MO  = MI.getOperand(OpIdx);
435   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
436 
437   Reg = getARMRegisterNumbering(MO.getReg());
438 
439   int32_t SImm = MO1.getImm();
440   bool isAdd = true;
441 
442   // Special value for #-0
443   if (SImm == INT32_MIN) {
444     SImm = 0;
445     isAdd = false;
446   }
447 
448   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
449   if (SImm < 0) {
450     SImm = -SImm;
451     isAdd = false;
452   }
453 
454   Imm = SImm;
455   return isAdd;
456 }
457 
458 /// getBranchTargetOpValue - Helper function to get the branch target operand,
459 /// which is either an immediate or requires a fixup.
460 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
461                                        unsigned FixupKind,
462                                        SmallVectorImpl<MCFixup> &Fixups) {
463   const MCOperand &MO = MI.getOperand(OpIdx);
464 
465   // If the destination is an immediate, we have nothing to do.
466   if (MO.isImm()) return MO.getImm();
467   assert(MO.isExpr() && "Unexpected branch target type!");
468   const MCExpr *Expr = MO.getExpr();
469   MCFixupKind Kind = MCFixupKind(FixupKind);
470   Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
471 
472   // All of the information is in the fixup.
473   return 0;
474 }
475 
476 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
477 // determined by negating them and XOR'ing them with bit 23.
478 static int32_t encodeThumbBLOffset(int32_t offset) {
479   offset >>= 1;
480   uint32_t S  = (offset & 0x800000) >> 23;
481   uint32_t J1 = (offset & 0x400000) >> 22;
482   uint32_t J2 = (offset & 0x200000) >> 21;
483   J1 = (~J1 & 0x1);
484   J2 = (~J2 & 0x1);
485   J1 ^= S;
486   J2 ^= S;
487 
488   offset &= ~0x600000;
489   offset |= J1 << 22;
490   offset |= J2 << 21;
491 
492   return offset;
493 }
494 
495 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
496 uint32_t ARMMCCodeEmitter::
497 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
498                         SmallVectorImpl<MCFixup> &Fixups) const {
499   const MCOperand MO = MI.getOperand(OpIdx);
500   if (MO.isExpr())
501     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
502                                     Fixups);
503   return encodeThumbBLOffset(MO.getImm());
504 }
505 
506 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
507 /// BLX branch target.
508 uint32_t ARMMCCodeEmitter::
509 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
510                          SmallVectorImpl<MCFixup> &Fixups) const {
511   const MCOperand MO = MI.getOperand(OpIdx);
512   if (MO.isExpr())
513     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
514                                     Fixups);
515   return encodeThumbBLOffset(MO.getImm());
516 }
517 
518 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
519 uint32_t ARMMCCodeEmitter::
520 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
521                         SmallVectorImpl<MCFixup> &Fixups) const {
522   const MCOperand MO = MI.getOperand(OpIdx);
523   if (MO.isExpr())
524     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
525                                     Fixups);
526   return (MO.getImm() >> 1);
527 }
528 
529 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
530 uint32_t ARMMCCodeEmitter::
531 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
532                          SmallVectorImpl<MCFixup> &Fixups) const {
533   const MCOperand MO = MI.getOperand(OpIdx);
534   if (MO.isExpr())
535     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
536                                     Fixups);
537   return (MO.getImm() >> 1);
538 }
539 
540 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
541 uint32_t ARMMCCodeEmitter::
542 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
543                         SmallVectorImpl<MCFixup> &Fixups) const {
544   const MCOperand MO = MI.getOperand(OpIdx);
545   if (MO.isExpr())
546     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
547   return (MO.getImm() >> 1);
548 }
549 
550 /// Return true if this branch has a non-always predication
551 static bool HasConditionalBranch(const MCInst &MI) {
552   int NumOp = MI.getNumOperands();
553   if (NumOp >= 2) {
554     for (int i = 0; i < NumOp-1; ++i) {
555       const MCOperand &MCOp1 = MI.getOperand(i);
556       const MCOperand &MCOp2 = MI.getOperand(i + 1);
557       if (MCOp1.isImm() && MCOp2.isReg() &&
558           (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
559         if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
560           return true;
561       }
562     }
563   }
564   return false;
565 }
566 
567 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
568 /// target.
569 uint32_t ARMMCCodeEmitter::
570 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
571                        SmallVectorImpl<MCFixup> &Fixups) const {
572   // FIXME: This really, really shouldn't use TargetMachine. We don't want
573   // coupling between MC and TM anywhere we can help it.
574   if (isThumb2())
575     return
576       ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
577   return getARMBranchTargetOpValue(MI, OpIdx, Fixups);
578 }
579 
580 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
581 /// target.
582 uint32_t ARMMCCodeEmitter::
583 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
584                           SmallVectorImpl<MCFixup> &Fixups) const {
585   const MCOperand MO = MI.getOperand(OpIdx);
586   if (MO.isExpr()) {
587     if (HasConditionalBranch(MI))
588       return ::getBranchTargetOpValue(MI, OpIdx,
589                                       ARM::fixup_arm_condbranch, Fixups);
590     return ::getBranchTargetOpValue(MI, OpIdx,
591                                     ARM::fixup_arm_uncondbranch, Fixups);
592   }
593 
594   return MO.getImm() >> 2;
595 }
596 
597 uint32_t ARMMCCodeEmitter::
598 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
599                           SmallVectorImpl<MCFixup> &Fixups) const {
600   const MCOperand MO = MI.getOperand(OpIdx);
601   if (MO.isExpr()) {
602     if (HasConditionalBranch(MI))
603       return ::getBranchTargetOpValue(MI, OpIdx,
604                                       ARM::fixup_arm_condbl, Fixups);
605     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups);
606   }
607 
608   return MO.getImm() >> 2;
609 }
610 
611 uint32_t ARMMCCodeEmitter::
612 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
613                           SmallVectorImpl<MCFixup> &Fixups) const {
614   const MCOperand MO = MI.getOperand(OpIdx);
615   if (MO.isExpr())
616     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups);
617 
618   return MO.getImm() >> 1;
619 }
620 
621 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
622 /// immediate branch target.
623 uint32_t ARMMCCodeEmitter::
624 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
625                        SmallVectorImpl<MCFixup> &Fixups) const {
626   unsigned Val =
627     ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
628   bool I  = (Val & 0x800000);
629   bool J1 = (Val & 0x400000);
630   bool J2 = (Val & 0x200000);
631   if (I ^ J1)
632     Val &= ~0x400000;
633   else
634     Val |= 0x400000;
635 
636   if (I ^ J2)
637     Val &= ~0x200000;
638   else
639     Val |= 0x200000;
640 
641   return Val;
642 }
643 
644 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
645 /// target.
646 uint32_t ARMMCCodeEmitter::
647 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
648                    SmallVectorImpl<MCFixup> &Fixups) const {
649   const MCOperand MO = MI.getOperand(OpIdx);
650   if (MO.isExpr())
651     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
652                                     Fixups);
653   int32_t offset = MO.getImm();
654   uint32_t Val = 0x2000;
655   if (offset < 0) {
656     Val = 0x1000;
657     offset *= -1;
658   }
659   Val |= offset;
660   return Val;
661 }
662 
663 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
664 /// target.
665 uint32_t ARMMCCodeEmitter::
666 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
667                    SmallVectorImpl<MCFixup> &Fixups) const {
668   const MCOperand MO = MI.getOperand(OpIdx);
669   if (MO.isExpr())
670     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
671                                     Fixups);
672   int32_t Val = MO.getImm();
673   if (Val < 0) {
674     Val *= -1;
675     Val |= 0x1000;
676   }
677   return Val;
678 }
679 
680 /// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
681 /// target.
682 uint32_t ARMMCCodeEmitter::
683 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
684                    SmallVectorImpl<MCFixup> &Fixups) const {
685   const MCOperand MO = MI.getOperand(OpIdx);
686   if (MO.isExpr())
687     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
688                                     Fixups);
689   return MO.getImm();
690 }
691 
692 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
693 /// operand.
694 uint32_t ARMMCCodeEmitter::
695 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
696                               SmallVectorImpl<MCFixup> &) const {
697   // [Rn, Rm]
698   //   {5-3} = Rm
699   //   {2-0} = Rn
700   const MCOperand &MO1 = MI.getOperand(OpIdx);
701   const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
702   unsigned Rn = getARMRegisterNumbering(MO1.getReg());
703   unsigned Rm = getARMRegisterNumbering(MO2.getReg());
704   return (Rm << 3) | Rn;
705 }
706 
707 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
708 uint32_t ARMMCCodeEmitter::
709 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
710                         SmallVectorImpl<MCFixup> &Fixups) const {
711   // {17-13} = reg
712   // {12}    = (U)nsigned (add == '1', sub == '0')
713   // {11-0}  = imm12
714   unsigned Reg, Imm12;
715   bool isAdd = true;
716   // If The first operand isn't a register, we have a label reference.
717   const MCOperand &MO = MI.getOperand(OpIdx);
718   if (!MO.isReg()) {
719     Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
720     Imm12 = 0;
721     isAdd = false ; // 'U' bit is set as part of the fixup.
722 
723     if (MO.isExpr()) {
724       const MCExpr *Expr = MO.getExpr();
725 
726       MCFixupKind Kind;
727       if (isThumb2())
728         Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
729       else
730         Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
731       Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
732 
733       ++MCNumCPRelocations;
734     } else {
735       Reg = ARM::PC;
736       int32_t Offset = MO.getImm();
737       // FIXME: Handle #-0.
738       if (Offset < 0) {
739         Offset *= -1;
740         isAdd = false;
741       }
742       Imm12 = Offset;
743     }
744   } else
745     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
746 
747   uint32_t Binary = Imm12 & 0xfff;
748   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
749   if (isAdd)
750     Binary |= (1 << 12);
751   Binary |= (Reg << 13);
752   return Binary;
753 }
754 
755 /// getT2Imm8s4OpValue - Return encoding info for
756 /// '+/- imm8<<2' operand.
757 uint32_t ARMMCCodeEmitter::
758 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
759                    SmallVectorImpl<MCFixup> &Fixups) const {
760   // FIXME: The immediate operand should have already been encoded like this
761   // before ever getting here. The encoder method should just need to combine
762   // the MI operands for the register and the offset into a single
763   // representation for the complex operand in the .td file. This isn't just
764   // style, unfortunately. As-is, we can't represent the distinct encoding
765   // for #-0.
766 
767   // {8}    = (U)nsigned (add == '1', sub == '0')
768   // {7-0}  = imm8
769   int32_t Imm8 = MI.getOperand(OpIdx).getImm();
770   bool isAdd = Imm8 >= 0;
771 
772   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
773   if (Imm8 < 0)
774     Imm8 = -Imm8;
775 
776   // Scaled by 4.
777   Imm8 /= 4;
778 
779   uint32_t Binary = Imm8 & 0xff;
780   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
781   if (isAdd)
782     Binary |= (1 << 8);
783   return Binary;
784 }
785 
786 /// getT2AddrModeImm8s4OpValue - Return encoding info for
787 /// 'reg +/- imm8<<2' operand.
788 uint32_t ARMMCCodeEmitter::
789 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
790                         SmallVectorImpl<MCFixup> &Fixups) const {
791   // {12-9} = reg
792   // {8}    = (U)nsigned (add == '1', sub == '0')
793   // {7-0}  = imm8
794   unsigned Reg, Imm8;
795   bool isAdd = true;
796   // If The first operand isn't a register, we have a label reference.
797   const MCOperand &MO = MI.getOperand(OpIdx);
798   if (!MO.isReg()) {
799     Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
800     Imm8 = 0;
801     isAdd = false ; // 'U' bit is set as part of the fixup.
802 
803     assert(MO.isExpr() && "Unexpected machine operand type!");
804     const MCExpr *Expr = MO.getExpr();
805     MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
806     Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
807 
808     ++MCNumCPRelocations;
809   } else
810     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
811 
812   // FIXME: The immediate operand should have already been encoded like this
813   // before ever getting here. The encoder method should just need to combine
814   // the MI operands for the register and the offset into a single
815   // representation for the complex operand in the .td file. This isn't just
816   // style, unfortunately. As-is, we can't represent the distinct encoding
817   // for #-0.
818   uint32_t Binary = (Imm8 >> 2) & 0xff;
819   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
820   if (isAdd)
821     Binary |= (1 << 8);
822   Binary |= (Reg << 9);
823   return Binary;
824 }
825 
826 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
827 /// 'reg + imm8<<2' operand.
828 uint32_t ARMMCCodeEmitter::
829 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
830                         SmallVectorImpl<MCFixup> &Fixups) const {
831   // {11-8} = reg
832   // {7-0}  = imm8
833   const MCOperand &MO = MI.getOperand(OpIdx);
834   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
835   unsigned Reg = getARMRegisterNumbering(MO.getReg());
836   unsigned Imm8 = MO1.getImm();
837   return (Reg << 8) | Imm8;
838 }
839 
840 // FIXME: This routine assumes that a binary
841 // expression will always result in a PCRel expression
842 // In reality, its only true if one or more subexpressions
843 // is itself a PCRel (i.e. "." in asm or some other pcrel construct)
844 // but this is good enough for now.
845 static bool EvaluateAsPCRel(const MCExpr *Expr) {
846   switch (Expr->getKind()) {
847   default: llvm_unreachable("Unexpected expression type");
848   case MCExpr::SymbolRef: return false;
849   case MCExpr::Binary: return true;
850   }
851 }
852 
853 uint32_t
854 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
855                                       SmallVectorImpl<MCFixup> &Fixups) const {
856   // {20-16} = imm{15-12}
857   // {11-0}  = imm{11-0}
858   const MCOperand &MO = MI.getOperand(OpIdx);
859   if (MO.isImm())
860     // Hi / lo 16 bits already extracted during earlier passes.
861     return static_cast<unsigned>(MO.getImm());
862 
863   // Handle :upper16: and :lower16: assembly prefixes.
864   const MCExpr *E = MO.getExpr();
865   MCFixupKind Kind;
866   if (E->getKind() == MCExpr::Target) {
867     const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
868     E = ARM16Expr->getSubExpr();
869 
870     switch (ARM16Expr->getKind()) {
871     default: llvm_unreachable("Unsupported ARMFixup");
872     case ARMMCExpr::VK_ARM_HI16:
873       if (!isTargetDarwin() && EvaluateAsPCRel(E))
874         Kind = MCFixupKind(isThumb2()
875                            ? ARM::fixup_t2_movt_hi16_pcrel
876                            : ARM::fixup_arm_movt_hi16_pcrel);
877       else
878         Kind = MCFixupKind(isThumb2()
879                            ? ARM::fixup_t2_movt_hi16
880                            : ARM::fixup_arm_movt_hi16);
881       break;
882     case ARMMCExpr::VK_ARM_LO16:
883       if (!isTargetDarwin() && EvaluateAsPCRel(E))
884         Kind = MCFixupKind(isThumb2()
885                            ? ARM::fixup_t2_movw_lo16_pcrel
886                            : ARM::fixup_arm_movw_lo16_pcrel);
887       else
888         Kind = MCFixupKind(isThumb2()
889                            ? ARM::fixup_t2_movw_lo16
890                            : ARM::fixup_arm_movw_lo16);
891       break;
892     }
893     Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
894     return 0;
895   }
896   // If the expression doesn't have :upper16: or :lower16: on it,
897   // it's just a plain immediate expression, and those evaluate to
898   // the lower 16 bits of the expression regardless of whether
899   // we have a movt or a movw.
900   if (!isTargetDarwin() && EvaluateAsPCRel(E))
901     Kind = MCFixupKind(isThumb2()
902                        ? ARM::fixup_t2_movw_lo16_pcrel
903                        : ARM::fixup_arm_movw_lo16_pcrel);
904   else
905     Kind = MCFixupKind(isThumb2()
906                        ? ARM::fixup_t2_movw_lo16
907                        : ARM::fixup_arm_movw_lo16);
908   Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
909   return 0;
910 }
911 
912 uint32_t ARMMCCodeEmitter::
913 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
914                     SmallVectorImpl<MCFixup> &Fixups) const {
915   const MCOperand &MO = MI.getOperand(OpIdx);
916   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
917   const MCOperand &MO2 = MI.getOperand(OpIdx+2);
918   unsigned Rn = getARMRegisterNumbering(MO.getReg());
919   unsigned Rm = getARMRegisterNumbering(MO1.getReg());
920   unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
921   bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
922   ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
923   unsigned SBits = getShiftOp(ShOp);
924 
925   // {16-13} = Rn
926   // {12}    = isAdd
927   // {11-0}  = shifter
928   //  {3-0}  = Rm
929   //  {4}    = 0
930   //  {6-5}  = type
931   //  {11-7} = imm
932   uint32_t Binary = Rm;
933   Binary |= Rn << 13;
934   Binary |= SBits << 5;
935   Binary |= ShImm << 7;
936   if (isAdd)
937     Binary |= 1 << 12;
938   return Binary;
939 }
940 
941 uint32_t ARMMCCodeEmitter::
942 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
943                     SmallVectorImpl<MCFixup> &Fixups) const {
944   // {17-14}  Rn
945   // {13}     1 == imm12, 0 == Rm
946   // {12}     isAdd
947   // {11-0}   imm12/Rm
948   const MCOperand &MO = MI.getOperand(OpIdx);
949   unsigned Rn = getARMRegisterNumbering(MO.getReg());
950   uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
951   Binary |= Rn << 14;
952   return Binary;
953 }
954 
955 uint32_t ARMMCCodeEmitter::
956 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
957                           SmallVectorImpl<MCFixup> &Fixups) const {
958   // {13}     1 == imm12, 0 == Rm
959   // {12}     isAdd
960   // {11-0}   imm12/Rm
961   const MCOperand &MO = MI.getOperand(OpIdx);
962   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
963   unsigned Imm = MO1.getImm();
964   bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
965   bool isReg = MO.getReg() != 0;
966   uint32_t Binary = ARM_AM::getAM2Offset(Imm);
967   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
968   if (isReg) {
969     ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
970     Binary <<= 7;                    // Shift amount is bits [11:7]
971     Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
972     Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
973   }
974   return Binary | (isAdd << 12) | (isReg << 13);
975 }
976 
977 uint32_t ARMMCCodeEmitter::
978 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
979                      SmallVectorImpl<MCFixup> &Fixups) const {
980   // {4}      isAdd
981   // {3-0}    Rm
982   const MCOperand &MO = MI.getOperand(OpIdx);
983   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
984   bool isAdd = MO1.getImm() != 0;
985   return getARMRegisterNumbering(MO.getReg()) | (isAdd << 4);
986 }
987 
988 uint32_t ARMMCCodeEmitter::
989 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
990                           SmallVectorImpl<MCFixup> &Fixups) const {
991   // {9}      1 == imm8, 0 == Rm
992   // {8}      isAdd
993   // {7-4}    imm7_4/zero
994   // {3-0}    imm3_0/Rm
995   const MCOperand &MO = MI.getOperand(OpIdx);
996   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
997   unsigned Imm = MO1.getImm();
998   bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
999   bool isImm = MO.getReg() == 0;
1000   uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1001   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1002   if (!isImm)
1003     Imm8 = getARMRegisterNumbering(MO.getReg());
1004   return Imm8 | (isAdd << 8) | (isImm << 9);
1005 }
1006 
1007 uint32_t ARMMCCodeEmitter::
1008 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1009                     SmallVectorImpl<MCFixup> &Fixups) const {
1010   // {13}     1 == imm8, 0 == Rm
1011   // {12-9}   Rn
1012   // {8}      isAdd
1013   // {7-4}    imm7_4/zero
1014   // {3-0}    imm3_0/Rm
1015   const MCOperand &MO = MI.getOperand(OpIdx);
1016   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1017   const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1018 
1019   // If The first operand isn't a register, we have a label reference.
1020   if (!MO.isReg()) {
1021     unsigned Rn = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
1022 
1023     assert(MO.isExpr() && "Unexpected machine operand type!");
1024     const MCExpr *Expr = MO.getExpr();
1025     MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1026     Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1027 
1028     ++MCNumCPRelocations;
1029     return (Rn << 9) | (1 << 13);
1030   }
1031   unsigned Rn = getARMRegisterNumbering(MO.getReg());
1032   unsigned Imm = MO2.getImm();
1033   bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1034   bool isImm = MO1.getReg() == 0;
1035   uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1036   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1037   if (!isImm)
1038     Imm8 = getARMRegisterNumbering(MO1.getReg());
1039   return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1040 }
1041 
1042 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1043 uint32_t ARMMCCodeEmitter::
1044 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1045                           SmallVectorImpl<MCFixup> &Fixups) const {
1046   // [SP, #imm]
1047   //   {7-0} = imm8
1048   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1049   assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1050          "Unexpected base register!");
1051 
1052   // The immediate is already shifted for the implicit zeroes, so no change
1053   // here.
1054   return MO1.getImm() & 0xff;
1055 }
1056 
1057 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1058 uint32_t ARMMCCodeEmitter::
1059 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1060                      SmallVectorImpl<MCFixup> &Fixups) const {
1061   // [Rn, #imm]
1062   //   {7-3} = imm5
1063   //   {2-0} = Rn
1064   const MCOperand &MO = MI.getOperand(OpIdx);
1065   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1066   unsigned Rn = getARMRegisterNumbering(MO.getReg());
1067   unsigned Imm5 = MO1.getImm();
1068   return ((Imm5 & 0x1f) << 3) | Rn;
1069 }
1070 
1071 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1072 uint32_t ARMMCCodeEmitter::
1073 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1074                      SmallVectorImpl<MCFixup> &Fixups) const {
1075   const MCOperand MO = MI.getOperand(OpIdx);
1076   if (MO.isExpr())
1077     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
1078   return (MO.getImm() >> 2);
1079 }
1080 
1081 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
1082 uint32_t ARMMCCodeEmitter::
1083 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1084                     SmallVectorImpl<MCFixup> &Fixups) const {
1085   // {12-9} = reg
1086   // {8}    = (U)nsigned (add == '1', sub == '0')
1087   // {7-0}  = imm8
1088   unsigned Reg, Imm8;
1089   bool isAdd;
1090   // If The first operand isn't a register, we have a label reference.
1091   const MCOperand &MO = MI.getOperand(OpIdx);
1092   if (!MO.isReg()) {
1093     Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
1094     Imm8 = 0;
1095     isAdd = false; // 'U' bit is handled as part of the fixup.
1096 
1097     assert(MO.isExpr() && "Unexpected machine operand type!");
1098     const MCExpr *Expr = MO.getExpr();
1099     MCFixupKind Kind;
1100     if (isThumb2())
1101       Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1102     else
1103       Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1104     Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1105 
1106     ++MCNumCPRelocations;
1107   } else {
1108     EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
1109     isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1110   }
1111 
1112   uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1113   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1114   if (isAdd)
1115     Binary |= (1 << 8);
1116   Binary |= (Reg << 9);
1117   return Binary;
1118 }
1119 
1120 unsigned ARMMCCodeEmitter::
1121 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1122                 SmallVectorImpl<MCFixup> &Fixups) const {
1123   // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1124   // shifted. The second is Rs, the amount to shift by, and the third specifies
1125   // the type of the shift.
1126   //
1127   // {3-0} = Rm.
1128   // {4}   = 1
1129   // {6-5} = type
1130   // {11-8} = Rs
1131   // {7}    = 0
1132 
1133   const MCOperand &MO  = MI.getOperand(OpIdx);
1134   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1135   const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1136   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1137 
1138   // Encode Rm.
1139   unsigned Binary = getARMRegisterNumbering(MO.getReg());
1140 
1141   // Encode the shift opcode.
1142   unsigned SBits = 0;
1143   unsigned Rs = MO1.getReg();
1144   if (Rs) {
1145     // Set shift operand (bit[7:4]).
1146     // LSL - 0001
1147     // LSR - 0011
1148     // ASR - 0101
1149     // ROR - 0111
1150     switch (SOpc) {
1151     default: llvm_unreachable("Unknown shift opc!");
1152     case ARM_AM::lsl: SBits = 0x1; break;
1153     case ARM_AM::lsr: SBits = 0x3; break;
1154     case ARM_AM::asr: SBits = 0x5; break;
1155     case ARM_AM::ror: SBits = 0x7; break;
1156     }
1157   }
1158 
1159   Binary |= SBits << 4;
1160 
1161   // Encode the shift operation Rs.
1162   // Encode Rs bit[11:8].
1163   assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1164   return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
1165 }
1166 
1167 unsigned ARMMCCodeEmitter::
1168 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1169                 SmallVectorImpl<MCFixup> &Fixups) const {
1170   // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1171   // shifted. The second is the amount to shift by.
1172   //
1173   // {3-0} = Rm.
1174   // {4}   = 0
1175   // {6-5} = type
1176   // {11-7} = imm
1177 
1178   const MCOperand &MO  = MI.getOperand(OpIdx);
1179   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1180   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1181 
1182   // Encode Rm.
1183   unsigned Binary = getARMRegisterNumbering(MO.getReg());
1184 
1185   // Encode the shift opcode.
1186   unsigned SBits = 0;
1187 
1188   // Set shift operand (bit[6:4]).
1189   // LSL - 000
1190   // LSR - 010
1191   // ASR - 100
1192   // ROR - 110
1193   // RRX - 110 and bit[11:8] clear.
1194   switch (SOpc) {
1195   default: llvm_unreachable("Unknown shift opc!");
1196   case ARM_AM::lsl: SBits = 0x0; break;
1197   case ARM_AM::lsr: SBits = 0x2; break;
1198   case ARM_AM::asr: SBits = 0x4; break;
1199   case ARM_AM::ror: SBits = 0x6; break;
1200   case ARM_AM::rrx:
1201     Binary |= 0x60;
1202     return Binary;
1203   }
1204 
1205   // Encode shift_imm bit[11:7].
1206   Binary |= SBits << 4;
1207   unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1208   assert(Offset < 32 && "Offset must be in range 0-31!");
1209   return Binary | (Offset << 7);
1210 }
1211 
1212 
1213 unsigned ARMMCCodeEmitter::
1214 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1215                 SmallVectorImpl<MCFixup> &Fixups) const {
1216   const MCOperand &MO1 = MI.getOperand(OpNum);
1217   const MCOperand &MO2 = MI.getOperand(OpNum+1);
1218   const MCOperand &MO3 = MI.getOperand(OpNum+2);
1219 
1220   // Encoded as [Rn, Rm, imm].
1221   // FIXME: Needs fixup support.
1222   unsigned Value = getARMRegisterNumbering(MO1.getReg());
1223   Value <<= 4;
1224   Value |= getARMRegisterNumbering(MO2.getReg());
1225   Value <<= 2;
1226   Value |= MO3.getImm();
1227 
1228   return Value;
1229 }
1230 
1231 unsigned ARMMCCodeEmitter::
1232 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1233                          SmallVectorImpl<MCFixup> &Fixups) const {
1234   const MCOperand &MO1 = MI.getOperand(OpNum);
1235   const MCOperand &MO2 = MI.getOperand(OpNum+1);
1236 
1237   // FIXME: Needs fixup support.
1238   unsigned Value = getARMRegisterNumbering(MO1.getReg());
1239 
1240   // Even though the immediate is 8 bits long, we need 9 bits in order
1241   // to represent the (inverse of the) sign bit.
1242   Value <<= 9;
1243   int32_t tmp = (int32_t)MO2.getImm();
1244   if (tmp < 0)
1245     tmp = abs(tmp);
1246   else
1247     Value |= 256; // Set the ADD bit
1248   Value |= tmp & 255;
1249   return Value;
1250 }
1251 
1252 unsigned ARMMCCodeEmitter::
1253 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1254                          SmallVectorImpl<MCFixup> &Fixups) const {
1255   const MCOperand &MO1 = MI.getOperand(OpNum);
1256 
1257   // FIXME: Needs fixup support.
1258   unsigned Value = 0;
1259   int32_t tmp = (int32_t)MO1.getImm();
1260   if (tmp < 0)
1261     tmp = abs(tmp);
1262   else
1263     Value |= 256; // Set the ADD bit
1264   Value |= tmp & 255;
1265   return Value;
1266 }
1267 
1268 unsigned ARMMCCodeEmitter::
1269 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1270                          SmallVectorImpl<MCFixup> &Fixups) const {
1271   const MCOperand &MO1 = MI.getOperand(OpNum);
1272 
1273   // FIXME: Needs fixup support.
1274   unsigned Value = 0;
1275   int32_t tmp = (int32_t)MO1.getImm();
1276   if (tmp < 0)
1277     tmp = abs(tmp);
1278   else
1279     Value |= 4096; // Set the ADD bit
1280   Value |= tmp & 4095;
1281   return Value;
1282 }
1283 
1284 unsigned ARMMCCodeEmitter::
1285 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1286                 SmallVectorImpl<MCFixup> &Fixups) const {
1287   // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1288   // shifted. The second is the amount to shift by.
1289   //
1290   // {3-0} = Rm.
1291   // {4}   = 0
1292   // {6-5} = type
1293   // {11-7} = imm
1294 
1295   const MCOperand &MO  = MI.getOperand(OpIdx);
1296   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1297   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1298 
1299   // Encode Rm.
1300   unsigned Binary = getARMRegisterNumbering(MO.getReg());
1301 
1302   // Encode the shift opcode.
1303   unsigned SBits = 0;
1304   // Set shift operand (bit[6:4]).
1305   // LSL - 000
1306   // LSR - 010
1307   // ASR - 100
1308   // ROR - 110
1309   switch (SOpc) {
1310   default: llvm_unreachable("Unknown shift opc!");
1311   case ARM_AM::lsl: SBits = 0x0; break;
1312   case ARM_AM::lsr: SBits = 0x2; break;
1313   case ARM_AM::asr: SBits = 0x4; break;
1314   case ARM_AM::rrx: // FALLTHROUGH
1315   case ARM_AM::ror: SBits = 0x6; break;
1316   }
1317 
1318   Binary |= SBits << 4;
1319   if (SOpc == ARM_AM::rrx)
1320     return Binary;
1321 
1322   // Encode shift_imm bit[11:7].
1323   return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1324 }
1325 
1326 unsigned ARMMCCodeEmitter::
1327 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1328                                SmallVectorImpl<MCFixup> &Fixups) const {
1329   // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1330   // msb of the mask.
1331   const MCOperand &MO = MI.getOperand(Op);
1332   uint32_t v = ~MO.getImm();
1333   uint32_t lsb = CountTrailingZeros_32(v);
1334   uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
1335   assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1336   return lsb | (msb << 5);
1337 }
1338 
1339 unsigned ARMMCCodeEmitter::
1340 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1341                        SmallVectorImpl<MCFixup> &Fixups) const {
1342   // VLDM/VSTM:
1343   //   {12-8} = Vd
1344   //   {7-0}  = Number of registers
1345   //
1346   // LDM/STM:
1347   //   {15-0}  = Bitfield of GPRs.
1348   unsigned Reg = MI.getOperand(Op).getReg();
1349   bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1350   bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1351 
1352   unsigned Binary = 0;
1353 
1354   if (SPRRegs || DPRRegs) {
1355     // VLDM/VSTM
1356     unsigned RegNo = getARMRegisterNumbering(Reg);
1357     unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1358     Binary |= (RegNo & 0x1f) << 8;
1359     if (SPRRegs)
1360       Binary |= NumRegs;
1361     else
1362       Binary |= NumRegs * 2;
1363   } else {
1364     for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1365       unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1366       Binary |= 1 << RegNo;
1367     }
1368   }
1369 
1370   return Binary;
1371 }
1372 
1373 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1374 /// with the alignment operand.
1375 unsigned ARMMCCodeEmitter::
1376 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1377                            SmallVectorImpl<MCFixup> &Fixups) const {
1378   const MCOperand &Reg = MI.getOperand(Op);
1379   const MCOperand &Imm = MI.getOperand(Op + 1);
1380 
1381   unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1382   unsigned Align = 0;
1383 
1384   switch (Imm.getImm()) {
1385   default: break;
1386   case 2:
1387   case 4:
1388   case 8:  Align = 0x01; break;
1389   case 16: Align = 0x02; break;
1390   case 32: Align = 0x03; break;
1391   }
1392 
1393   return RegNo | (Align << 4);
1394 }
1395 
1396 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1397 /// along  with the alignment operand for use in VST1 and VLD1 with size 32.
1398 unsigned ARMMCCodeEmitter::
1399 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1400                                     SmallVectorImpl<MCFixup> &Fixups) const {
1401   const MCOperand &Reg = MI.getOperand(Op);
1402   const MCOperand &Imm = MI.getOperand(Op + 1);
1403 
1404   unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1405   unsigned Align = 0;
1406 
1407   switch (Imm.getImm()) {
1408   default: break;
1409   case 8:
1410   case 16:
1411   case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1412   case 2: Align = 0x00; break;
1413   case 4: Align = 0x03; break;
1414   }
1415 
1416   return RegNo | (Align << 4);
1417 }
1418 
1419 
1420 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1421 /// alignment operand for use in VLD-dup instructions.  This is the same as
1422 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1423 /// different for VLD4-dup.
1424 unsigned ARMMCCodeEmitter::
1425 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1426                               SmallVectorImpl<MCFixup> &Fixups) const {
1427   const MCOperand &Reg = MI.getOperand(Op);
1428   const MCOperand &Imm = MI.getOperand(Op + 1);
1429 
1430   unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1431   unsigned Align = 0;
1432 
1433   switch (Imm.getImm()) {
1434   default: break;
1435   case 2:
1436   case 4:
1437   case 8:  Align = 0x01; break;
1438   case 16: Align = 0x03; break;
1439   }
1440 
1441   return RegNo | (Align << 4);
1442 }
1443 
1444 unsigned ARMMCCodeEmitter::
1445 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1446                           SmallVectorImpl<MCFixup> &Fixups) const {
1447   const MCOperand &MO = MI.getOperand(Op);
1448   if (MO.getReg() == 0) return 0x0D;
1449   return getARMRegisterNumbering(MO.getReg());
1450 }
1451 
1452 unsigned ARMMCCodeEmitter::
1453 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1454                   SmallVectorImpl<MCFixup> &Fixups) const {
1455   return 8 - MI.getOperand(Op).getImm();
1456 }
1457 
1458 unsigned ARMMCCodeEmitter::
1459 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1460                    SmallVectorImpl<MCFixup> &Fixups) const {
1461   return 16 - MI.getOperand(Op).getImm();
1462 }
1463 
1464 unsigned ARMMCCodeEmitter::
1465 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1466                    SmallVectorImpl<MCFixup> &Fixups) const {
1467   return 32 - MI.getOperand(Op).getImm();
1468 }
1469 
1470 unsigned ARMMCCodeEmitter::
1471 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1472                    SmallVectorImpl<MCFixup> &Fixups) const {
1473   return 64 - MI.getOperand(Op).getImm();
1474 }
1475 
1476 void ARMMCCodeEmitter::
1477 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1478                   SmallVectorImpl<MCFixup> &Fixups) const {
1479   // Pseudo instructions don't get encoded.
1480   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1481   uint64_t TSFlags = Desc.TSFlags;
1482   if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1483     return;
1484 
1485   int Size;
1486   if (Desc.getSize() == 2 || Desc.getSize() == 4)
1487     Size = Desc.getSize();
1488   else
1489     llvm_unreachable("Unexpected instruction size!");
1490 
1491   uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1492   // Thumb 32-bit wide instructions need to emit the high order halfword
1493   // first.
1494   if (isThumb() && Size == 4) {
1495     EmitConstant(Binary >> 16, 2, OS);
1496     EmitConstant(Binary & 0xffff, 2, OS);
1497   } else
1498     EmitConstant(Binary, Size, OS);
1499   ++MCNumEmitted;  // Keep track of the # of mi's emitted.
1500 }
1501 
1502 #include "ARMGenMCCodeEmitter.inc"
1503