1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the ARMMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMFixupKinds.h"
16 #include "MCTargetDesc/ARMMCExpr.h"
17 #include "llvm/ADT/APFloat.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCFixup.h"
26 #include "llvm/MC/MCInst.h"
27 #include "llvm/MC/MCInstrDesc.h"
28 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/MC/MCSubtargetInfo.h"
31 #include "llvm/Support/Casting.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include <algorithm>
37 #include <cassert>
38 #include <cstdint>
39 #include <cstdlib>
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "mccodeemitter"
44 
45 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
46 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
47 
48 namespace {
49 
50 class ARMMCCodeEmitter : public MCCodeEmitter {
51   const MCInstrInfo &MCII;
52   MCContext &CTX;
53   bool IsLittleEndian;
54 
55 public:
56   ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle)
57     : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
58   }
59   ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete;
60   ARMMCCodeEmitter &operator=(const ARMMCCodeEmitter &) = delete;
61   ~ARMMCCodeEmitter() override = default;
62 
63   bool isThumb(const MCSubtargetInfo &STI) const {
64     return STI.getFeatureBits()[ARM::ModeThumb];
65   }
66 
67   bool isThumb2(const MCSubtargetInfo &STI) const {
68     return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
69   }
70 
71   bool isTargetMachO(const MCSubtargetInfo &STI) const {
72     const Triple &TT = STI.getTargetTriple();
73     return TT.isOSBinFormatMachO();
74   }
75 
76   unsigned getMachineSoImmOpValue(unsigned SoImm) const;
77 
78   // getBinaryCodeForInstr - TableGen'erated function for getting the
79   // binary encoding for an instruction.
80   uint64_t getBinaryCodeForInstr(const MCInst &MI,
81                                  SmallVectorImpl<MCFixup> &Fixups,
82                                  const MCSubtargetInfo &STI) const;
83 
84   /// getMachineOpValue - Return binary encoding of operand. If the machine
85   /// operand requires relocation, record the relocation and return zero.
86   unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
87                              SmallVectorImpl<MCFixup> &Fixups,
88                              const MCSubtargetInfo &STI) const;
89 
90   /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
91   /// the specified operand. This is used for operands with :lower16: and
92   /// :upper16: prefixes.
93   uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
94                                SmallVectorImpl<MCFixup> &Fixups,
95                                const MCSubtargetInfo &STI) const;
96 
97   bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
98                               unsigned &Reg, unsigned &Imm,
99                               SmallVectorImpl<MCFixup> &Fixups,
100                               const MCSubtargetInfo &STI) const;
101 
102   /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
103   /// BL branch target.
104   uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
105                                    SmallVectorImpl<MCFixup> &Fixups,
106                                    const MCSubtargetInfo &STI) const;
107 
108   /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
109   /// BLX branch target.
110   uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
111                                     SmallVectorImpl<MCFixup> &Fixups,
112                                     const MCSubtargetInfo &STI) const;
113 
114   /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
115   uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
116                                    SmallVectorImpl<MCFixup> &Fixups,
117                                    const MCSubtargetInfo &STI) const;
118 
119   /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
120   uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
121                                     SmallVectorImpl<MCFixup> &Fixups,
122                                     const MCSubtargetInfo &STI) const;
123 
124   /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
125   uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
126                                    SmallVectorImpl<MCFixup> &Fixups,
127                                    const MCSubtargetInfo &STI) const;
128 
129   /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
130   /// branch target.
131   uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
132                                   SmallVectorImpl<MCFixup> &Fixups,
133                                   const MCSubtargetInfo &STI) const;
134 
135   /// getThumbBranchTargetOpValue - Return encoding info for 24-bit
136   /// immediate Thumb2 direct branch target.
137   uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
138                                        SmallVectorImpl<MCFixup> &Fixups,
139                                        const MCSubtargetInfo &STI) const;
140 
141   /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
142   /// branch target.
143   uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
144                                      SmallVectorImpl<MCFixup> &Fixups,
145                                      const MCSubtargetInfo &STI) const;
146   uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
147                                  SmallVectorImpl<MCFixup> &Fixups,
148                                  const MCSubtargetInfo &STI) const;
149   uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
150                                   SmallVectorImpl<MCFixup> &Fixups,
151                                   const MCSubtargetInfo &STI) const;
152 
153   /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
154   /// ADR label target.
155   uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
156                               SmallVectorImpl<MCFixup> &Fixups,
157                               const MCSubtargetInfo &STI) const;
158   uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
159                               SmallVectorImpl<MCFixup> &Fixups,
160                               const MCSubtargetInfo &STI) const;
161   uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
162                               SmallVectorImpl<MCFixup> &Fixups,
163                               const MCSubtargetInfo &STI) const;
164 
165   uint32_t getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
166                             SmallVectorImpl<MCFixup> &Fixups,
167                             const MCSubtargetInfo &STI) const;
168 
169   /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
170   /// operand.
171   uint32_t getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
172                                  SmallVectorImpl<MCFixup> &Fixups,
173                                  const MCSubtargetInfo &STI) const;
174 
175   /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
176   /// operand.
177   uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
178                                    SmallVectorImpl<MCFixup> &Fixups,
179                                    const MCSubtargetInfo &STI) const;
180 
181   /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
182   uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
183                                          SmallVectorImpl<MCFixup> &Fixups,
184                                          const MCSubtargetInfo &STI) const;
185 
186   /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
187   /// operand.
188   uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
189                                    SmallVectorImpl<MCFixup> &Fixups,
190                                    const MCSubtargetInfo &STI) const;
191 
192   /// getT2AddrModeImm7s4OpValue - Return encoding info for 'reg +/- imm7<<2'
193   /// operand.
194   uint32_t getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
195                                       SmallVectorImpl<MCFixup> &Fixups,
196                                       const MCSubtargetInfo &STI) const;
197 
198   /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
199   /// operand.
200   uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
201                                    SmallVectorImpl<MCFixup> &Fixups,
202                                    const MCSubtargetInfo &STI) const;
203 
204   /// getT2ScaledImmOpValue - Return encoding info for '+/- immX<<Y'
205   /// operand.
206   template<unsigned Bits, unsigned Shift>
207   uint32_t getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
208                                  SmallVectorImpl<MCFixup> &Fixups,
209                                  const MCSubtargetInfo &STI) const;
210 
211   /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
212   /// operand as needed by load/store instructions.
213   uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
214                                SmallVectorImpl<MCFixup> &Fixups,
215                                const MCSubtargetInfo &STI) const;
216 
217   /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
218   uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
219                                SmallVectorImpl<MCFixup> &Fixups,
220                                const MCSubtargetInfo &STI) const {
221     ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
222     switch (Mode) {
223     default: llvm_unreachable("Unknown addressing sub-mode!");
224     case ARM_AM::da: return 0;
225     case ARM_AM::ia: return 1;
226     case ARM_AM::db: return 2;
227     case ARM_AM::ib: return 3;
228     }
229   }
230 
231   /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
232   ///
233   unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
234     switch (ShOpc) {
235     case ARM_AM::no_shift:
236     case ARM_AM::lsl: return 0;
237     case ARM_AM::lsr: return 1;
238     case ARM_AM::asr: return 2;
239     case ARM_AM::ror:
240     case ARM_AM::rrx: return 3;
241     }
242     llvm_unreachable("Invalid ShiftOpc!");
243   }
244 
245   /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
246   uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
247                                      SmallVectorImpl<MCFixup> &Fixups,
248                                      const MCSubtargetInfo &STI) const;
249 
250   /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
251   uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
252                                 SmallVectorImpl<MCFixup> &Fixups,
253                                 const MCSubtargetInfo &STI) const;
254 
255   /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
256   uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
257                                      SmallVectorImpl<MCFixup> &Fixups,
258                                      const MCSubtargetInfo &STI) const;
259 
260   /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
261   uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
262                                SmallVectorImpl<MCFixup> &Fixups,
263                                const MCSubtargetInfo &STI) const;
264 
265   /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
266   /// operand.
267   uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
268                                      SmallVectorImpl<MCFixup> &Fixups,
269                                      const MCSubtargetInfo &STI) const;
270 
271   /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
272   uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
273                                 SmallVectorImpl<MCFixup> &Fixups,
274                                 const MCSubtargetInfo &STI) const;
275 
276   /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
277   uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
278                                 SmallVectorImpl<MCFixup> &Fixups,
279                                 const MCSubtargetInfo &STI) const;
280 
281   /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
282   uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
283                                SmallVectorImpl<MCFixup> &Fixups,
284                                const MCSubtargetInfo &STI) const;
285 
286   /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
287   uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
288                                SmallVectorImpl<MCFixup> &Fixups,
289                                const MCSubtargetInfo &STI) const;
290 
291   /// getCCOutOpValue - Return encoding of the 's' bit.
292   unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
293                            SmallVectorImpl<MCFixup> &Fixups,
294                            const MCSubtargetInfo &STI) const {
295     // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
296     // '1' respectively.
297     return MI.getOperand(Op).getReg() == ARM::CPSR;
298   }
299 
300   unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
301                             SmallVectorImpl<MCFixup> &Fixups,
302                             const MCSubtargetInfo &ST) const {
303     const MCOperand &MO = MI.getOperand(Op);
304 
305     // Support for fixups (MCFixup)
306     if (MO.isExpr()) {
307       const MCExpr *Expr = MO.getExpr();
308       // Fixups resolve to plain values that need to be encoded.
309       MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_mod_imm);
310       Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
311       return 0;
312     }
313 
314     // Immediate is already in its encoded format
315     return MO.getImm();
316   }
317 
318   /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
319   unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
320                            SmallVectorImpl<MCFixup> &Fixups,
321                            const MCSubtargetInfo &STI) const {
322     const MCOperand &MO = MI.getOperand(Op);
323 
324     // Support for fixups (MCFixup)
325     if (MO.isExpr()) {
326       const MCExpr *Expr = MO.getExpr();
327       // Fixups resolve to plain values that need to be encoded.
328       MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_so_imm);
329       Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
330       return 0;
331     }
332     unsigned SoImm = MO.getImm();
333     unsigned Encoded =  ARM_AM::getT2SOImmVal(SoImm);
334     assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
335     return Encoded;
336   }
337 
338   unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
339     SmallVectorImpl<MCFixup> &Fixups,
340     const MCSubtargetInfo &STI) const;
341   unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
342     SmallVectorImpl<MCFixup> &Fixups,
343     const MCSubtargetInfo &STI) const;
344   unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
345     SmallVectorImpl<MCFixup> &Fixups,
346     const MCSubtargetInfo &STI) const;
347 
348   /// getSORegOpValue - Return an encoded so_reg shifted register value.
349   unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
350                            SmallVectorImpl<MCFixup> &Fixups,
351                            const MCSubtargetInfo &STI) const;
352   unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
353                            SmallVectorImpl<MCFixup> &Fixups,
354                            const MCSubtargetInfo &STI) const;
355   unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
356                              SmallVectorImpl<MCFixup> &Fixups,
357                              const MCSubtargetInfo &STI) const;
358 
359   unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
360                                    SmallVectorImpl<MCFixup> &Fixups,
361                                    const MCSubtargetInfo &STI) const {
362     return 64 - MI.getOperand(Op).getImm();
363   }
364 
365   unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
366                                       SmallVectorImpl<MCFixup> &Fixups,
367                                       const MCSubtargetInfo &STI) const;
368 
369   unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
370                                   SmallVectorImpl<MCFixup> &Fixups,
371                                   const MCSubtargetInfo &STI) const;
372   unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
373                                       SmallVectorImpl<MCFixup> &Fixups,
374                                       const MCSubtargetInfo &STI) const;
375   unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
376                                         SmallVectorImpl<MCFixup> &Fixups,
377                                         const MCSubtargetInfo &STI) const;
378   unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
379                                         SmallVectorImpl<MCFixup> &Fixups,
380                                         const MCSubtargetInfo &STI) const;
381   unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
382                                      SmallVectorImpl<MCFixup> &Fixups,
383                                      const MCSubtargetInfo &STI) const;
384 
385   unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
386                              SmallVectorImpl<MCFixup> &Fixups,
387                              const MCSubtargetInfo &STI) const;
388   unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
389                               SmallVectorImpl<MCFixup> &Fixups,
390                               const MCSubtargetInfo &STI) const;
391   unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
392                               SmallVectorImpl<MCFixup> &Fixups,
393                               const MCSubtargetInfo &STI) const;
394   unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
395                               SmallVectorImpl<MCFixup> &Fixups,
396                               const MCSubtargetInfo &STI) const;
397 
398   unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
399                                  SmallVectorImpl<MCFixup> &Fixups,
400                                  const MCSubtargetInfo &STI) const;
401   template <uint8_t shift, bool invert>
402   unsigned getExpandedImmOpValue(const MCInst &MI, unsigned Op,
403                                  SmallVectorImpl<MCFixup> &Fixups,
404                                  const MCSubtargetInfo &STI) const {
405     static_assert(shift <= 32, "Shift count must be less than or equal to 32.");
406     const MCOperand MO = MI.getOperand(Op);
407     return (invert ? (MO.getImm() ^ 0xff) : MO.getImm()) >> shift;
408   }
409 
410   unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
411                                       unsigned EncodedValue,
412                                       const MCSubtargetInfo &STI) const;
413   unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
414                                           unsigned EncodedValue,
415                                           const MCSubtargetInfo &STI) const;
416   unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
417                                     unsigned EncodedValue,
418                                     const MCSubtargetInfo &STI) const;
419   unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
420                                    unsigned EncodedValue,
421                                    const MCSubtargetInfo &STI) const;
422 
423   unsigned VFPThumb2PostEncoder(const MCInst &MI,
424                                 unsigned EncodedValue,
425                                 const MCSubtargetInfo &STI) const;
426 
427   void EmitByte(unsigned char C, raw_ostream &OS) const {
428     OS << (char)C;
429   }
430 
431   void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
432     // Output the constant in little endian byte order.
433     for (unsigned i = 0; i != Size; ++i) {
434       unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
435       EmitByte((Val >> Shift) & 0xff, OS);
436     }
437   }
438 
439   void encodeInstruction(const MCInst &MI, raw_ostream &OS,
440                          SmallVectorImpl<MCFixup> &Fixups,
441                          const MCSubtargetInfo &STI) const override;
442 
443   template <bool isNeg, ARM::Fixups fixup>
444   uint32_t getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
445                               SmallVectorImpl<MCFixup> &Fixups,
446                               const MCSubtargetInfo &STI) const;
447 
448   uint32_t getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
449                                    SmallVectorImpl<MCFixup> &Fixups,
450                                    const MCSubtargetInfo &STI) const;
451 
452   uint32_t getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
453                              SmallVectorImpl<MCFixup> &Fixups,
454                              const MCSubtargetInfo &STI) const;
455   uint32_t getRestrictedCondCodeOpValue(const MCInst &MI, unsigned OpIdx,
456                                         SmallVectorImpl<MCFixup> &Fixups,
457                                         const MCSubtargetInfo &STI) const;
458 };
459 
460 } // end anonymous namespace
461 
462 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
463 /// instructions, and rewrite them to their Thumb2 form if we are currently in
464 /// Thumb2 mode.
465 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
466                                                  unsigned EncodedValue,
467                                                  const MCSubtargetInfo &STI) const {
468   if (isThumb2(STI)) {
469     // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
470     // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
471     // set to 1111.
472     unsigned Bit24 = EncodedValue & 0x01000000;
473     unsigned Bit28 = Bit24 << 4;
474     EncodedValue &= 0xEFFFFFFF;
475     EncodedValue |= Bit28;
476     EncodedValue |= 0x0F000000;
477   }
478 
479   return EncodedValue;
480 }
481 
482 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
483 /// instructions, and rewrite them to their Thumb2 form if we are currently in
484 /// Thumb2 mode.
485 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
486                                                  unsigned EncodedValue,
487                                                  const MCSubtargetInfo &STI) const {
488   if (isThumb2(STI)) {
489     EncodedValue &= 0xF0FFFFFF;
490     EncodedValue |= 0x09000000;
491   }
492 
493   return EncodedValue;
494 }
495 
496 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
497 /// instructions, and rewrite them to their Thumb2 form if we are currently in
498 /// Thumb2 mode.
499 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
500                                                  unsigned EncodedValue,
501                                                  const MCSubtargetInfo &STI) const {
502   if (isThumb2(STI)) {
503     EncodedValue &= 0x00FFFFFF;
504     EncodedValue |= 0xEE000000;
505   }
506 
507   return EncodedValue;
508 }
509 
510 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
511 /// if we are in Thumb2.
512 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
513                                                  unsigned EncodedValue,
514                                                  const MCSubtargetInfo &STI) const {
515   if (isThumb2(STI)) {
516     EncodedValue |= 0xC000000; // Set bits 27-26
517   }
518 
519   return EncodedValue;
520 }
521 
522 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
523 /// them to their Thumb2 form if we are currently in Thumb2 mode.
524 unsigned ARMMCCodeEmitter::
525 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
526                      const MCSubtargetInfo &STI) const {
527   if (isThumb2(STI)) {
528     EncodedValue &= 0x0FFFFFFF;
529     EncodedValue |= 0xE0000000;
530   }
531   return EncodedValue;
532 }
533 
534 /// getMachineOpValue - Return binary encoding of operand. If the machine
535 /// operand requires relocation, record the relocation and return zero.
536 unsigned ARMMCCodeEmitter::
537 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
538                   SmallVectorImpl<MCFixup> &Fixups,
539                   const MCSubtargetInfo &STI) const {
540   if (MO.isReg()) {
541     unsigned Reg = MO.getReg();
542     unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
543 
544     // In NEON, Q registers are encoded as 2x their register number,
545     // because they're using the same indices as the D registers they
546     // overlap. In MVE, there are no 64-bit vector instructions, so
547     // the encodings all refer to Q-registers by their literal
548     // register number.
549 
550     if (STI.getFeatureBits()[ARM::HasMVEIntegerOps])
551       return RegNo;
552 
553     switch (Reg) {
554     default:
555       return RegNo;
556     case ARM::Q0:  case ARM::Q1:  case ARM::Q2:  case ARM::Q3:
557     case ARM::Q4:  case ARM::Q5:  case ARM::Q6:  case ARM::Q7:
558     case ARM::Q8:  case ARM::Q9:  case ARM::Q10: case ARM::Q11:
559     case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
560       return 2 * RegNo;
561     }
562   } else if (MO.isImm()) {
563     return static_cast<unsigned>(MO.getImm());
564   } else if (MO.isFPImm()) {
565     return static_cast<unsigned>(APFloat(MO.getFPImm())
566                      .bitcastToAPInt().getHiBits(32).getLimitedValue());
567   }
568 
569   llvm_unreachable("Unable to encode MCOperand!");
570 }
571 
572 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
573 bool ARMMCCodeEmitter::
574 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
575                        unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
576                        const MCSubtargetInfo &STI) const {
577   const MCOperand &MO  = MI.getOperand(OpIdx);
578   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
579 
580   Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
581 
582   int32_t SImm = MO1.getImm();
583   bool isAdd = true;
584 
585   // Special value for #-0
586   if (SImm == INT32_MIN) {
587     SImm = 0;
588     isAdd = false;
589   }
590 
591   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
592   if (SImm < 0) {
593     SImm = -SImm;
594     isAdd = false;
595   }
596 
597   Imm = SImm;
598   return isAdd;
599 }
600 
601 /// getBranchTargetOpValue - Helper function to get the branch target operand,
602 /// which is either an immediate or requires a fixup.
603 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
604                                        unsigned FixupKind,
605                                        SmallVectorImpl<MCFixup> &Fixups,
606                                        const MCSubtargetInfo &STI) {
607   const MCOperand &MO = MI.getOperand(OpIdx);
608 
609   // If the destination is an immediate, we have nothing to do.
610   if (MO.isImm()) return MO.getImm();
611   assert(MO.isExpr() && "Unexpected branch target type!");
612   const MCExpr *Expr = MO.getExpr();
613   MCFixupKind Kind = MCFixupKind(FixupKind);
614   Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
615 
616   // All of the information is in the fixup.
617   return 0;
618 }
619 
620 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
621 // determined by negating them and XOR'ing them with bit 23.
622 static int32_t encodeThumbBLOffset(int32_t offset) {
623   offset >>= 1;
624   uint32_t S  = (offset & 0x800000) >> 23;
625   uint32_t J1 = (offset & 0x400000) >> 22;
626   uint32_t J2 = (offset & 0x200000) >> 21;
627   J1 = (~J1 & 0x1);
628   J2 = (~J2 & 0x1);
629   J1 ^= S;
630   J2 ^= S;
631 
632   offset &= ~0x600000;
633   offset |= J1 << 22;
634   offset |= J2 << 21;
635 
636   return offset;
637 }
638 
639 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
640 uint32_t ARMMCCodeEmitter::
641 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
642                         SmallVectorImpl<MCFixup> &Fixups,
643                         const MCSubtargetInfo &STI) const {
644   const MCOperand MO = MI.getOperand(OpIdx);
645   if (MO.isExpr())
646     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
647                                     Fixups, STI);
648   return encodeThumbBLOffset(MO.getImm());
649 }
650 
651 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
652 /// BLX branch target.
653 uint32_t ARMMCCodeEmitter::
654 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
655                          SmallVectorImpl<MCFixup> &Fixups,
656                          const MCSubtargetInfo &STI) const {
657   const MCOperand MO = MI.getOperand(OpIdx);
658   if (MO.isExpr())
659     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
660                                     Fixups, STI);
661   return encodeThumbBLOffset(MO.getImm());
662 }
663 
664 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
665 uint32_t ARMMCCodeEmitter::
666 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
667                         SmallVectorImpl<MCFixup> &Fixups,
668                         const MCSubtargetInfo &STI) const {
669   const MCOperand MO = MI.getOperand(OpIdx);
670   if (MO.isExpr())
671     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
672                                     Fixups, STI);
673   return (MO.getImm() >> 1);
674 }
675 
676 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
677 uint32_t ARMMCCodeEmitter::
678 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
679                          SmallVectorImpl<MCFixup> &Fixups,
680                          const MCSubtargetInfo &STI) const {
681   const MCOperand MO = MI.getOperand(OpIdx);
682   if (MO.isExpr())
683     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
684                                     Fixups, STI);
685   return (MO.getImm() >> 1);
686 }
687 
688 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
689 uint32_t ARMMCCodeEmitter::
690 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
691                         SmallVectorImpl<MCFixup> &Fixups,
692                         const MCSubtargetInfo &STI) const {
693   const MCOperand MO = MI.getOperand(OpIdx);
694   if (MO.isExpr())
695     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI);
696   return (MO.getImm() >> 1);
697 }
698 
699 /// Return true if this branch has a non-always predication
700 static bool HasConditionalBranch(const MCInst &MI) {
701   int NumOp = MI.getNumOperands();
702   if (NumOp >= 2) {
703     for (int i = 0; i < NumOp-1; ++i) {
704       const MCOperand &MCOp1 = MI.getOperand(i);
705       const MCOperand &MCOp2 = MI.getOperand(i + 1);
706       if (MCOp1.isImm() && MCOp2.isReg() &&
707           (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
708         if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
709           return true;
710       }
711     }
712   }
713   return false;
714 }
715 
716 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
717 /// target.
718 uint32_t ARMMCCodeEmitter::
719 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
720                        SmallVectorImpl<MCFixup> &Fixups,
721                        const MCSubtargetInfo &STI) const {
722   // FIXME: This really, really shouldn't use TargetMachine. We don't want
723   // coupling between MC and TM anywhere we can help it.
724   if (isThumb2(STI))
725     return
726       ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI);
727   return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
728 }
729 
730 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
731 /// target.
732 uint32_t ARMMCCodeEmitter::
733 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
734                           SmallVectorImpl<MCFixup> &Fixups,
735                           const MCSubtargetInfo &STI) const {
736   const MCOperand MO = MI.getOperand(OpIdx);
737   if (MO.isExpr()) {
738     if (HasConditionalBranch(MI))
739       return ::getBranchTargetOpValue(MI, OpIdx,
740                                       ARM::fixup_arm_condbranch, Fixups, STI);
741     return ::getBranchTargetOpValue(MI, OpIdx,
742                                     ARM::fixup_arm_uncondbranch, Fixups, STI);
743   }
744 
745   return MO.getImm() >> 2;
746 }
747 
748 uint32_t ARMMCCodeEmitter::
749 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
750                           SmallVectorImpl<MCFixup> &Fixups,
751                           const MCSubtargetInfo &STI) const {
752   const MCOperand MO = MI.getOperand(OpIdx);
753   if (MO.isExpr()) {
754     if (HasConditionalBranch(MI))
755       return ::getBranchTargetOpValue(MI, OpIdx,
756                                       ARM::fixup_arm_condbl, Fixups, STI);
757     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI);
758   }
759 
760   return MO.getImm() >> 2;
761 }
762 
763 uint32_t ARMMCCodeEmitter::
764 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
765                           SmallVectorImpl<MCFixup> &Fixups,
766                           const MCSubtargetInfo &STI) const {
767   const MCOperand MO = MI.getOperand(OpIdx);
768   if (MO.isExpr())
769     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI);
770 
771   return MO.getImm() >> 1;
772 }
773 
774 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
775 /// immediate branch target.
776 uint32_t ARMMCCodeEmitter::getThumbBranchTargetOpValue(
777     const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
778     const MCSubtargetInfo &STI) const {
779   unsigned Val = 0;
780   const MCOperand MO = MI.getOperand(OpIdx);
781 
782   if(MO.isExpr())
783     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI);
784   else
785     Val = MO.getImm() >> 1;
786 
787   bool I  = (Val & 0x800000);
788   bool J1 = (Val & 0x400000);
789   bool J2 = (Val & 0x200000);
790   if (I ^ J1)
791     Val &= ~0x400000;
792   else
793     Val |= 0x400000;
794 
795   if (I ^ J2)
796     Val &= ~0x200000;
797   else
798     Val |= 0x200000;
799 
800   return Val;
801 }
802 
803 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
804 /// ADR label target.
805 uint32_t ARMMCCodeEmitter::
806 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
807                    SmallVectorImpl<MCFixup> &Fixups,
808                    const MCSubtargetInfo &STI) const {
809   const MCOperand MO = MI.getOperand(OpIdx);
810   if (MO.isExpr())
811     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
812                                     Fixups, STI);
813   int64_t offset = MO.getImm();
814   uint32_t Val = 0x2000;
815 
816   int SoImmVal;
817   if (offset == INT32_MIN) {
818     Val = 0x1000;
819     SoImmVal = 0;
820   } else if (offset < 0) {
821     Val = 0x1000;
822     offset *= -1;
823     SoImmVal = ARM_AM::getSOImmVal(offset);
824     if(SoImmVal == -1) {
825       Val = 0x2000;
826       offset *= -1;
827       SoImmVal = ARM_AM::getSOImmVal(offset);
828     }
829   } else {
830     SoImmVal = ARM_AM::getSOImmVal(offset);
831     if(SoImmVal == -1) {
832       Val = 0x1000;
833       offset *= -1;
834       SoImmVal = ARM_AM::getSOImmVal(offset);
835     }
836   }
837 
838   assert(SoImmVal != -1 && "Not a valid so_imm value!");
839 
840   Val |= SoImmVal;
841   return Val;
842 }
843 
844 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
845 /// target.
846 uint32_t ARMMCCodeEmitter::
847 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
848                    SmallVectorImpl<MCFixup> &Fixups,
849                    const MCSubtargetInfo &STI) const {
850   const MCOperand MO = MI.getOperand(OpIdx);
851   if (MO.isExpr())
852     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
853                                     Fixups, STI);
854   int32_t Val = MO.getImm();
855   if (Val == INT32_MIN)
856     Val = 0x1000;
857   else if (Val < 0) {
858     Val *= -1;
859     Val |= 0x1000;
860   }
861   return Val;
862 }
863 
864 /// getITMaskOpValue - Return the architectural encoding of an IT
865 /// predication mask, given the MCOperand format.
866 uint32_t ARMMCCodeEmitter::
867 getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
868                  SmallVectorImpl<MCFixup> &Fixups,
869                  const MCSubtargetInfo &STI) const {
870   const MCOperand MaskMO = MI.getOperand(OpIdx);
871   assert(MaskMO.isImm() && "Unexpected operand type!");
872 
873   unsigned Mask = MaskMO.getImm();
874 
875   // IT masks are encoded as a sequence of replacement low-order bits
876   // for the condition code. So if the low bit of the starting
877   // condition code is 1, then we have to flip all the bits above the
878   // terminating bit (which is the lowest 1 bit).
879   assert(OpIdx > 0 && "IT mask appears first!");
880   const MCOperand CondMO = MI.getOperand(OpIdx-1);
881   assert(CondMO.isImm() && "Unexpected operand type!");
882   if (CondMO.getImm() & 1) {
883     unsigned LowBit = Mask & -Mask;
884     unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
885     Mask ^= BitsAboveLowBit;
886   }
887 
888   return Mask;
889 }
890 
891 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
892 /// target.
893 uint32_t ARMMCCodeEmitter::
894 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
895                    SmallVectorImpl<MCFixup> &Fixups,
896                    const MCSubtargetInfo &STI) const {
897   const MCOperand MO = MI.getOperand(OpIdx);
898   if (MO.isExpr())
899     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
900                                     Fixups, STI);
901   return MO.getImm();
902 }
903 
904 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
905 /// operand.
906 uint32_t ARMMCCodeEmitter::
907 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
908                               SmallVectorImpl<MCFixup> &,
909                               const MCSubtargetInfo &STI) const {
910   // [Rn, Rm]
911   //   {5-3} = Rm
912   //   {2-0} = Rn
913   const MCOperand &MO1 = MI.getOperand(OpIdx);
914   const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
915   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
916   unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
917   return (Rm << 3) | Rn;
918 }
919 
920 /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
921 /// operand.
922 uint32_t
923 ARMMCCodeEmitter::getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
924                                         SmallVectorImpl<MCFixup> &Fixups,
925                                         const MCSubtargetInfo &STI) const {
926   // {4-0} = szimm5
927   // The value we are trying to encode is an immediate between either the
928   // range of [1-7] or [1-15] depending on whether we are dealing with the
929   // u8/s8 or the u16/s16 variants respectively.
930   // This value is encoded as follows, if ShiftImm is the value within those
931   // ranges then the encoding szimm5 = ShiftImm + size, where size is either 8
932   // or 16.
933 
934   unsigned Size, ShiftImm;
935   switch(MI.getOpcode()) {
936     case ARM::MVE_VSHLL_imms16bh:
937     case ARM::MVE_VSHLL_imms16th:
938     case ARM::MVE_VSHLL_immu16bh:
939     case ARM::MVE_VSHLL_immu16th:
940       Size = 16;
941       break;
942     case ARM::MVE_VSHLL_imms8bh:
943     case ARM::MVE_VSHLL_imms8th:
944     case ARM::MVE_VSHLL_immu8bh:
945     case ARM::MVE_VSHLL_immu8th:
946       Size = 8;
947       break;
948     default:
949       llvm_unreachable("Use of operand not supported by this instruction");
950   }
951   ShiftImm = MI.getOperand(OpIdx).getImm();
952   return Size + ShiftImm;
953 }
954 
955 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
956 uint32_t ARMMCCodeEmitter::
957 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
958                         SmallVectorImpl<MCFixup> &Fixups,
959                         const MCSubtargetInfo &STI) const {
960   // {17-13} = reg
961   // {12}    = (U)nsigned (add == '1', sub == '0')
962   // {11-0}  = imm12
963   unsigned Reg, Imm12;
964   bool isAdd = true;
965   // If The first operand isn't a register, we have a label reference.
966   const MCOperand &MO = MI.getOperand(OpIdx);
967   if (!MO.isReg()) {
968     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
969     Imm12 = 0;
970 
971     if (MO.isExpr()) {
972       const MCExpr *Expr = MO.getExpr();
973       isAdd = false ; // 'U' bit is set as part of the fixup.
974 
975       MCFixupKind Kind;
976       if (isThumb2(STI))
977         Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
978       else
979         Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
980       Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
981 
982       ++MCNumCPRelocations;
983     } else {
984       Reg = ARM::PC;
985       int32_t Offset = MO.getImm();
986       if (Offset == INT32_MIN) {
987         Offset = 0;
988         isAdd = false;
989       } else if (Offset < 0) {
990         Offset *= -1;
991         isAdd = false;
992       }
993       Imm12 = Offset;
994     }
995   } else
996     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
997 
998   uint32_t Binary = Imm12 & 0xfff;
999   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1000   if (isAdd)
1001     Binary |= (1 << 12);
1002   Binary |= (Reg << 13);
1003   return Binary;
1004 }
1005 
1006 template<unsigned Bits, unsigned Shift>
1007 uint32_t ARMMCCodeEmitter::
1008 getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
1009                       SmallVectorImpl<MCFixup> &Fixups,
1010                       const MCSubtargetInfo &STI) const {
1011   // FIXME: The immediate operand should have already been encoded like this
1012   // before ever getting here. The encoder method should just need to combine
1013   // the MI operands for the register and the offset into a single
1014   // representation for the complex operand in the .td file. This isn't just
1015   // style, unfortunately. As-is, we can't represent the distinct encoding
1016   // for #-0.
1017 
1018   // {Bits}    = (U)nsigned (add == '1', sub == '0')
1019   // {(Bits-1)-0}  = immediate
1020   int32_t Imm = MI.getOperand(OpIdx).getImm();
1021   bool isAdd = Imm >= 0;
1022 
1023   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1024   if (Imm < 0)
1025     Imm = -(uint32_t)Imm;
1026 
1027   Imm >>= Shift;
1028 
1029   uint32_t Binary = Imm & ((1U << Bits) - 1);
1030   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1031   if (isAdd)
1032     Binary |= (1U << Bits);
1033   return Binary;
1034 }
1035 /// getT2AddrModeImm8s4OpValue - Return encoding info for
1036 /// 'reg +/- imm8<<2' operand.
1037 uint32_t ARMMCCodeEmitter::
1038 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
1039                         SmallVectorImpl<MCFixup> &Fixups,
1040                         const MCSubtargetInfo &STI) const {
1041   // {12-9} = reg
1042   // {8}    = (U)nsigned (add == '1', sub == '0')
1043   // {7-0}  = imm8
1044   unsigned Reg, Imm8;
1045   bool isAdd = true;
1046   // If The first operand isn't a register, we have a label reference.
1047   const MCOperand &MO = MI.getOperand(OpIdx);
1048   if (!MO.isReg()) {
1049     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1050     Imm8 = 0;
1051     isAdd = false ; // 'U' bit is set as part of the fixup.
1052 
1053     assert(MO.isExpr() && "Unexpected machine operand type!");
1054     const MCExpr *Expr = MO.getExpr();
1055     MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1056     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1057 
1058     ++MCNumCPRelocations;
1059   } else
1060     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1061 
1062   // FIXME: The immediate operand should have already been encoded like this
1063   // before ever getting here. The encoder method should just need to combine
1064   // the MI operands for the register and the offset into a single
1065   // representation for the complex operand in the .td file. This isn't just
1066   // style, unfortunately. As-is, we can't represent the distinct encoding
1067   // for #-0.
1068   uint32_t Binary = (Imm8 >> 2) & 0xff;
1069   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1070   if (isAdd)
1071     Binary |= (1 << 8);
1072   Binary |= (Reg << 9);
1073   return Binary;
1074 }
1075 
1076 /// getT2AddrModeImm7s4OpValue - Return encoding info for
1077 /// 'reg +/- imm7<<2' operand.
1078 uint32_t
1079 ARMMCCodeEmitter::getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
1080                                              SmallVectorImpl<MCFixup> &Fixups,
1081                                              const MCSubtargetInfo &STI) const {
1082   // {11-8} = reg
1083   // {7}    = (A)dd (add == '1', sub == '0')
1084   // {6-0}  = imm7
1085   unsigned Reg, Imm7;
1086   // If The first operand isn't a register, we have a label reference.
1087   bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm7, Fixups, STI);
1088 
1089   // FIXME: The immediate operand should have already been encoded like this
1090   // before ever getting here. The encoder method should just need to combine
1091   // the MI operands for the register and the offset into a single
1092   // representation for the complex operand in the .td file. This isn't just
1093   // style, unfortunately. As-is, we can't represent the distinct encoding
1094   // for #-0.
1095   uint32_t Binary = (Imm7 >> 2) & 0xff;
1096   // Immediate is always encoded as positive. The 'A' bit controls add vs sub.
1097   if (isAdd)
1098     Binary |= (1 << 7);
1099   Binary |= (Reg << 8);
1100   return Binary;
1101 }
1102 
1103 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
1104 /// 'reg + imm8<<2' operand.
1105 uint32_t ARMMCCodeEmitter::
1106 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
1107                         SmallVectorImpl<MCFixup> &Fixups,
1108                         const MCSubtargetInfo &STI) const {
1109   // {11-8} = reg
1110   // {7-0}  = imm8
1111   const MCOperand &MO = MI.getOperand(OpIdx);
1112   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1113   unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1114   unsigned Imm8 = MO1.getImm();
1115   return (Reg << 8) | Imm8;
1116 }
1117 
1118 uint32_t
1119 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
1120                                       SmallVectorImpl<MCFixup> &Fixups,
1121                                       const MCSubtargetInfo &STI) const {
1122   // {20-16} = imm{15-12}
1123   // {11-0}  = imm{11-0}
1124   const MCOperand &MO = MI.getOperand(OpIdx);
1125   if (MO.isImm())
1126     // Hi / lo 16 bits already extracted during earlier passes.
1127     return static_cast<unsigned>(MO.getImm());
1128 
1129   // Handle :upper16: and :lower16: assembly prefixes.
1130   const MCExpr *E = MO.getExpr();
1131   MCFixupKind Kind;
1132   if (E->getKind() == MCExpr::Target) {
1133     const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
1134     E = ARM16Expr->getSubExpr();
1135 
1136     if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) {
1137       const int64_t Value = MCE->getValue();
1138       if (Value > UINT32_MAX)
1139         report_fatal_error("constant value truncated (limited to 32-bit)");
1140 
1141       switch (ARM16Expr->getKind()) {
1142       case ARMMCExpr::VK_ARM_HI16:
1143         return (int32_t(Value) & 0xffff0000) >> 16;
1144       case ARMMCExpr::VK_ARM_LO16:
1145         return (int32_t(Value) & 0x0000ffff);
1146       default: llvm_unreachable("Unsupported ARMFixup");
1147       }
1148     }
1149 
1150     switch (ARM16Expr->getKind()) {
1151     default: llvm_unreachable("Unsupported ARMFixup");
1152     case ARMMCExpr::VK_ARM_HI16:
1153       Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movt_hi16
1154                                       : ARM::fixup_arm_movt_hi16);
1155       break;
1156     case ARMMCExpr::VK_ARM_LO16:
1157       Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movw_lo16
1158                                       : ARM::fixup_arm_movw_lo16);
1159       break;
1160     }
1161 
1162     Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc()));
1163     return 0;
1164   }
1165   // If the expression doesn't have :upper16: or :lower16: on it,
1166   // it's just a plain immediate expression, previously those evaluated to
1167   // the lower 16 bits of the expression regardless of whether
1168   // we have a movt or a movw, but that led to misleadingly results.
1169   // This is disallowed in the AsmParser in validateInstruction()
1170   // so this should never happen.
1171   llvm_unreachable("expression without :upper16: or :lower16:");
1172 }
1173 
1174 uint32_t ARMMCCodeEmitter::
1175 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1176                     SmallVectorImpl<MCFixup> &Fixups,
1177                     const MCSubtargetInfo &STI) const {
1178   const MCOperand &MO = MI.getOperand(OpIdx);
1179   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1180   const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1181   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1182   unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1183   unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
1184   bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
1185   ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
1186   unsigned SBits = getShiftOp(ShOp);
1187 
1188   // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1189   // amount. However, it would be an easy mistake to make so check here.
1190   assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
1191 
1192   // {16-13} = Rn
1193   // {12}    = isAdd
1194   // {11-0}  = shifter
1195   //  {3-0}  = Rm
1196   //  {4}    = 0
1197   //  {6-5}  = type
1198   //  {11-7} = imm
1199   uint32_t Binary = Rm;
1200   Binary |= Rn << 13;
1201   Binary |= SBits << 5;
1202   Binary |= ShImm << 7;
1203   if (isAdd)
1204     Binary |= 1 << 12;
1205   return Binary;
1206 }
1207 
1208 uint32_t ARMMCCodeEmitter::
1209 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1210                           SmallVectorImpl<MCFixup> &Fixups,
1211                           const MCSubtargetInfo &STI) const {
1212   // {13}     1 == imm12, 0 == Rm
1213   // {12}     isAdd
1214   // {11-0}   imm12/Rm
1215   const MCOperand &MO = MI.getOperand(OpIdx);
1216   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1217   unsigned Imm = MO1.getImm();
1218   bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1219   bool isReg = MO.getReg() != 0;
1220   uint32_t Binary = ARM_AM::getAM2Offset(Imm);
1221   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
1222   if (isReg) {
1223     ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
1224     Binary <<= 7;                    // Shift amount is bits [11:7]
1225     Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1226     Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1227   }
1228   return Binary | (isAdd << 12) | (isReg << 13);
1229 }
1230 
1231 uint32_t ARMMCCodeEmitter::
1232 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1233                      SmallVectorImpl<MCFixup> &Fixups,
1234                      const MCSubtargetInfo &STI) const {
1235   // {4}      isAdd
1236   // {3-0}    Rm
1237   const MCOperand &MO = MI.getOperand(OpIdx);
1238   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1239   bool isAdd = MO1.getImm() != 0;
1240   return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
1241 }
1242 
1243 uint32_t ARMMCCodeEmitter::
1244 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1245                           SmallVectorImpl<MCFixup> &Fixups,
1246                           const MCSubtargetInfo &STI) const {
1247   // {9}      1 == imm8, 0 == Rm
1248   // {8}      isAdd
1249   // {7-4}    imm7_4/zero
1250   // {3-0}    imm3_0/Rm
1251   const MCOperand &MO = MI.getOperand(OpIdx);
1252   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1253   unsigned Imm = MO1.getImm();
1254   bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1255   bool isImm = MO.getReg() == 0;
1256   uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1257   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1258   if (!isImm)
1259     Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1260   return Imm8 | (isAdd << 8) | (isImm << 9);
1261 }
1262 
1263 uint32_t ARMMCCodeEmitter::
1264 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1265                     SmallVectorImpl<MCFixup> &Fixups,
1266                     const MCSubtargetInfo &STI) const {
1267   // {13}     1 == imm8, 0 == Rm
1268   // {12-9}   Rn
1269   // {8}      isAdd
1270   // {7-4}    imm7_4/zero
1271   // {3-0}    imm3_0/Rm
1272   const MCOperand &MO = MI.getOperand(OpIdx);
1273   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1274   const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1275 
1276   // If The first operand isn't a register, we have a label reference.
1277   if (!MO.isReg()) {
1278     unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1279 
1280     assert(MO.isExpr() && "Unexpected machine operand type!");
1281     const MCExpr *Expr = MO.getExpr();
1282     MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1283     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1284 
1285     ++MCNumCPRelocations;
1286     return (Rn << 9) | (1 << 13);
1287   }
1288   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1289   unsigned Imm = MO2.getImm();
1290   bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1291   bool isImm = MO1.getReg() == 0;
1292   uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1293   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1294   if (!isImm)
1295     Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1296   return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1297 }
1298 
1299 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1300 uint32_t ARMMCCodeEmitter::
1301 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1302                           SmallVectorImpl<MCFixup> &Fixups,
1303                           const MCSubtargetInfo &STI) const {
1304   // [SP, #imm]
1305   //   {7-0} = imm8
1306   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1307   assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1308          "Unexpected base register!");
1309 
1310   // The immediate is already shifted for the implicit zeroes, so no change
1311   // here.
1312   return MO1.getImm() & 0xff;
1313 }
1314 
1315 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1316 uint32_t ARMMCCodeEmitter::
1317 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1318                      SmallVectorImpl<MCFixup> &Fixups,
1319                      const MCSubtargetInfo &STI) const {
1320   // [Rn, #imm]
1321   //   {7-3} = imm5
1322   //   {2-0} = Rn
1323   const MCOperand &MO = MI.getOperand(OpIdx);
1324   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1325   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1326   unsigned Imm5 = MO1.getImm();
1327   return ((Imm5 & 0x1f) << 3) | Rn;
1328 }
1329 
1330 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1331 uint32_t ARMMCCodeEmitter::
1332 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1333                      SmallVectorImpl<MCFixup> &Fixups,
1334                      const MCSubtargetInfo &STI) const {
1335   const MCOperand MO = MI.getOperand(OpIdx);
1336   if (MO.isExpr())
1337     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI);
1338   return (MO.getImm() >> 2);
1339 }
1340 
1341 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
1342 uint32_t ARMMCCodeEmitter::
1343 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1344                     SmallVectorImpl<MCFixup> &Fixups,
1345                     const MCSubtargetInfo &STI) const {
1346   // {12-9} = reg
1347   // {8}    = (U)nsigned (add == '1', sub == '0')
1348   // {7-0}  = imm8
1349   unsigned Reg, Imm8;
1350   bool isAdd;
1351   // If The first operand isn't a register, we have a label reference.
1352   const MCOperand &MO = MI.getOperand(OpIdx);
1353   if (!MO.isReg()) {
1354     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1355     Imm8 = 0;
1356     isAdd = false; // 'U' bit is handled as part of the fixup.
1357 
1358     assert(MO.isExpr() && "Unexpected machine operand type!");
1359     const MCExpr *Expr = MO.getExpr();
1360     MCFixupKind Kind;
1361     if (isThumb2(STI))
1362       Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1363     else
1364       Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1365     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1366 
1367     ++MCNumCPRelocations;
1368   } else {
1369     EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1370     isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1371   }
1372 
1373   uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1374   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1375   if (isAdd)
1376     Binary |= (1 << 8);
1377   Binary |= (Reg << 9);
1378   return Binary;
1379 }
1380 
1381 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
1382 uint32_t ARMMCCodeEmitter::
1383 getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
1384                     SmallVectorImpl<MCFixup> &Fixups,
1385                     const MCSubtargetInfo &STI) const {
1386   // {12-9} = reg
1387   // {8}    = (U)nsigned (add == '1', sub == '0')
1388   // {7-0}  = imm8
1389   unsigned Reg, Imm8;
1390   bool isAdd;
1391   // If The first operand isn't a register, we have a label reference.
1392   const MCOperand &MO = MI.getOperand(OpIdx);
1393   if (!MO.isReg()) {
1394     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1395     Imm8 = 0;
1396     isAdd = false; // 'U' bit is handled as part of the fixup.
1397 
1398     assert(MO.isExpr() && "Unexpected machine operand type!");
1399     const MCExpr *Expr = MO.getExpr();
1400     MCFixupKind Kind;
1401     if (isThumb2(STI))
1402       Kind = MCFixupKind(ARM::fixup_t2_pcrel_9);
1403     else
1404       Kind = MCFixupKind(ARM::fixup_arm_pcrel_9);
1405     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1406 
1407     ++MCNumCPRelocations;
1408   } else {
1409     EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1410     isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1411   }
1412 
1413   uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1414   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1415   if (isAdd)
1416     Binary |= (1 << 8);
1417   Binary |= (Reg << 9);
1418   return Binary;
1419 }
1420 
1421 unsigned ARMMCCodeEmitter::
1422 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1423                 SmallVectorImpl<MCFixup> &Fixups,
1424                 const MCSubtargetInfo &STI) const {
1425   // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1426   // shifted. The second is Rs, the amount to shift by, and the third specifies
1427   // the type of the shift.
1428   //
1429   // {3-0} = Rm.
1430   // {4}   = 1
1431   // {6-5} = type
1432   // {11-8} = Rs
1433   // {7}    = 0
1434 
1435   const MCOperand &MO  = MI.getOperand(OpIdx);
1436   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1437   const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1438   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1439 
1440   // Encode Rm.
1441   unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1442 
1443   // Encode the shift opcode.
1444   unsigned SBits = 0;
1445   unsigned Rs = MO1.getReg();
1446   if (Rs) {
1447     // Set shift operand (bit[7:4]).
1448     // LSL - 0001
1449     // LSR - 0011
1450     // ASR - 0101
1451     // ROR - 0111
1452     switch (SOpc) {
1453     default: llvm_unreachable("Unknown shift opc!");
1454     case ARM_AM::lsl: SBits = 0x1; break;
1455     case ARM_AM::lsr: SBits = 0x3; break;
1456     case ARM_AM::asr: SBits = 0x5; break;
1457     case ARM_AM::ror: SBits = 0x7; break;
1458     }
1459   }
1460 
1461   Binary |= SBits << 4;
1462 
1463   // Encode the shift operation Rs.
1464   // Encode Rs bit[11:8].
1465   assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1466   return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
1467 }
1468 
1469 unsigned ARMMCCodeEmitter::
1470 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1471                 SmallVectorImpl<MCFixup> &Fixups,
1472                 const MCSubtargetInfo &STI) const {
1473   // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1474   // shifted. The second is the amount to shift by.
1475   //
1476   // {3-0} = Rm.
1477   // {4}   = 0
1478   // {6-5} = type
1479   // {11-7} = imm
1480 
1481   const MCOperand &MO  = MI.getOperand(OpIdx);
1482   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1483   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1484 
1485   // Encode Rm.
1486   unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1487 
1488   // Encode the shift opcode.
1489   unsigned SBits = 0;
1490 
1491   // Set shift operand (bit[6:4]).
1492   // LSL - 000
1493   // LSR - 010
1494   // ASR - 100
1495   // ROR - 110
1496   // RRX - 110 and bit[11:8] clear.
1497   switch (SOpc) {
1498   default: llvm_unreachable("Unknown shift opc!");
1499   case ARM_AM::lsl: SBits = 0x0; break;
1500   case ARM_AM::lsr: SBits = 0x2; break;
1501   case ARM_AM::asr: SBits = 0x4; break;
1502   case ARM_AM::ror: SBits = 0x6; break;
1503   case ARM_AM::rrx:
1504     Binary |= 0x60;
1505     return Binary;
1506   }
1507 
1508   // Encode shift_imm bit[11:7].
1509   Binary |= SBits << 4;
1510   unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1511   assert(Offset < 32 && "Offset must be in range 0-31!");
1512   return Binary | (Offset << 7);
1513 }
1514 
1515 
1516 unsigned ARMMCCodeEmitter::
1517 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1518                 SmallVectorImpl<MCFixup> &Fixups,
1519                 const MCSubtargetInfo &STI) const {
1520   const MCOperand &MO1 = MI.getOperand(OpNum);
1521   const MCOperand &MO2 = MI.getOperand(OpNum+1);
1522   const MCOperand &MO3 = MI.getOperand(OpNum+2);
1523 
1524   // Encoded as [Rn, Rm, imm].
1525   // FIXME: Needs fixup support.
1526   unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1527   Value <<= 4;
1528   Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1529   Value <<= 2;
1530   Value |= MO3.getImm();
1531 
1532   return Value;
1533 }
1534 
1535 unsigned ARMMCCodeEmitter::
1536 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1537                          SmallVectorImpl<MCFixup> &Fixups,
1538                          const MCSubtargetInfo &STI) const {
1539   const MCOperand &MO1 = MI.getOperand(OpNum);
1540   const MCOperand &MO2 = MI.getOperand(OpNum+1);
1541 
1542   // FIXME: Needs fixup support.
1543   unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1544 
1545   // Even though the immediate is 8 bits long, we need 9 bits in order
1546   // to represent the (inverse of the) sign bit.
1547   Value <<= 9;
1548   int32_t tmp = (int32_t)MO2.getImm();
1549   if (tmp < 0)
1550     tmp = abs(tmp);
1551   else
1552     Value |= 256; // Set the ADD bit
1553   Value |= tmp & 255;
1554   return Value;
1555 }
1556 
1557 unsigned ARMMCCodeEmitter::
1558 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1559                          SmallVectorImpl<MCFixup> &Fixups,
1560                          const MCSubtargetInfo &STI) const {
1561   const MCOperand &MO1 = MI.getOperand(OpNum);
1562 
1563   // FIXME: Needs fixup support.
1564   unsigned Value = 0;
1565   int32_t tmp = (int32_t)MO1.getImm();
1566   if (tmp < 0)
1567     tmp = abs(tmp);
1568   else
1569     Value |= 256; // Set the ADD bit
1570   Value |= tmp & 255;
1571   return Value;
1572 }
1573 
1574 unsigned ARMMCCodeEmitter::
1575 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1576                 SmallVectorImpl<MCFixup> &Fixups,
1577                 const MCSubtargetInfo &STI) const {
1578   // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1579   // shifted. The second is the amount to shift by.
1580   //
1581   // {3-0} = Rm.
1582   // {4}   = 0
1583   // {6-5} = type
1584   // {11-7} = imm
1585 
1586   const MCOperand &MO  = MI.getOperand(OpIdx);
1587   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1588   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1589 
1590   // Encode Rm.
1591   unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1592 
1593   // Encode the shift opcode.
1594   unsigned SBits = 0;
1595   // Set shift operand (bit[6:4]).
1596   // LSL - 000
1597   // LSR - 010
1598   // ASR - 100
1599   // ROR - 110
1600   switch (SOpc) {
1601   default: llvm_unreachable("Unknown shift opc!");
1602   case ARM_AM::lsl: SBits = 0x0; break;
1603   case ARM_AM::lsr: SBits = 0x2; break;
1604   case ARM_AM::asr: SBits = 0x4; break;
1605   case ARM_AM::rrx: LLVM_FALLTHROUGH;
1606   case ARM_AM::ror: SBits = 0x6; break;
1607   }
1608 
1609   Binary |= SBits << 4;
1610   if (SOpc == ARM_AM::rrx)
1611     return Binary;
1612 
1613   // Encode shift_imm bit[11:7].
1614   return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1615 }
1616 
1617 unsigned ARMMCCodeEmitter::
1618 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1619                                SmallVectorImpl<MCFixup> &Fixups,
1620                                const MCSubtargetInfo &STI) const {
1621   // 10 bits. lower 5 bits are the lsb of the mask, high five bits are the
1622   // msb of the mask.
1623   const MCOperand &MO = MI.getOperand(Op);
1624   uint32_t v = ~MO.getImm();
1625   uint32_t lsb = countTrailingZeros(v);
1626   uint32_t msb = (32 - countLeadingZeros (v)) - 1;
1627   assert(v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1628   return lsb | (msb << 5);
1629 }
1630 
1631 unsigned ARMMCCodeEmitter::
1632 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1633                        SmallVectorImpl<MCFixup> &Fixups,
1634                        const MCSubtargetInfo &STI) const {
1635   // VLDM/VSTM/VSCCLRM:
1636   //   {12-8} = Vd
1637   //   {7-0}  = Number of registers
1638   //
1639   // LDM/STM:
1640   //   {15-0}  = Bitfield of GPRs.
1641   unsigned Reg = MI.getOperand(Op).getReg();
1642   bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1643   bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1644   bool CLRMRegs = MI.getOpcode() == ARM::t2CLRM;
1645 
1646   unsigned Binary = 0;
1647 
1648   if (SPRRegs || DPRRegs) {
1649     // VLDM/VSTM/VSCCLRM
1650     unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1651     unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1652     Binary |= (RegNo & 0x1f) << 8;
1653 
1654     // Ignore VPR
1655     if (MI.getOpcode() == ARM::VSCCLRMD || MI.getOpcode() == ARM::VSCCLRMS)
1656       --NumRegs;
1657     if (SPRRegs)
1658       Binary |= NumRegs;
1659     else
1660       Binary |= NumRegs * 2;
1661   } else {
1662     const MCRegisterInfo &MRI = *CTX.getRegisterInfo();
1663     if (!CLRMRegs) {
1664       assert(std::is_sorted(MI.begin() + Op, MI.end(),
1665                             [&](const MCOperand &LHS, const MCOperand &RHS) {
1666                               return MRI.getEncodingValue(LHS.getReg()) <
1667                                      MRI.getEncodingValue(RHS.getReg());
1668                             }));
1669     }
1670 
1671     for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1672       unsigned RegNo;
1673       if (CLRMRegs && MI.getOperand(I).getReg() == ARM::APSR) {
1674         RegNo = 15;
1675       } else {
1676         RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
1677       }
1678       Binary |= 1 << RegNo;
1679     }
1680   }
1681 
1682   return Binary;
1683 }
1684 
1685 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1686 /// with the alignment operand.
1687 unsigned ARMMCCodeEmitter::
1688 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1689                            SmallVectorImpl<MCFixup> &Fixups,
1690                            const MCSubtargetInfo &STI) const {
1691   const MCOperand &Reg = MI.getOperand(Op);
1692   const MCOperand &Imm = MI.getOperand(Op + 1);
1693 
1694   unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1695   unsigned Align = 0;
1696 
1697   switch (Imm.getImm()) {
1698   default: break;
1699   case 2:
1700   case 4:
1701   case 8:  Align = 0x01; break;
1702   case 16: Align = 0x02; break;
1703   case 32: Align = 0x03; break;
1704   }
1705 
1706   return RegNo | (Align << 4);
1707 }
1708 
1709 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1710 /// along  with the alignment operand for use in VST1 and VLD1 with size 32.
1711 unsigned ARMMCCodeEmitter::
1712 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1713                                     SmallVectorImpl<MCFixup> &Fixups,
1714                                     const MCSubtargetInfo &STI) const {
1715   const MCOperand &Reg = MI.getOperand(Op);
1716   const MCOperand &Imm = MI.getOperand(Op + 1);
1717 
1718   unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1719   unsigned Align = 0;
1720 
1721   switch (Imm.getImm()) {
1722   default: break;
1723   case 8:
1724   case 16:
1725   case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1726   case 2: Align = 0x00; break;
1727   case 4: Align = 0x03; break;
1728   }
1729 
1730   return RegNo | (Align << 4);
1731 }
1732 
1733 
1734 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1735 /// alignment operand for use in VLD-dup instructions.  This is the same as
1736 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1737 /// different for VLD4-dup.
1738 unsigned ARMMCCodeEmitter::
1739 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1740                               SmallVectorImpl<MCFixup> &Fixups,
1741                               const MCSubtargetInfo &STI) const {
1742   const MCOperand &Reg = MI.getOperand(Op);
1743   const MCOperand &Imm = MI.getOperand(Op + 1);
1744 
1745   unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1746   unsigned Align = 0;
1747 
1748   switch (Imm.getImm()) {
1749   default: break;
1750   case 2:
1751   case 4:
1752   case 8:  Align = 0x01; break;
1753   case 16: Align = 0x03; break;
1754   }
1755 
1756   return RegNo | (Align << 4);
1757 }
1758 
1759 unsigned ARMMCCodeEmitter::
1760 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1761                           SmallVectorImpl<MCFixup> &Fixups,
1762                           const MCSubtargetInfo &STI) const {
1763   const MCOperand &MO = MI.getOperand(Op);
1764   if (MO.getReg() == 0) return 0x0D;
1765   return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1766 }
1767 
1768 unsigned ARMMCCodeEmitter::
1769 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1770                   SmallVectorImpl<MCFixup> &Fixups,
1771                   const MCSubtargetInfo &STI) const {
1772   return 8 - MI.getOperand(Op).getImm();
1773 }
1774 
1775 unsigned ARMMCCodeEmitter::
1776 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1777                    SmallVectorImpl<MCFixup> &Fixups,
1778                    const MCSubtargetInfo &STI) const {
1779   return 16 - MI.getOperand(Op).getImm();
1780 }
1781 
1782 unsigned ARMMCCodeEmitter::
1783 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1784                    SmallVectorImpl<MCFixup> &Fixups,
1785                    const MCSubtargetInfo &STI) const {
1786   return 32 - MI.getOperand(Op).getImm();
1787 }
1788 
1789 unsigned ARMMCCodeEmitter::
1790 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1791                    SmallVectorImpl<MCFixup> &Fixups,
1792                    const MCSubtargetInfo &STI) const {
1793   return 64 - MI.getOperand(Op).getImm();
1794 }
1795 
1796 void ARMMCCodeEmitter::
1797 encodeInstruction(const MCInst &MI, raw_ostream &OS,
1798                   SmallVectorImpl<MCFixup> &Fixups,
1799                   const MCSubtargetInfo &STI) const {
1800   // Pseudo instructions don't get encoded.
1801   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1802   uint64_t TSFlags = Desc.TSFlags;
1803   if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1804     return;
1805 
1806   int Size;
1807   if (Desc.getSize() == 2 || Desc.getSize() == 4)
1808     Size = Desc.getSize();
1809   else
1810     llvm_unreachable("Unexpected instruction size!");
1811 
1812   uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1813   // Thumb 32-bit wide instructions need to emit the high order halfword
1814   // first.
1815   if (isThumb(STI) && Size == 4) {
1816     EmitConstant(Binary >> 16, 2, OS);
1817     EmitConstant(Binary & 0xffff, 2, OS);
1818   } else
1819     EmitConstant(Binary, Size, OS);
1820   ++MCNumEmitted;  // Keep track of the # of mi's emitted.
1821 }
1822 
1823 template <bool isNeg, ARM::Fixups fixup>
1824 uint32_t
1825 ARMMCCodeEmitter::getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
1826                                      SmallVectorImpl<MCFixup> &Fixups,
1827                                      const MCSubtargetInfo &STI) const {
1828   const MCOperand MO = MI.getOperand(OpIdx);
1829   if (MO.isExpr())
1830     return ::getBranchTargetOpValue(MI, OpIdx, fixup, Fixups, STI);
1831   return isNeg ? -(MO.getImm() >> 1) : (MO.getImm() >> 1);
1832 }
1833 
1834 uint32_t
1835 ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
1836                                           SmallVectorImpl<MCFixup> &Fixups,
1837                                           const MCSubtargetInfo &STI) const {
1838   const MCOperand MO = MI.getOperand(OpIdx);
1839   const MCOperand BranchMO = MI.getOperand(0);
1840 
1841   if (MO.isExpr()) {
1842     assert(BranchMO.isExpr());
1843     const MCExpr *DiffExpr = MCBinaryExpr::createSub(
1844         MO.getExpr(), BranchMO.getExpr(), CTX);
1845     MCFixupKind Kind = MCFixupKind(ARM::fixup_bfcsel_else_target);
1846     Fixups.push_back(llvm::MCFixup::create(0, DiffExpr, Kind, MI.getLoc()));
1847     return 0;
1848   }
1849 
1850   assert(MO.isImm() && BranchMO.isImm());
1851   int Diff = MO.getImm() - BranchMO.getImm();
1852   assert(Diff == 4 || Diff == 2);
1853 
1854   return Diff == 4;
1855 }
1856 
1857 uint32_t ARMMCCodeEmitter::getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
1858                                              SmallVectorImpl<MCFixup> &Fixups,
1859                                              const MCSubtargetInfo &STI)const {
1860   const MCOperand MO = MI.getOperand(OpIdx);
1861   assert(MO.isImm() && "Unexpected operand type!");
1862 
1863   int Value = MO.getImm();
1864   int Imm = 0;
1865 
1866   // VPT Masks are actually encoded as a series of invert/don't invert bits,
1867   // rather than true/false bits.
1868   unsigned PrevBit = 0;
1869   for (int i = 3; i >= 0; --i) {
1870     unsigned Bit = (Value >> i) & 1;
1871 
1872     // Check if we are at the end of the mask.
1873     if ((Value & ~(~0U << i)) == 0) {
1874       Imm |= (1 << i);
1875       break;
1876     }
1877 
1878     // Convert the bit in the mask based on the previous bit.
1879     if (Bit != PrevBit)
1880       Imm |= (1 << i);
1881 
1882     PrevBit = Bit;
1883   }
1884 
1885   return Imm;
1886 }
1887 
1888 uint32_t ARMMCCodeEmitter::getRestrictedCondCodeOpValue(
1889     const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
1890     const MCSubtargetInfo &STI) const {
1891 
1892   const MCOperand MO = MI.getOperand(OpIdx);
1893   assert(MO.isImm() && "Unexpected operand type!");
1894 
1895   switch (MO.getImm()) {
1896   default:
1897     assert(0 && "Unexpected Condition!");
1898     return 0;
1899   case ARMCC::HS:
1900   case ARMCC::EQ:
1901     return 0;
1902   case ARMCC::HI:
1903   case ARMCC::NE:
1904     return 1;
1905   case ARMCC::GE:
1906     return 4;
1907   case ARMCC::LT:
1908     return 5;
1909   case ARMCC::GT:
1910     return 6;
1911   case ARMCC::LE:
1912     return 7;
1913   }
1914 }
1915 
1916 #include "ARMGenMCCodeEmitter.inc"
1917 
1918 MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
1919                                               const MCRegisterInfo &MRI,
1920                                               MCContext &Ctx) {
1921   return new ARMMCCodeEmitter(MCII, Ctx, true);
1922 }
1923 
1924 MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
1925                                               const MCRegisterInfo &MRI,
1926                                               MCContext &Ctx) {
1927   return new ARMMCCodeEmitter(MCII, Ctx, false);
1928 }
1929