1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the ARMMCCodeEmitter class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/ARMAddressingModes.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "MCTargetDesc/ARMFixupKinds.h" 16 #include "MCTargetDesc/ARMMCExpr.h" 17 #include "llvm/ADT/APFloat.h" 18 #include "llvm/ADT/APInt.h" 19 #include "llvm/ADT/SmallVector.h" 20 #include "llvm/ADT/Statistic.h" 21 #include "llvm/ADT/Triple.h" 22 #include "llvm/MC/MCCodeEmitter.h" 23 #include "llvm/MC/MCContext.h" 24 #include "llvm/MC/MCExpr.h" 25 #include "llvm/MC/MCFixup.h" 26 #include "llvm/MC/MCInst.h" 27 #include "llvm/MC/MCInstrDesc.h" 28 #include "llvm/MC/MCInstrInfo.h" 29 #include "llvm/MC/MCRegisterInfo.h" 30 #include "llvm/MC/MCSubtargetInfo.h" 31 #include "llvm/Support/Casting.h" 32 #include "llvm/Support/Compiler.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include "llvm/Support/MathExtras.h" 35 #include "llvm/Support/raw_ostream.h" 36 #include <algorithm> 37 #include <cassert> 38 #include <cstdint> 39 #include <cstdlib> 40 41 using namespace llvm; 42 43 #define DEBUG_TYPE "mccodeemitter" 44 45 STATISTIC(MCNumEmitted, "Number of MC instructions emitted."); 46 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created."); 47 48 namespace { 49 50 class ARMMCCodeEmitter : public MCCodeEmitter { 51 const MCInstrInfo &MCII; 52 MCContext &CTX; 53 bool IsLittleEndian; 54 55 public: 56 ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle) 57 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) { 58 } 59 ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete; 60 ARMMCCodeEmitter &operator=(const ARMMCCodeEmitter &) = delete; 61 ~ARMMCCodeEmitter() override = default; 62 63 bool isThumb(const MCSubtargetInfo &STI) const { 64 return STI.getFeatureBits()[ARM::ModeThumb]; 65 } 66 67 bool isThumb2(const MCSubtargetInfo &STI) const { 68 return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2]; 69 } 70 71 bool isTargetMachO(const MCSubtargetInfo &STI) const { 72 const Triple &TT = STI.getTargetTriple(); 73 return TT.isOSBinFormatMachO(); 74 } 75 76 unsigned getMachineSoImmOpValue(unsigned SoImm) const; 77 78 // getBinaryCodeForInstr - TableGen'erated function for getting the 79 // binary encoding for an instruction. 80 uint64_t getBinaryCodeForInstr(const MCInst &MI, 81 SmallVectorImpl<MCFixup> &Fixups, 82 const MCSubtargetInfo &STI) const; 83 84 /// getMachineOpValue - Return binary encoding of operand. If the machine 85 /// operand requires relocation, record the relocation and return zero. 86 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 87 SmallVectorImpl<MCFixup> &Fixups, 88 const MCSubtargetInfo &STI) const; 89 90 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of 91 /// the specified operand. This is used for operands with :lower16: and 92 /// :upper16: prefixes. 93 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 94 SmallVectorImpl<MCFixup> &Fixups, 95 const MCSubtargetInfo &STI) const; 96 97 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, 98 unsigned &Reg, unsigned &Imm, 99 SmallVectorImpl<MCFixup> &Fixups, 100 const MCSubtargetInfo &STI) const; 101 102 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate 103 /// BL branch target. 104 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 105 SmallVectorImpl<MCFixup> &Fixups, 106 const MCSubtargetInfo &STI) const; 107 108 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 109 /// BLX branch target. 110 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 111 SmallVectorImpl<MCFixup> &Fixups, 112 const MCSubtargetInfo &STI) const; 113 114 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 115 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 116 SmallVectorImpl<MCFixup> &Fixups, 117 const MCSubtargetInfo &STI) const; 118 119 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 120 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 121 SmallVectorImpl<MCFixup> &Fixups, 122 const MCSubtargetInfo &STI) const; 123 124 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 125 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 126 SmallVectorImpl<MCFixup> &Fixups, 127 const MCSubtargetInfo &STI) const; 128 129 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate 130 /// branch target. 131 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 132 SmallVectorImpl<MCFixup> &Fixups, 133 const MCSubtargetInfo &STI) const; 134 135 /// getThumbBranchTargetOpValue - Return encoding info for 24-bit 136 /// immediate Thumb2 direct branch target. 137 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 138 SmallVectorImpl<MCFixup> &Fixups, 139 const MCSubtargetInfo &STI) const; 140 141 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate 142 /// branch target. 143 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 144 SmallVectorImpl<MCFixup> &Fixups, 145 const MCSubtargetInfo &STI) const; 146 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 147 SmallVectorImpl<MCFixup> &Fixups, 148 const MCSubtargetInfo &STI) const; 149 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 150 SmallVectorImpl<MCFixup> &Fixups, 151 const MCSubtargetInfo &STI) const; 152 153 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate 154 /// ADR label target. 155 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 156 SmallVectorImpl<MCFixup> &Fixups, 157 const MCSubtargetInfo &STI) const; 158 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 159 SmallVectorImpl<MCFixup> &Fixups, 160 const MCSubtargetInfo &STI) const; 161 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 162 SmallVectorImpl<MCFixup> &Fixups, 163 const MCSubtargetInfo &STI) const; 164 165 uint32_t getITMaskOpValue(const MCInst &MI, unsigned OpIdx, 166 SmallVectorImpl<MCFixup> &Fixups, 167 const MCSubtargetInfo &STI) const; 168 169 /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5' 170 /// operand. 171 uint32_t getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx, 172 SmallVectorImpl<MCFixup> &Fixups, 173 const MCSubtargetInfo &STI) const; 174 175 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' 176 /// operand. 177 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 178 SmallVectorImpl<MCFixup> &Fixups, 179 const MCSubtargetInfo &STI) const; 180 181 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand. 182 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 183 SmallVectorImpl<MCFixup> &Fixups, 184 const MCSubtargetInfo &STI) const; 185 186 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2' 187 /// operand. 188 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 189 SmallVectorImpl<MCFixup> &Fixups, 190 const MCSubtargetInfo &STI) const; 191 192 /// getT2AddrModeImm7s4OpValue - Return encoding info for 'reg +/- imm7<<2' 193 /// operand. 194 uint32_t getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx, 195 SmallVectorImpl<MCFixup> &Fixups, 196 const MCSubtargetInfo &STI) const; 197 198 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2' 199 /// operand. 200 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, 201 SmallVectorImpl<MCFixup> &Fixups, 202 const MCSubtargetInfo &STI) const; 203 204 /// getT2ScaledImmOpValue - Return encoding info for '+/- immX<<Y' 205 /// operand. 206 template<unsigned Bits, unsigned Shift> 207 uint32_t getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx, 208 SmallVectorImpl<MCFixup> &Fixups, 209 const MCSubtargetInfo &STI) const; 210 211 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm' 212 /// operand as needed by load/store instructions. 213 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 214 SmallVectorImpl<MCFixup> &Fixups, 215 const MCSubtargetInfo &STI) const; 216 217 /// getLdStmModeOpValue - Return encoding for load/store multiple mode. 218 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, 219 SmallVectorImpl<MCFixup> &Fixups, 220 const MCSubtargetInfo &STI) const { 221 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); 222 switch (Mode) { 223 default: llvm_unreachable("Unknown addressing sub-mode!"); 224 case ARM_AM::da: return 0; 225 case ARM_AM::ia: return 1; 226 case ARM_AM::db: return 2; 227 case ARM_AM::ib: return 3; 228 } 229 } 230 231 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 232 /// 233 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { 234 switch (ShOpc) { 235 case ARM_AM::no_shift: 236 case ARM_AM::lsl: return 0; 237 case ARM_AM::lsr: return 1; 238 case ARM_AM::asr: return 2; 239 case ARM_AM::ror: 240 case ARM_AM::rrx: return 3; 241 } 242 llvm_unreachable("Invalid ShiftOpc!"); 243 } 244 245 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands. 246 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 247 SmallVectorImpl<MCFixup> &Fixups, 248 const MCSubtargetInfo &STI) const; 249 250 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands. 251 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 252 SmallVectorImpl<MCFixup> &Fixups, 253 const MCSubtargetInfo &STI) const; 254 255 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands. 256 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 257 SmallVectorImpl<MCFixup> &Fixups, 258 const MCSubtargetInfo &STI) const; 259 260 /// getAddrMode3OpValue - Return encoding for addrmode3 operands. 261 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 262 SmallVectorImpl<MCFixup> &Fixups, 263 const MCSubtargetInfo &STI) const; 264 265 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12' 266 /// operand. 267 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 268 SmallVectorImpl<MCFixup> &Fixups, 269 const MCSubtargetInfo &STI) const; 270 271 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 272 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 273 SmallVectorImpl<MCFixup> &Fixups, 274 const MCSubtargetInfo &STI) const; 275 276 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 277 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 278 SmallVectorImpl<MCFixup> &Fixups, 279 const MCSubtargetInfo &STI) const; 280 281 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand. 282 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 283 SmallVectorImpl<MCFixup> &Fixups, 284 const MCSubtargetInfo &STI) const; 285 286 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand. 287 uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx, 288 SmallVectorImpl<MCFixup> &Fixups, 289 const MCSubtargetInfo &STI) const; 290 291 /// getCCOutOpValue - Return encoding of the 's' bit. 292 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op, 293 SmallVectorImpl<MCFixup> &Fixups, 294 const MCSubtargetInfo &STI) const { 295 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or 296 // '1' respectively. 297 return MI.getOperand(Op).getReg() == ARM::CPSR; 298 } 299 300 unsigned getModImmOpValue(const MCInst &MI, unsigned Op, 301 SmallVectorImpl<MCFixup> &Fixups, 302 const MCSubtargetInfo &ST) const { 303 const MCOperand &MO = MI.getOperand(Op); 304 305 // Support for fixups (MCFixup) 306 if (MO.isExpr()) { 307 const MCExpr *Expr = MO.getExpr(); 308 // Fixups resolve to plain values that need to be encoded. 309 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_mod_imm); 310 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 311 return 0; 312 } 313 314 // Immediate is already in its encoded format 315 return MO.getImm(); 316 } 317 318 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value. 319 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op, 320 SmallVectorImpl<MCFixup> &Fixups, 321 const MCSubtargetInfo &STI) const { 322 const MCOperand &MO = MI.getOperand(Op); 323 324 // Support for fixups (MCFixup) 325 if (MO.isExpr()) { 326 const MCExpr *Expr = MO.getExpr(); 327 // Fixups resolve to plain values that need to be encoded. 328 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_so_imm); 329 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 330 return 0; 331 } 332 unsigned SoImm = MO.getImm(); 333 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm); 334 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?"); 335 return Encoded; 336 } 337 338 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 339 SmallVectorImpl<MCFixup> &Fixups, 340 const MCSubtargetInfo &STI) const; 341 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, 342 SmallVectorImpl<MCFixup> &Fixups, 343 const MCSubtargetInfo &STI) const; 344 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 345 SmallVectorImpl<MCFixup> &Fixups, 346 const MCSubtargetInfo &STI) const; 347 348 /// getSORegOpValue - Return an encoded so_reg shifted register value. 349 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op, 350 SmallVectorImpl<MCFixup> &Fixups, 351 const MCSubtargetInfo &STI) const; 352 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op, 353 SmallVectorImpl<MCFixup> &Fixups, 354 const MCSubtargetInfo &STI) const; 355 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op, 356 SmallVectorImpl<MCFixup> &Fixups, 357 const MCSubtargetInfo &STI) const; 358 359 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op, 360 SmallVectorImpl<MCFixup> &Fixups, 361 const MCSubtargetInfo &STI) const { 362 return 64 - MI.getOperand(Op).getImm(); 363 } 364 365 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 366 SmallVectorImpl<MCFixup> &Fixups, 367 const MCSubtargetInfo &STI) const; 368 369 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op, 370 SmallVectorImpl<MCFixup> &Fixups, 371 const MCSubtargetInfo &STI) const; 372 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 373 SmallVectorImpl<MCFixup> &Fixups, 374 const MCSubtargetInfo &STI) const; 375 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 376 SmallVectorImpl<MCFixup> &Fixups, 377 const MCSubtargetInfo &STI) const; 378 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 379 SmallVectorImpl<MCFixup> &Fixups, 380 const MCSubtargetInfo &STI) const; 381 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 382 SmallVectorImpl<MCFixup> &Fixups, 383 const MCSubtargetInfo &STI) const; 384 385 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op, 386 SmallVectorImpl<MCFixup> &Fixups, 387 const MCSubtargetInfo &STI) const; 388 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op, 389 SmallVectorImpl<MCFixup> &Fixups, 390 const MCSubtargetInfo &STI) const; 391 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op, 392 SmallVectorImpl<MCFixup> &Fixups, 393 const MCSubtargetInfo &STI) const; 394 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op, 395 SmallVectorImpl<MCFixup> &Fixups, 396 const MCSubtargetInfo &STI) const; 397 398 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op, 399 SmallVectorImpl<MCFixup> &Fixups, 400 const MCSubtargetInfo &STI) const; 401 template <uint8_t shift, bool invert> 402 unsigned getExpandedImmOpValue(const MCInst &MI, unsigned Op, 403 SmallVectorImpl<MCFixup> &Fixups, 404 const MCSubtargetInfo &STI) const { 405 static_assert(shift <= 32, "Shift count must be less than or equal to 32."); 406 const MCOperand MO = MI.getOperand(Op); 407 return (invert ? (MO.getImm() ^ 0xff) : MO.getImm()) >> shift; 408 } 409 410 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, 411 unsigned EncodedValue, 412 const MCSubtargetInfo &STI) const; 413 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI, 414 unsigned EncodedValue, 415 const MCSubtargetInfo &STI) const; 416 unsigned NEONThumb2DupPostEncoder(const MCInst &MI, 417 unsigned EncodedValue, 418 const MCSubtargetInfo &STI) const; 419 unsigned NEONThumb2V8PostEncoder(const MCInst &MI, 420 unsigned EncodedValue, 421 const MCSubtargetInfo &STI) const; 422 423 unsigned VFPThumb2PostEncoder(const MCInst &MI, 424 unsigned EncodedValue, 425 const MCSubtargetInfo &STI) const; 426 427 uint32_t getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx, 428 SmallVectorImpl<MCFixup> &Fixups, 429 const MCSubtargetInfo &STI) const; 430 431 void EmitByte(unsigned char C, raw_ostream &OS) const { 432 OS << (char)C; 433 } 434 435 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const { 436 // Output the constant in little endian byte order. 437 for (unsigned i = 0; i != Size; ++i) { 438 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8; 439 EmitByte((Val >> Shift) & 0xff, OS); 440 } 441 } 442 443 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 444 SmallVectorImpl<MCFixup> &Fixups, 445 const MCSubtargetInfo &STI) const override; 446 447 template <bool isNeg, ARM::Fixups fixup> 448 uint32_t getBFTargetOpValue(const MCInst &MI, unsigned OpIdx, 449 SmallVectorImpl<MCFixup> &Fixups, 450 const MCSubtargetInfo &STI) const; 451 452 uint32_t getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx, 453 SmallVectorImpl<MCFixup> &Fixups, 454 const MCSubtargetInfo &STI) const; 455 456 uint32_t getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx, 457 SmallVectorImpl<MCFixup> &Fixups, 458 const MCSubtargetInfo &STI) const; 459 uint32_t getRestrictedCondCodeOpValue(const MCInst &MI, unsigned OpIdx, 460 SmallVectorImpl<MCFixup> &Fixups, 461 const MCSubtargetInfo &STI) const; 462 template <unsigned size> 463 uint32_t getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx, 464 SmallVectorImpl<MCFixup> &Fixups, 465 const MCSubtargetInfo &STI) const; 466 }; 467 468 } // end anonymous namespace 469 470 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing 471 /// instructions, and rewrite them to their Thumb2 form if we are currently in 472 /// Thumb2 mode. 473 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI, 474 unsigned EncodedValue, 475 const MCSubtargetInfo &STI) const { 476 if (isThumb2(STI)) { 477 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved 478 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are 479 // set to 1111. 480 unsigned Bit24 = EncodedValue & 0x01000000; 481 unsigned Bit28 = Bit24 << 4; 482 EncodedValue &= 0xEFFFFFFF; 483 EncodedValue |= Bit28; 484 EncodedValue |= 0x0F000000; 485 } 486 487 return EncodedValue; 488 } 489 490 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store 491 /// instructions, and rewrite them to their Thumb2 form if we are currently in 492 /// Thumb2 mode. 493 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI, 494 unsigned EncodedValue, 495 const MCSubtargetInfo &STI) const { 496 if (isThumb2(STI)) { 497 EncodedValue &= 0xF0FFFFFF; 498 EncodedValue |= 0x09000000; 499 } 500 501 return EncodedValue; 502 } 503 504 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup 505 /// instructions, and rewrite them to their Thumb2 form if we are currently in 506 /// Thumb2 mode. 507 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI, 508 unsigned EncodedValue, 509 const MCSubtargetInfo &STI) const { 510 if (isThumb2(STI)) { 511 EncodedValue &= 0x00FFFFFF; 512 EncodedValue |= 0xEE000000; 513 } 514 515 return EncodedValue; 516 } 517 518 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form 519 /// if we are in Thumb2. 520 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI, 521 unsigned EncodedValue, 522 const MCSubtargetInfo &STI) const { 523 if (isThumb2(STI)) { 524 EncodedValue |= 0xC000000; // Set bits 27-26 525 } 526 527 return EncodedValue; 528 } 529 530 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite 531 /// them to their Thumb2 form if we are currently in Thumb2 mode. 532 unsigned ARMMCCodeEmitter:: 533 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue, 534 const MCSubtargetInfo &STI) const { 535 if (isThumb2(STI)) { 536 EncodedValue &= 0x0FFFFFFF; 537 EncodedValue |= 0xE0000000; 538 } 539 return EncodedValue; 540 } 541 542 /// getMachineOpValue - Return binary encoding of operand. If the machine 543 /// operand requires relocation, record the relocation and return zero. 544 unsigned ARMMCCodeEmitter:: 545 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 546 SmallVectorImpl<MCFixup> &Fixups, 547 const MCSubtargetInfo &STI) const { 548 if (MO.isReg()) { 549 unsigned Reg = MO.getReg(); 550 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); 551 552 // In NEON, Q registers are encoded as 2x their register number, 553 // because they're using the same indices as the D registers they 554 // overlap. In MVE, there are no 64-bit vector instructions, so 555 // the encodings all refer to Q-registers by their literal 556 // register number. 557 558 if (STI.getFeatureBits()[ARM::HasMVEIntegerOps]) 559 return RegNo; 560 561 switch (Reg) { 562 default: 563 return RegNo; 564 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3: 565 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: 566 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11: 567 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15: 568 return 2 * RegNo; 569 } 570 } else if (MO.isImm()) { 571 return static_cast<unsigned>(MO.getImm()); 572 } else if (MO.isFPImm()) { 573 return static_cast<unsigned>(APFloat(MO.getFPImm()) 574 .bitcastToAPInt().getHiBits(32).getLimitedValue()); 575 } 576 577 llvm_unreachable("Unable to encode MCOperand!"); 578 } 579 580 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. 581 bool ARMMCCodeEmitter:: 582 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, 583 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups, 584 const MCSubtargetInfo &STI) const { 585 const MCOperand &MO = MI.getOperand(OpIdx); 586 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 587 588 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 589 590 int32_t SImm = MO1.getImm(); 591 bool isAdd = true; 592 593 // Special value for #-0 594 if (SImm == INT32_MIN) { 595 SImm = 0; 596 isAdd = false; 597 } 598 599 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 600 if (SImm < 0) { 601 SImm = -SImm; 602 isAdd = false; 603 } 604 605 Imm = SImm; 606 return isAdd; 607 } 608 609 /// getBranchTargetOpValue - Helper function to get the branch target operand, 610 /// which is either an immediate or requires a fixup. 611 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 612 unsigned FixupKind, 613 SmallVectorImpl<MCFixup> &Fixups, 614 const MCSubtargetInfo &STI) { 615 const MCOperand &MO = MI.getOperand(OpIdx); 616 617 // If the destination is an immediate, we have nothing to do. 618 if (MO.isImm()) return MO.getImm(); 619 assert(MO.isExpr() && "Unexpected branch target type!"); 620 const MCExpr *Expr = MO.getExpr(); 621 MCFixupKind Kind = MCFixupKind(FixupKind); 622 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 623 624 // All of the information is in the fixup. 625 return 0; 626 } 627 628 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are 629 // determined by negating them and XOR'ing them with bit 23. 630 static int32_t encodeThumbBLOffset(int32_t offset) { 631 offset >>= 1; 632 uint32_t S = (offset & 0x800000) >> 23; 633 uint32_t J1 = (offset & 0x400000) >> 22; 634 uint32_t J2 = (offset & 0x200000) >> 21; 635 J1 = (~J1 & 0x1); 636 J2 = (~J2 & 0x1); 637 J1 ^= S; 638 J2 ^= S; 639 640 offset &= ~0x600000; 641 offset |= J1 << 22; 642 offset |= J2 << 21; 643 644 return offset; 645 } 646 647 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target. 648 uint32_t ARMMCCodeEmitter:: 649 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 650 SmallVectorImpl<MCFixup> &Fixups, 651 const MCSubtargetInfo &STI) const { 652 const MCOperand MO = MI.getOperand(OpIdx); 653 if (MO.isExpr()) 654 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, 655 Fixups, STI); 656 return encodeThumbBLOffset(MO.getImm()); 657 } 658 659 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 660 /// BLX branch target. 661 uint32_t ARMMCCodeEmitter:: 662 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 663 SmallVectorImpl<MCFixup> &Fixups, 664 const MCSubtargetInfo &STI) const { 665 const MCOperand MO = MI.getOperand(OpIdx); 666 if (MO.isExpr()) 667 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, 668 Fixups, STI); 669 return encodeThumbBLOffset(MO.getImm()); 670 } 671 672 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 673 uint32_t ARMMCCodeEmitter:: 674 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 675 SmallVectorImpl<MCFixup> &Fixups, 676 const MCSubtargetInfo &STI) const { 677 const MCOperand MO = MI.getOperand(OpIdx); 678 if (MO.isExpr()) 679 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, 680 Fixups, STI); 681 return (MO.getImm() >> 1); 682 } 683 684 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 685 uint32_t ARMMCCodeEmitter:: 686 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 687 SmallVectorImpl<MCFixup> &Fixups, 688 const MCSubtargetInfo &STI) const { 689 const MCOperand MO = MI.getOperand(OpIdx); 690 if (MO.isExpr()) 691 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, 692 Fixups, STI); 693 return (MO.getImm() >> 1); 694 } 695 696 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 697 uint32_t ARMMCCodeEmitter:: 698 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 699 SmallVectorImpl<MCFixup> &Fixups, 700 const MCSubtargetInfo &STI) const { 701 const MCOperand MO = MI.getOperand(OpIdx); 702 if (MO.isExpr()) 703 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI); 704 return (MO.getImm() >> 1); 705 } 706 707 /// Return true if this branch has a non-always predication 708 static bool HasConditionalBranch(const MCInst &MI) { 709 int NumOp = MI.getNumOperands(); 710 if (NumOp >= 2) { 711 for (int i = 0; i < NumOp-1; ++i) { 712 const MCOperand &MCOp1 = MI.getOperand(i); 713 const MCOperand &MCOp2 = MI.getOperand(i + 1); 714 if (MCOp1.isImm() && MCOp2.isReg() && 715 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) { 716 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL) 717 return true; 718 } 719 } 720 } 721 return false; 722 } 723 724 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 725 /// target. 726 uint32_t ARMMCCodeEmitter:: 727 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 728 SmallVectorImpl<MCFixup> &Fixups, 729 const MCSubtargetInfo &STI) const { 730 // FIXME: This really, really shouldn't use TargetMachine. We don't want 731 // coupling between MC and TM anywhere we can help it. 732 if (isThumb2(STI)) 733 return 734 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI); 735 return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI); 736 } 737 738 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 739 /// target. 740 uint32_t ARMMCCodeEmitter:: 741 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 742 SmallVectorImpl<MCFixup> &Fixups, 743 const MCSubtargetInfo &STI) const { 744 const MCOperand MO = MI.getOperand(OpIdx); 745 if (MO.isExpr()) { 746 if (HasConditionalBranch(MI)) 747 return ::getBranchTargetOpValue(MI, OpIdx, 748 ARM::fixup_arm_condbranch, Fixups, STI); 749 return ::getBranchTargetOpValue(MI, OpIdx, 750 ARM::fixup_arm_uncondbranch, Fixups, STI); 751 } 752 753 return MO.getImm() >> 2; 754 } 755 756 uint32_t ARMMCCodeEmitter:: 757 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 758 SmallVectorImpl<MCFixup> &Fixups, 759 const MCSubtargetInfo &STI) const { 760 const MCOperand MO = MI.getOperand(OpIdx); 761 if (MO.isExpr()) { 762 if (HasConditionalBranch(MI)) 763 return ::getBranchTargetOpValue(MI, OpIdx, 764 ARM::fixup_arm_condbl, Fixups, STI); 765 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI); 766 } 767 768 return MO.getImm() >> 2; 769 } 770 771 uint32_t ARMMCCodeEmitter:: 772 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 773 SmallVectorImpl<MCFixup> &Fixups, 774 const MCSubtargetInfo &STI) const { 775 const MCOperand MO = MI.getOperand(OpIdx); 776 if (MO.isExpr()) 777 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI); 778 779 return MO.getImm() >> 1; 780 } 781 782 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit 783 /// immediate branch target. 784 uint32_t ARMMCCodeEmitter::getThumbBranchTargetOpValue( 785 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, 786 const MCSubtargetInfo &STI) const { 787 unsigned Val = 0; 788 const MCOperand MO = MI.getOperand(OpIdx); 789 790 if(MO.isExpr()) 791 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI); 792 else 793 Val = MO.getImm() >> 1; 794 795 bool I = (Val & 0x800000); 796 bool J1 = (Val & 0x400000); 797 bool J2 = (Val & 0x200000); 798 if (I ^ J1) 799 Val &= ~0x400000; 800 else 801 Val |= 0x400000; 802 803 if (I ^ J2) 804 Val &= ~0x200000; 805 else 806 Val |= 0x200000; 807 808 return Val; 809 } 810 811 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate 812 /// ADR label target. 813 uint32_t ARMMCCodeEmitter:: 814 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 815 SmallVectorImpl<MCFixup> &Fixups, 816 const MCSubtargetInfo &STI) const { 817 const MCOperand MO = MI.getOperand(OpIdx); 818 if (MO.isExpr()) 819 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12, 820 Fixups, STI); 821 int64_t offset = MO.getImm(); 822 uint32_t Val = 0x2000; 823 824 int SoImmVal; 825 if (offset == INT32_MIN) { 826 Val = 0x1000; 827 SoImmVal = 0; 828 } else if (offset < 0) { 829 Val = 0x1000; 830 offset *= -1; 831 SoImmVal = ARM_AM::getSOImmVal(offset); 832 if(SoImmVal == -1) { 833 Val = 0x2000; 834 offset *= -1; 835 SoImmVal = ARM_AM::getSOImmVal(offset); 836 } 837 } else { 838 SoImmVal = ARM_AM::getSOImmVal(offset); 839 if(SoImmVal == -1) { 840 Val = 0x1000; 841 offset *= -1; 842 SoImmVal = ARM_AM::getSOImmVal(offset); 843 } 844 } 845 846 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 847 848 Val |= SoImmVal; 849 return Val; 850 } 851 852 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label 853 /// target. 854 uint32_t ARMMCCodeEmitter:: 855 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 856 SmallVectorImpl<MCFixup> &Fixups, 857 const MCSubtargetInfo &STI) const { 858 const MCOperand MO = MI.getOperand(OpIdx); 859 if (MO.isExpr()) 860 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12, 861 Fixups, STI); 862 int32_t Val = MO.getImm(); 863 if (Val == INT32_MIN) 864 Val = 0x1000; 865 else if (Val < 0) { 866 Val *= -1; 867 Val |= 0x1000; 868 } 869 return Val; 870 } 871 872 /// getITMaskOpValue - Return the architectural encoding of an IT 873 /// predication mask, given the MCOperand format. 874 uint32_t ARMMCCodeEmitter:: 875 getITMaskOpValue(const MCInst &MI, unsigned OpIdx, 876 SmallVectorImpl<MCFixup> &Fixups, 877 const MCSubtargetInfo &STI) const { 878 const MCOperand MaskMO = MI.getOperand(OpIdx); 879 assert(MaskMO.isImm() && "Unexpected operand type!"); 880 881 unsigned Mask = MaskMO.getImm(); 882 883 // IT masks are encoded as a sequence of replacement low-order bits 884 // for the condition code. So if the low bit of the starting 885 // condition code is 1, then we have to flip all the bits above the 886 // terminating bit (which is the lowest 1 bit). 887 assert(OpIdx > 0 && "IT mask appears first!"); 888 const MCOperand CondMO = MI.getOperand(OpIdx-1); 889 assert(CondMO.isImm() && "Unexpected operand type!"); 890 if (CondMO.getImm() & 1) { 891 unsigned LowBit = Mask & -Mask; 892 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 893 Mask ^= BitsAboveLowBit; 894 } 895 896 return Mask; 897 } 898 899 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label 900 /// target. 901 uint32_t ARMMCCodeEmitter:: 902 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 903 SmallVectorImpl<MCFixup> &Fixups, 904 const MCSubtargetInfo &STI) const { 905 const MCOperand MO = MI.getOperand(OpIdx); 906 if (MO.isExpr()) 907 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10, 908 Fixups, STI); 909 return MO.getImm(); 910 } 911 912 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg' 913 /// operand. 914 uint32_t ARMMCCodeEmitter:: 915 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 916 SmallVectorImpl<MCFixup> &, 917 const MCSubtargetInfo &STI) const { 918 // [Rn, Rm] 919 // {5-3} = Rm 920 // {2-0} = Rn 921 const MCOperand &MO1 = MI.getOperand(OpIdx); 922 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); 923 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 924 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); 925 return (Rm << 3) | Rn; 926 } 927 928 /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5' 929 /// operand. 930 uint32_t 931 ARMMCCodeEmitter::getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx, 932 SmallVectorImpl<MCFixup> &Fixups, 933 const MCSubtargetInfo &STI) const { 934 // {4-0} = szimm5 935 // The value we are trying to encode is an immediate between either the 936 // range of [1-7] or [1-15] depending on whether we are dealing with the 937 // u8/s8 or the u16/s16 variants respectively. 938 // This value is encoded as follows, if ShiftImm is the value within those 939 // ranges then the encoding szimm5 = ShiftImm + size, where size is either 8 940 // or 16. 941 942 unsigned Size, ShiftImm; 943 switch(MI.getOpcode()) { 944 case ARM::MVE_VSHLL_imms16bh: 945 case ARM::MVE_VSHLL_imms16th: 946 case ARM::MVE_VSHLL_immu16bh: 947 case ARM::MVE_VSHLL_immu16th: 948 Size = 16; 949 break; 950 case ARM::MVE_VSHLL_imms8bh: 951 case ARM::MVE_VSHLL_imms8th: 952 case ARM::MVE_VSHLL_immu8bh: 953 case ARM::MVE_VSHLL_immu8th: 954 Size = 8; 955 break; 956 default: 957 llvm_unreachable("Use of operand not supported by this instruction"); 958 } 959 ShiftImm = MI.getOperand(OpIdx).getImm(); 960 return Size + ShiftImm; 961 } 962 963 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand. 964 uint32_t ARMMCCodeEmitter:: 965 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 966 SmallVectorImpl<MCFixup> &Fixups, 967 const MCSubtargetInfo &STI) const { 968 // {17-13} = reg 969 // {12} = (U)nsigned (add == '1', sub == '0') 970 // {11-0} = imm12 971 unsigned Reg, Imm12; 972 bool isAdd = true; 973 // If The first operand isn't a register, we have a label reference. 974 const MCOperand &MO = MI.getOperand(OpIdx); 975 if (!MO.isReg()) { 976 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 977 Imm12 = 0; 978 979 if (MO.isExpr()) { 980 const MCExpr *Expr = MO.getExpr(); 981 isAdd = false ; // 'U' bit is set as part of the fixup. 982 983 MCFixupKind Kind; 984 if (isThumb2(STI)) 985 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12); 986 else 987 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12); 988 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 989 990 ++MCNumCPRelocations; 991 } else { 992 Reg = ARM::PC; 993 int32_t Offset = MO.getImm(); 994 if (Offset == INT32_MIN) { 995 Offset = 0; 996 isAdd = false; 997 } else if (Offset < 0) { 998 Offset *= -1; 999 isAdd = false; 1000 } 1001 Imm12 = Offset; 1002 } 1003 } else 1004 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI); 1005 1006 uint32_t Binary = Imm12 & 0xfff; 1007 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1008 if (isAdd) 1009 Binary |= (1 << 12); 1010 Binary |= (Reg << 13); 1011 return Binary; 1012 } 1013 1014 template<unsigned Bits, unsigned Shift> 1015 uint32_t ARMMCCodeEmitter:: 1016 getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx, 1017 SmallVectorImpl<MCFixup> &Fixups, 1018 const MCSubtargetInfo &STI) const { 1019 // FIXME: The immediate operand should have already been encoded like this 1020 // before ever getting here. The encoder method should just need to combine 1021 // the MI operands for the register and the offset into a single 1022 // representation for the complex operand in the .td file. This isn't just 1023 // style, unfortunately. As-is, we can't represent the distinct encoding 1024 // for #-0. 1025 1026 // {Bits} = (U)nsigned (add == '1', sub == '0') 1027 // {(Bits-1)-0} = immediate 1028 int32_t Imm = MI.getOperand(OpIdx).getImm(); 1029 bool isAdd = Imm >= 0; 1030 1031 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1032 if (Imm < 0) 1033 Imm = -(uint32_t)Imm; 1034 1035 Imm >>= Shift; 1036 1037 uint32_t Binary = Imm & ((1U << Bits) - 1); 1038 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1039 if (isAdd) 1040 Binary |= (1U << Bits); 1041 return Binary; 1042 } 1043 /// getT2AddrModeImm8s4OpValue - Return encoding info for 1044 /// 'reg +/- imm8<<2' operand. 1045 uint32_t ARMMCCodeEmitter:: 1046 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 1047 SmallVectorImpl<MCFixup> &Fixups, 1048 const MCSubtargetInfo &STI) const { 1049 // {12-9} = reg 1050 // {8} = (U)nsigned (add == '1', sub == '0') 1051 // {7-0} = imm8 1052 unsigned Reg, Imm8; 1053 bool isAdd = true; 1054 // If The first operand isn't a register, we have a label reference. 1055 const MCOperand &MO = MI.getOperand(OpIdx); 1056 if (!MO.isReg()) { 1057 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 1058 Imm8 = 0; 1059 isAdd = false ; // 'U' bit is set as part of the fixup. 1060 1061 assert(MO.isExpr() && "Unexpected machine operand type!"); 1062 const MCExpr *Expr = MO.getExpr(); 1063 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); 1064 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 1065 1066 ++MCNumCPRelocations; 1067 } else 1068 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); 1069 1070 // FIXME: The immediate operand should have already been encoded like this 1071 // before ever getting here. The encoder method should just need to combine 1072 // the MI operands for the register and the offset into a single 1073 // representation for the complex operand in the .td file. This isn't just 1074 // style, unfortunately. As-is, we can't represent the distinct encoding 1075 // for #-0. 1076 uint32_t Binary = (Imm8 >> 2) & 0xff; 1077 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1078 if (isAdd) 1079 Binary |= (1 << 8); 1080 Binary |= (Reg << 9); 1081 return Binary; 1082 } 1083 1084 /// getT2AddrModeImm7s4OpValue - Return encoding info for 1085 /// 'reg +/- imm7<<2' operand. 1086 uint32_t 1087 ARMMCCodeEmitter::getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx, 1088 SmallVectorImpl<MCFixup> &Fixups, 1089 const MCSubtargetInfo &STI) const { 1090 // {11-8} = reg 1091 // {7} = (A)dd (add == '1', sub == '0') 1092 // {6-0} = imm7 1093 unsigned Reg, Imm7; 1094 // If The first operand isn't a register, we have a label reference. 1095 bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm7, Fixups, STI); 1096 1097 // FIXME: The immediate operand should have already been encoded like this 1098 // before ever getting here. The encoder method should just need to combine 1099 // the MI operands for the register and the offset into a single 1100 // representation for the complex operand in the .td file. This isn't just 1101 // style, unfortunately. As-is, we can't represent the distinct encoding 1102 // for #-0. 1103 uint32_t Binary = (Imm7 >> 2) & 0xff; 1104 // Immediate is always encoded as positive. The 'A' bit controls add vs sub. 1105 if (isAdd) 1106 Binary |= (1 << 7); 1107 Binary |= (Reg << 8); 1108 return Binary; 1109 } 1110 1111 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 1112 /// 'reg + imm8<<2' operand. 1113 uint32_t ARMMCCodeEmitter:: 1114 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, 1115 SmallVectorImpl<MCFixup> &Fixups, 1116 const MCSubtargetInfo &STI) const { 1117 // {11-8} = reg 1118 // {7-0} = imm8 1119 const MCOperand &MO = MI.getOperand(OpIdx); 1120 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1121 unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1122 unsigned Imm8 = MO1.getImm(); 1123 return (Reg << 8) | Imm8; 1124 } 1125 1126 uint32_t 1127 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 1128 SmallVectorImpl<MCFixup> &Fixups, 1129 const MCSubtargetInfo &STI) const { 1130 // {20-16} = imm{15-12} 1131 // {11-0} = imm{11-0} 1132 const MCOperand &MO = MI.getOperand(OpIdx); 1133 if (MO.isImm()) 1134 // Hi / lo 16 bits already extracted during earlier passes. 1135 return static_cast<unsigned>(MO.getImm()); 1136 1137 // Handle :upper16: and :lower16: assembly prefixes. 1138 const MCExpr *E = MO.getExpr(); 1139 MCFixupKind Kind; 1140 if (E->getKind() == MCExpr::Target) { 1141 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E); 1142 E = ARM16Expr->getSubExpr(); 1143 1144 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) { 1145 const int64_t Value = MCE->getValue(); 1146 if (Value > UINT32_MAX) 1147 report_fatal_error("constant value truncated (limited to 32-bit)"); 1148 1149 switch (ARM16Expr->getKind()) { 1150 case ARMMCExpr::VK_ARM_HI16: 1151 return (int32_t(Value) & 0xffff0000) >> 16; 1152 case ARMMCExpr::VK_ARM_LO16: 1153 return (int32_t(Value) & 0x0000ffff); 1154 default: llvm_unreachable("Unsupported ARMFixup"); 1155 } 1156 } 1157 1158 switch (ARM16Expr->getKind()) { 1159 default: llvm_unreachable("Unsupported ARMFixup"); 1160 case ARMMCExpr::VK_ARM_HI16: 1161 Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movt_hi16 1162 : ARM::fixup_arm_movt_hi16); 1163 break; 1164 case ARMMCExpr::VK_ARM_LO16: 1165 Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movw_lo16 1166 : ARM::fixup_arm_movw_lo16); 1167 break; 1168 } 1169 1170 Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc())); 1171 return 0; 1172 } 1173 // If the expression doesn't have :upper16: or :lower16: on it, 1174 // it's just a plain immediate expression, previously those evaluated to 1175 // the lower 16 bits of the expression regardless of whether 1176 // we have a movt or a movw, but that led to misleadingly results. 1177 // This is disallowed in the AsmParser in validateInstruction() 1178 // so this should never happen. 1179 llvm_unreachable("expression without :upper16: or :lower16:"); 1180 } 1181 1182 uint32_t ARMMCCodeEmitter:: 1183 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 1184 SmallVectorImpl<MCFixup> &Fixups, 1185 const MCSubtargetInfo &STI) const { 1186 const MCOperand &MO = MI.getOperand(OpIdx); 1187 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1188 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 1189 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1190 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1191 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); 1192 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; 1193 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); 1194 unsigned SBits = getShiftOp(ShOp); 1195 1196 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift 1197 // amount. However, it would be an easy mistake to make so check here. 1198 assert((ShImm & ~0x1f) == 0 && "Out of range shift amount"); 1199 1200 // {16-13} = Rn 1201 // {12} = isAdd 1202 // {11-0} = shifter 1203 // {3-0} = Rm 1204 // {4} = 0 1205 // {6-5} = type 1206 // {11-7} = imm 1207 uint32_t Binary = Rm; 1208 Binary |= Rn << 13; 1209 Binary |= SBits << 5; 1210 Binary |= ShImm << 7; 1211 if (isAdd) 1212 Binary |= 1 << 12; 1213 return Binary; 1214 } 1215 1216 uint32_t ARMMCCodeEmitter:: 1217 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 1218 SmallVectorImpl<MCFixup> &Fixups, 1219 const MCSubtargetInfo &STI) const { 1220 // {13} 1 == imm12, 0 == Rm 1221 // {12} isAdd 1222 // {11-0} imm12/Rm 1223 const MCOperand &MO = MI.getOperand(OpIdx); 1224 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1225 unsigned Imm = MO1.getImm(); 1226 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add; 1227 bool isReg = MO.getReg() != 0; 1228 uint32_t Binary = ARM_AM::getAM2Offset(Imm); 1229 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12 1230 if (isReg) { 1231 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); 1232 Binary <<= 7; // Shift amount is bits [11:7] 1233 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] 1234 Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0] 1235 } 1236 return Binary | (isAdd << 12) | (isReg << 13); 1237 } 1238 1239 uint32_t ARMMCCodeEmitter:: 1240 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 1241 SmallVectorImpl<MCFixup> &Fixups, 1242 const MCSubtargetInfo &STI) const { 1243 // {4} isAdd 1244 // {3-0} Rm 1245 const MCOperand &MO = MI.getOperand(OpIdx); 1246 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1247 bool isAdd = MO1.getImm() != 0; 1248 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4); 1249 } 1250 1251 uint32_t ARMMCCodeEmitter:: 1252 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 1253 SmallVectorImpl<MCFixup> &Fixups, 1254 const MCSubtargetInfo &STI) const { 1255 // {9} 1 == imm8, 0 == Rm 1256 // {8} isAdd 1257 // {7-4} imm7_4/zero 1258 // {3-0} imm3_0/Rm 1259 const MCOperand &MO = MI.getOperand(OpIdx); 1260 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1261 unsigned Imm = MO1.getImm(); 1262 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 1263 bool isImm = MO.getReg() == 0; 1264 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 1265 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 1266 if (!isImm) 1267 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1268 return Imm8 | (isAdd << 8) | (isImm << 9); 1269 } 1270 1271 uint32_t ARMMCCodeEmitter:: 1272 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 1273 SmallVectorImpl<MCFixup> &Fixups, 1274 const MCSubtargetInfo &STI) const { 1275 // {13} 1 == imm8, 0 == Rm 1276 // {12-9} Rn 1277 // {8} isAdd 1278 // {7-4} imm7_4/zero 1279 // {3-0} imm3_0/Rm 1280 const MCOperand &MO = MI.getOperand(OpIdx); 1281 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1282 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 1283 1284 // If The first operand isn't a register, we have a label reference. 1285 if (!MO.isReg()) { 1286 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 1287 1288 assert(MO.isExpr() && "Unexpected machine operand type!"); 1289 const MCExpr *Expr = MO.getExpr(); 1290 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled); 1291 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 1292 1293 ++MCNumCPRelocations; 1294 return (Rn << 9) | (1 << 13); 1295 } 1296 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1297 unsigned Imm = MO2.getImm(); 1298 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 1299 bool isImm = MO1.getReg() == 0; 1300 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 1301 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 1302 if (!isImm) 1303 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1304 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13); 1305 } 1306 1307 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands. 1308 uint32_t ARMMCCodeEmitter:: 1309 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 1310 SmallVectorImpl<MCFixup> &Fixups, 1311 const MCSubtargetInfo &STI) const { 1312 // [SP, #imm] 1313 // {7-0} = imm8 1314 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1315 assert(MI.getOperand(OpIdx).getReg() == ARM::SP && 1316 "Unexpected base register!"); 1317 1318 // The immediate is already shifted for the implicit zeroes, so no change 1319 // here. 1320 return MO1.getImm() & 0xff; 1321 } 1322 1323 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 1324 uint32_t ARMMCCodeEmitter:: 1325 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 1326 SmallVectorImpl<MCFixup> &Fixups, 1327 const MCSubtargetInfo &STI) const { 1328 // [Rn, #imm] 1329 // {7-3} = imm5 1330 // {2-0} = Rn 1331 const MCOperand &MO = MI.getOperand(OpIdx); 1332 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1333 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1334 unsigned Imm5 = MO1.getImm(); 1335 return ((Imm5 & 0x1f) << 3) | Rn; 1336 } 1337 1338 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 1339 uint32_t ARMMCCodeEmitter:: 1340 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 1341 SmallVectorImpl<MCFixup> &Fixups, 1342 const MCSubtargetInfo &STI) const { 1343 const MCOperand MO = MI.getOperand(OpIdx); 1344 if (MO.isExpr()) 1345 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI); 1346 return (MO.getImm() >> 2); 1347 } 1348 1349 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand. 1350 uint32_t ARMMCCodeEmitter:: 1351 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 1352 SmallVectorImpl<MCFixup> &Fixups, 1353 const MCSubtargetInfo &STI) const { 1354 // {12-9} = reg 1355 // {8} = (U)nsigned (add == '1', sub == '0') 1356 // {7-0} = imm8 1357 unsigned Reg, Imm8; 1358 bool isAdd; 1359 // If The first operand isn't a register, we have a label reference. 1360 const MCOperand &MO = MI.getOperand(OpIdx); 1361 if (!MO.isReg()) { 1362 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 1363 Imm8 = 0; 1364 isAdd = false; // 'U' bit is handled as part of the fixup. 1365 1366 assert(MO.isExpr() && "Unexpected machine operand type!"); 1367 const MCExpr *Expr = MO.getExpr(); 1368 MCFixupKind Kind; 1369 if (isThumb2(STI)) 1370 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); 1371 else 1372 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10); 1373 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 1374 1375 ++MCNumCPRelocations; 1376 } else { 1377 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); 1378 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add; 1379 } 1380 1381 uint32_t Binary = ARM_AM::getAM5Offset(Imm8); 1382 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1383 if (isAdd) 1384 Binary |= (1 << 8); 1385 Binary |= (Reg << 9); 1386 return Binary; 1387 } 1388 1389 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand. 1390 uint32_t ARMMCCodeEmitter:: 1391 getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx, 1392 SmallVectorImpl<MCFixup> &Fixups, 1393 const MCSubtargetInfo &STI) const { 1394 // {12-9} = reg 1395 // {8} = (U)nsigned (add == '1', sub == '0') 1396 // {7-0} = imm8 1397 unsigned Reg, Imm8; 1398 bool isAdd; 1399 // If The first operand isn't a register, we have a label reference. 1400 const MCOperand &MO = MI.getOperand(OpIdx); 1401 if (!MO.isReg()) { 1402 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 1403 Imm8 = 0; 1404 isAdd = false; // 'U' bit is handled as part of the fixup. 1405 1406 assert(MO.isExpr() && "Unexpected machine operand type!"); 1407 const MCExpr *Expr = MO.getExpr(); 1408 MCFixupKind Kind; 1409 if (isThumb2(STI)) 1410 Kind = MCFixupKind(ARM::fixup_t2_pcrel_9); 1411 else 1412 Kind = MCFixupKind(ARM::fixup_arm_pcrel_9); 1413 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 1414 1415 ++MCNumCPRelocations; 1416 } else { 1417 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); 1418 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add; 1419 } 1420 1421 uint32_t Binary = ARM_AM::getAM5Offset(Imm8); 1422 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1423 if (isAdd) 1424 Binary |= (1 << 8); 1425 Binary |= (Reg << 9); 1426 return Binary; 1427 } 1428 1429 unsigned ARMMCCodeEmitter:: 1430 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, 1431 SmallVectorImpl<MCFixup> &Fixups, 1432 const MCSubtargetInfo &STI) const { 1433 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be 1434 // shifted. The second is Rs, the amount to shift by, and the third specifies 1435 // the type of the shift. 1436 // 1437 // {3-0} = Rm. 1438 // {4} = 1 1439 // {6-5} = type 1440 // {11-8} = Rs 1441 // {7} = 0 1442 1443 const MCOperand &MO = MI.getOperand(OpIdx); 1444 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1445 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); 1446 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 1447 1448 // Encode Rm. 1449 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1450 1451 // Encode the shift opcode. 1452 unsigned SBits = 0; 1453 unsigned Rs = MO1.getReg(); 1454 if (Rs) { 1455 // Set shift operand (bit[7:4]). 1456 // LSL - 0001 1457 // LSR - 0011 1458 // ASR - 0101 1459 // ROR - 0111 1460 switch (SOpc) { 1461 default: llvm_unreachable("Unknown shift opc!"); 1462 case ARM_AM::lsl: SBits = 0x1; break; 1463 case ARM_AM::lsr: SBits = 0x3; break; 1464 case ARM_AM::asr: SBits = 0x5; break; 1465 case ARM_AM::ror: SBits = 0x7; break; 1466 } 1467 } 1468 1469 Binary |= SBits << 4; 1470 1471 // Encode the shift operation Rs. 1472 // Encode Rs bit[11:8]. 1473 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 1474 return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift); 1475 } 1476 1477 unsigned ARMMCCodeEmitter:: 1478 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, 1479 SmallVectorImpl<MCFixup> &Fixups, 1480 const MCSubtargetInfo &STI) const { 1481 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 1482 // shifted. The second is the amount to shift by. 1483 // 1484 // {3-0} = Rm. 1485 // {4} = 0 1486 // {6-5} = type 1487 // {11-7} = imm 1488 1489 const MCOperand &MO = MI.getOperand(OpIdx); 1490 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1491 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 1492 1493 // Encode Rm. 1494 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1495 1496 // Encode the shift opcode. 1497 unsigned SBits = 0; 1498 1499 // Set shift operand (bit[6:4]). 1500 // LSL - 000 1501 // LSR - 010 1502 // ASR - 100 1503 // ROR - 110 1504 // RRX - 110 and bit[11:8] clear. 1505 switch (SOpc) { 1506 default: llvm_unreachable("Unknown shift opc!"); 1507 case ARM_AM::lsl: SBits = 0x0; break; 1508 case ARM_AM::lsr: SBits = 0x2; break; 1509 case ARM_AM::asr: SBits = 0x4; break; 1510 case ARM_AM::ror: SBits = 0x6; break; 1511 case ARM_AM::rrx: 1512 Binary |= 0x60; 1513 return Binary; 1514 } 1515 1516 // Encode shift_imm bit[11:7]. 1517 Binary |= SBits << 4; 1518 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm()); 1519 assert(Offset < 32 && "Offset must be in range 0-31!"); 1520 return Binary | (Offset << 7); 1521 } 1522 1523 1524 unsigned ARMMCCodeEmitter:: 1525 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 1526 SmallVectorImpl<MCFixup> &Fixups, 1527 const MCSubtargetInfo &STI) const { 1528 const MCOperand &MO1 = MI.getOperand(OpNum); 1529 const MCOperand &MO2 = MI.getOperand(OpNum+1); 1530 const MCOperand &MO3 = MI.getOperand(OpNum+2); 1531 1532 // Encoded as [Rn, Rm, imm]. 1533 // FIXME: Needs fixup support. 1534 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1535 Value <<= 4; 1536 Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); 1537 Value <<= 2; 1538 Value |= MO3.getImm(); 1539 1540 return Value; 1541 } 1542 1543 unsigned ARMMCCodeEmitter:: 1544 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, 1545 SmallVectorImpl<MCFixup> &Fixups, 1546 const MCSubtargetInfo &STI) const { 1547 const MCOperand &MO1 = MI.getOperand(OpNum); 1548 const MCOperand &MO2 = MI.getOperand(OpNum+1); 1549 1550 // FIXME: Needs fixup support. 1551 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1552 1553 // Even though the immediate is 8 bits long, we need 9 bits in order 1554 // to represent the (inverse of the) sign bit. 1555 Value <<= 9; 1556 int32_t tmp = (int32_t)MO2.getImm(); 1557 if (tmp < 0) 1558 tmp = abs(tmp); 1559 else 1560 Value |= 256; // Set the ADD bit 1561 Value |= tmp & 255; 1562 return Value; 1563 } 1564 1565 unsigned ARMMCCodeEmitter:: 1566 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 1567 SmallVectorImpl<MCFixup> &Fixups, 1568 const MCSubtargetInfo &STI) const { 1569 const MCOperand &MO1 = MI.getOperand(OpNum); 1570 1571 // FIXME: Needs fixup support. 1572 unsigned Value = 0; 1573 int32_t tmp = (int32_t)MO1.getImm(); 1574 if (tmp < 0) 1575 tmp = abs(tmp); 1576 else 1577 Value |= 256; // Set the ADD bit 1578 Value |= tmp & 255; 1579 return Value; 1580 } 1581 1582 unsigned ARMMCCodeEmitter:: 1583 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx, 1584 SmallVectorImpl<MCFixup> &Fixups, 1585 const MCSubtargetInfo &STI) const { 1586 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 1587 // shifted. The second is the amount to shift by. 1588 // 1589 // {3-0} = Rm. 1590 // {4} = 0 1591 // {6-5} = type 1592 // {11-7} = imm 1593 1594 const MCOperand &MO = MI.getOperand(OpIdx); 1595 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1596 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 1597 1598 // Encode Rm. 1599 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1600 1601 // Encode the shift opcode. 1602 unsigned SBits = 0; 1603 // Set shift operand (bit[6:4]). 1604 // LSL - 000 1605 // LSR - 010 1606 // ASR - 100 1607 // ROR - 110 1608 switch (SOpc) { 1609 default: llvm_unreachable("Unknown shift opc!"); 1610 case ARM_AM::lsl: SBits = 0x0; break; 1611 case ARM_AM::lsr: SBits = 0x2; break; 1612 case ARM_AM::asr: SBits = 0x4; break; 1613 case ARM_AM::rrx: LLVM_FALLTHROUGH; 1614 case ARM_AM::ror: SBits = 0x6; break; 1615 } 1616 1617 Binary |= SBits << 4; 1618 if (SOpc == ARM_AM::rrx) 1619 return Binary; 1620 1621 // Encode shift_imm bit[11:7]. 1622 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7; 1623 } 1624 1625 unsigned ARMMCCodeEmitter:: 1626 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 1627 SmallVectorImpl<MCFixup> &Fixups, 1628 const MCSubtargetInfo &STI) const { 1629 // 10 bits. lower 5 bits are the lsb of the mask, high five bits are the 1630 // msb of the mask. 1631 const MCOperand &MO = MI.getOperand(Op); 1632 uint32_t v = ~MO.getImm(); 1633 uint32_t lsb = countTrailingZeros(v); 1634 uint32_t msb = (32 - countLeadingZeros (v)) - 1; 1635 assert(v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!"); 1636 return lsb | (msb << 5); 1637 } 1638 1639 unsigned ARMMCCodeEmitter:: 1640 getRegisterListOpValue(const MCInst &MI, unsigned Op, 1641 SmallVectorImpl<MCFixup> &Fixups, 1642 const MCSubtargetInfo &STI) const { 1643 // VLDM/VSTM/VSCCLRM: 1644 // {12-8} = Vd 1645 // {7-0} = Number of registers 1646 // 1647 // LDM/STM: 1648 // {15-0} = Bitfield of GPRs. 1649 unsigned Reg = MI.getOperand(Op).getReg(); 1650 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg); 1651 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg); 1652 bool CLRMRegs = MI.getOpcode() == ARM::t2CLRM; 1653 1654 unsigned Binary = 0; 1655 1656 if (SPRRegs || DPRRegs) { 1657 // VLDM/VSTM/VSCCLRM 1658 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); 1659 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff; 1660 Binary |= (RegNo & 0x1f) << 8; 1661 1662 // Ignore VPR 1663 if (MI.getOpcode() == ARM::VSCCLRMD || MI.getOpcode() == ARM::VSCCLRMS) 1664 --NumRegs; 1665 if (SPRRegs) 1666 Binary |= NumRegs; 1667 else 1668 Binary |= NumRegs * 2; 1669 } else { 1670 const MCRegisterInfo &MRI = *CTX.getRegisterInfo(); 1671 if (!CLRMRegs) { 1672 assert(std::is_sorted(MI.begin() + Op, MI.end(), 1673 [&](const MCOperand &LHS, const MCOperand &RHS) { 1674 return MRI.getEncodingValue(LHS.getReg()) < 1675 MRI.getEncodingValue(RHS.getReg()); 1676 })); 1677 } 1678 1679 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) { 1680 unsigned RegNo; 1681 if (CLRMRegs && MI.getOperand(I).getReg() == ARM::APSR) { 1682 RegNo = 15; 1683 } else { 1684 RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg()); 1685 } 1686 Binary |= 1 << RegNo; 1687 } 1688 } 1689 1690 return Binary; 1691 } 1692 1693 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along 1694 /// with the alignment operand. 1695 unsigned ARMMCCodeEmitter:: 1696 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 1697 SmallVectorImpl<MCFixup> &Fixups, 1698 const MCSubtargetInfo &STI) const { 1699 const MCOperand &Reg = MI.getOperand(Op); 1700 const MCOperand &Imm = MI.getOperand(Op + 1); 1701 1702 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg()); 1703 unsigned Align = 0; 1704 1705 switch (Imm.getImm()) { 1706 default: break; 1707 case 2: 1708 case 4: 1709 case 8: Align = 0x01; break; 1710 case 16: Align = 0x02; break; 1711 case 32: Align = 0x03; break; 1712 } 1713 1714 return RegNo | (Align << 4); 1715 } 1716 1717 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number 1718 /// along with the alignment operand for use in VST1 and VLD1 with size 32. 1719 unsigned ARMMCCodeEmitter:: 1720 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 1721 SmallVectorImpl<MCFixup> &Fixups, 1722 const MCSubtargetInfo &STI) const { 1723 const MCOperand &Reg = MI.getOperand(Op); 1724 const MCOperand &Imm = MI.getOperand(Op + 1); 1725 1726 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg()); 1727 unsigned Align = 0; 1728 1729 switch (Imm.getImm()) { 1730 default: break; 1731 case 8: 1732 case 16: 1733 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes. 1734 case 2: Align = 0x00; break; 1735 case 4: Align = 0x03; break; 1736 } 1737 1738 return RegNo | (Align << 4); 1739 } 1740 1741 1742 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and 1743 /// alignment operand for use in VLD-dup instructions. This is the same as 1744 /// getAddrMode6AddressOpValue except for the alignment encoding, which is 1745 /// different for VLD4-dup. 1746 unsigned ARMMCCodeEmitter:: 1747 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 1748 SmallVectorImpl<MCFixup> &Fixups, 1749 const MCSubtargetInfo &STI) const { 1750 const MCOperand &Reg = MI.getOperand(Op); 1751 const MCOperand &Imm = MI.getOperand(Op + 1); 1752 1753 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg()); 1754 unsigned Align = 0; 1755 1756 switch (Imm.getImm()) { 1757 default: break; 1758 case 2: 1759 case 4: 1760 case 8: Align = 0x01; break; 1761 case 16: Align = 0x03; break; 1762 } 1763 1764 return RegNo | (Align << 4); 1765 } 1766 1767 unsigned ARMMCCodeEmitter:: 1768 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 1769 SmallVectorImpl<MCFixup> &Fixups, 1770 const MCSubtargetInfo &STI) const { 1771 const MCOperand &MO = MI.getOperand(Op); 1772 if (MO.getReg() == 0) return 0x0D; 1773 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1774 } 1775 1776 unsigned ARMMCCodeEmitter:: 1777 getShiftRight8Imm(const MCInst &MI, unsigned Op, 1778 SmallVectorImpl<MCFixup> &Fixups, 1779 const MCSubtargetInfo &STI) const { 1780 return 8 - MI.getOperand(Op).getImm(); 1781 } 1782 1783 unsigned ARMMCCodeEmitter:: 1784 getShiftRight16Imm(const MCInst &MI, unsigned Op, 1785 SmallVectorImpl<MCFixup> &Fixups, 1786 const MCSubtargetInfo &STI) const { 1787 return 16 - MI.getOperand(Op).getImm(); 1788 } 1789 1790 unsigned ARMMCCodeEmitter:: 1791 getShiftRight32Imm(const MCInst &MI, unsigned Op, 1792 SmallVectorImpl<MCFixup> &Fixups, 1793 const MCSubtargetInfo &STI) const { 1794 return 32 - MI.getOperand(Op).getImm(); 1795 } 1796 1797 unsigned ARMMCCodeEmitter:: 1798 getShiftRight64Imm(const MCInst &MI, unsigned Op, 1799 SmallVectorImpl<MCFixup> &Fixups, 1800 const MCSubtargetInfo &STI) const { 1801 return 64 - MI.getOperand(Op).getImm(); 1802 } 1803 1804 void ARMMCCodeEmitter:: 1805 encodeInstruction(const MCInst &MI, raw_ostream &OS, 1806 SmallVectorImpl<MCFixup> &Fixups, 1807 const MCSubtargetInfo &STI) const { 1808 // Pseudo instructions don't get encoded. 1809 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 1810 uint64_t TSFlags = Desc.TSFlags; 1811 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo) 1812 return; 1813 1814 int Size; 1815 if (Desc.getSize() == 2 || Desc.getSize() == 4) 1816 Size = Desc.getSize(); 1817 else 1818 llvm_unreachable("Unexpected instruction size!"); 1819 1820 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI); 1821 // Thumb 32-bit wide instructions need to emit the high order halfword 1822 // first. 1823 if (isThumb(STI) && Size == 4) { 1824 EmitConstant(Binary >> 16, 2, OS); 1825 EmitConstant(Binary & 0xffff, 2, OS); 1826 } else 1827 EmitConstant(Binary, Size, OS); 1828 ++MCNumEmitted; // Keep track of the # of mi's emitted. 1829 } 1830 1831 template <bool isNeg, ARM::Fixups fixup> 1832 uint32_t 1833 ARMMCCodeEmitter::getBFTargetOpValue(const MCInst &MI, unsigned OpIdx, 1834 SmallVectorImpl<MCFixup> &Fixups, 1835 const MCSubtargetInfo &STI) const { 1836 const MCOperand MO = MI.getOperand(OpIdx); 1837 if (MO.isExpr()) 1838 return ::getBranchTargetOpValue(MI, OpIdx, fixup, Fixups, STI); 1839 return isNeg ? -(MO.getImm() >> 1) : (MO.getImm() >> 1); 1840 } 1841 1842 uint32_t 1843 ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx, 1844 SmallVectorImpl<MCFixup> &Fixups, 1845 const MCSubtargetInfo &STI) const { 1846 const MCOperand MO = MI.getOperand(OpIdx); 1847 const MCOperand BranchMO = MI.getOperand(0); 1848 1849 if (MO.isExpr()) { 1850 assert(BranchMO.isExpr()); 1851 const MCExpr *DiffExpr = MCBinaryExpr::createSub( 1852 MO.getExpr(), BranchMO.getExpr(), CTX); 1853 MCFixupKind Kind = MCFixupKind(ARM::fixup_bfcsel_else_target); 1854 Fixups.push_back(llvm::MCFixup::create(0, DiffExpr, Kind, MI.getLoc())); 1855 return 0; 1856 } 1857 1858 assert(MO.isImm() && BranchMO.isImm()); 1859 int Diff = MO.getImm() - BranchMO.getImm(); 1860 assert(Diff == 4 || Diff == 2); 1861 1862 return Diff == 4; 1863 } 1864 1865 uint32_t ARMMCCodeEmitter::getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx, 1866 SmallVectorImpl<MCFixup> &Fixups, 1867 const MCSubtargetInfo &STI)const { 1868 const MCOperand MO = MI.getOperand(OpIdx); 1869 assert(MO.isImm() && "Unexpected operand type!"); 1870 1871 int Value = MO.getImm(); 1872 int Imm = 0; 1873 1874 // VPT Masks are actually encoded as a series of invert/don't invert bits, 1875 // rather than true/false bits. 1876 unsigned PrevBit = 0; 1877 for (int i = 3; i >= 0; --i) { 1878 unsigned Bit = (Value >> i) & 1; 1879 1880 // Check if we are at the end of the mask. 1881 if ((Value & ~(~0U << i)) == 0) { 1882 Imm |= (1 << i); 1883 break; 1884 } 1885 1886 // Convert the bit in the mask based on the previous bit. 1887 if (Bit != PrevBit) 1888 Imm |= (1 << i); 1889 1890 PrevBit = Bit; 1891 } 1892 1893 return Imm; 1894 } 1895 1896 uint32_t ARMMCCodeEmitter::getRestrictedCondCodeOpValue( 1897 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, 1898 const MCSubtargetInfo &STI) const { 1899 1900 const MCOperand MO = MI.getOperand(OpIdx); 1901 assert(MO.isImm() && "Unexpected operand type!"); 1902 1903 switch (MO.getImm()) { 1904 default: 1905 assert(0 && "Unexpected Condition!"); 1906 return 0; 1907 case ARMCC::HS: 1908 case ARMCC::EQ: 1909 return 0; 1910 case ARMCC::HI: 1911 case ARMCC::NE: 1912 return 1; 1913 case ARMCC::GE: 1914 return 4; 1915 case ARMCC::LT: 1916 return 5; 1917 case ARMCC::GT: 1918 return 6; 1919 case ARMCC::LE: 1920 return 7; 1921 } 1922 } 1923 1924 uint32_t ARMMCCodeEmitter:: 1925 getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx, 1926 SmallVectorImpl<MCFixup> &Fixups, 1927 const MCSubtargetInfo &STI) const { 1928 const MCOperand &MO = MI.getOperand(OpIdx); 1929 assert(MO.isImm() && "Unexpected operand type!"); 1930 return countTrailingZeros((uint64_t)MO.getImm()); 1931 } 1932 1933 template <unsigned start> 1934 uint32_t ARMMCCodeEmitter:: 1935 getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx, 1936 SmallVectorImpl<MCFixup> &Fixups, 1937 const MCSubtargetInfo &STI) const { 1938 const MCOperand MO = MI.getOperand(OpIdx); 1939 assert(MO.isImm() && "Unexpected operand type!"); 1940 1941 int Value = MO.getImm(); 1942 return Value - start; 1943 } 1944 1945 #include "ARMGenMCCodeEmitter.inc" 1946 1947 MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII, 1948 const MCRegisterInfo &MRI, 1949 MCContext &Ctx) { 1950 return new ARMMCCodeEmitter(MCII, Ctx, true); 1951 } 1952 1953 MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII, 1954 const MCRegisterInfo &MRI, 1955 MCContext &Ctx) { 1956 return new ARMMCCodeEmitter(MCII, Ctx, false); 1957 } 1958