1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the ARMMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMFixupKinds.h"
16 #include "MCTargetDesc/ARMMCExpr.h"
17 #include "llvm/ADT/APFloat.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCFixup.h"
26 #include "llvm/MC/MCInst.h"
27 #include "llvm/MC/MCInstrDesc.h"
28 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/MC/MCSubtargetInfo.h"
31 #include "llvm/Support/Casting.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include <algorithm>
37 #include <cassert>
38 #include <cstdint>
39 #include <cstdlib>
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "mccodeemitter"
44 
45 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
46 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
47 
48 namespace {
49 
50 class ARMMCCodeEmitter : public MCCodeEmitter {
51   const MCInstrInfo &MCII;
52   MCContext &CTX;
53   bool IsLittleEndian;
54 
55 public:
56   ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle)
57     : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
58   }
59   ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete;
60   ARMMCCodeEmitter &operator=(const ARMMCCodeEmitter &) = delete;
61   ~ARMMCCodeEmitter() override = default;
62 
63   bool isThumb(const MCSubtargetInfo &STI) const {
64     return STI.getFeatureBits()[ARM::ModeThumb];
65   }
66 
67   bool isThumb2(const MCSubtargetInfo &STI) const {
68     return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
69   }
70 
71   bool isTargetMachO(const MCSubtargetInfo &STI) const {
72     const Triple &TT = STI.getTargetTriple();
73     return TT.isOSBinFormatMachO();
74   }
75 
76   unsigned getMachineSoImmOpValue(unsigned SoImm) const;
77 
78   // getBinaryCodeForInstr - TableGen'erated function for getting the
79   // binary encoding for an instruction.
80   uint64_t getBinaryCodeForInstr(const MCInst &MI,
81                                  SmallVectorImpl<MCFixup> &Fixups,
82                                  const MCSubtargetInfo &STI) const;
83 
84   /// getMachineOpValue - Return binary encoding of operand. If the machine
85   /// operand requires relocation, record the relocation and return zero.
86   unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
87                              SmallVectorImpl<MCFixup> &Fixups,
88                              const MCSubtargetInfo &STI) const;
89 
90   /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
91   /// the specified operand. This is used for operands with :lower16: and
92   /// :upper16: prefixes.
93   uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
94                                SmallVectorImpl<MCFixup> &Fixups,
95                                const MCSubtargetInfo &STI) const;
96 
97   bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
98                               unsigned &Reg, unsigned &Imm,
99                               SmallVectorImpl<MCFixup> &Fixups,
100                               const MCSubtargetInfo &STI) const;
101 
102   /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
103   /// BL branch target.
104   uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
105                                    SmallVectorImpl<MCFixup> &Fixups,
106                                    const MCSubtargetInfo &STI) const;
107 
108   /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
109   /// BLX branch target.
110   uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
111                                     SmallVectorImpl<MCFixup> &Fixups,
112                                     const MCSubtargetInfo &STI) const;
113 
114   /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
115   uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
116                                    SmallVectorImpl<MCFixup> &Fixups,
117                                    const MCSubtargetInfo &STI) const;
118 
119   /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
120   uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
121                                     SmallVectorImpl<MCFixup> &Fixups,
122                                     const MCSubtargetInfo &STI) const;
123 
124   /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
125   uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
126                                    SmallVectorImpl<MCFixup> &Fixups,
127                                    const MCSubtargetInfo &STI) const;
128 
129   /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
130   /// branch target.
131   uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
132                                   SmallVectorImpl<MCFixup> &Fixups,
133                                   const MCSubtargetInfo &STI) const;
134 
135   /// getThumbBranchTargetOpValue - Return encoding info for 24-bit
136   /// immediate Thumb2 direct branch target.
137   uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
138                                        SmallVectorImpl<MCFixup> &Fixups,
139                                        const MCSubtargetInfo &STI) const;
140 
141   /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
142   /// branch target.
143   uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
144                                      SmallVectorImpl<MCFixup> &Fixups,
145                                      const MCSubtargetInfo &STI) const;
146   uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
147                                  SmallVectorImpl<MCFixup> &Fixups,
148                                  const MCSubtargetInfo &STI) const;
149   uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
150                                   SmallVectorImpl<MCFixup> &Fixups,
151                                   const MCSubtargetInfo &STI) const;
152 
153   /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
154   /// ADR label target.
155   uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
156                               SmallVectorImpl<MCFixup> &Fixups,
157                               const MCSubtargetInfo &STI) const;
158   uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
159                               SmallVectorImpl<MCFixup> &Fixups,
160                               const MCSubtargetInfo &STI) const;
161   uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
162                               SmallVectorImpl<MCFixup> &Fixups,
163                               const MCSubtargetInfo &STI) const;
164 
165   uint32_t getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
166                             SmallVectorImpl<MCFixup> &Fixups,
167                             const MCSubtargetInfo &STI) const;
168 
169   /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
170   /// operand.
171   uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
172                                    SmallVectorImpl<MCFixup> &Fixups,
173                                    const MCSubtargetInfo &STI) const;
174 
175   /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
176   uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
177                                          SmallVectorImpl<MCFixup> &Fixups,
178                                          const MCSubtargetInfo &STI) const;
179 
180   /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
181   /// operand.
182   uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
183                                    SmallVectorImpl<MCFixup> &Fixups,
184                                    const MCSubtargetInfo &STI) const;
185 
186   /// getT2AddrModeImm7s4OpValue - Return encoding info for 'reg +/- imm7<<2'
187   /// operand.
188   uint32_t getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
189                                       SmallVectorImpl<MCFixup> &Fixups,
190                                       const MCSubtargetInfo &STI) const;
191 
192   /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
193   /// operand.
194   uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
195                                    SmallVectorImpl<MCFixup> &Fixups,
196                                    const MCSubtargetInfo &STI) const;
197 
198   /// getT2ScaledImmOpValue - Return encoding info for '+/- immX<<Y'
199   /// operand.
200   template<unsigned Bits, unsigned Shift>
201   uint32_t getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
202                                  SmallVectorImpl<MCFixup> &Fixups,
203                                  const MCSubtargetInfo &STI) const;
204 
205   /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
206   /// operand as needed by load/store instructions.
207   uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
208                                SmallVectorImpl<MCFixup> &Fixups,
209                                const MCSubtargetInfo &STI) const;
210 
211   /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
212   uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
213                                SmallVectorImpl<MCFixup> &Fixups,
214                                const MCSubtargetInfo &STI) const {
215     ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
216     switch (Mode) {
217     default: llvm_unreachable("Unknown addressing sub-mode!");
218     case ARM_AM::da: return 0;
219     case ARM_AM::ia: return 1;
220     case ARM_AM::db: return 2;
221     case ARM_AM::ib: return 3;
222     }
223   }
224 
225   /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
226   ///
227   unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
228     switch (ShOpc) {
229     case ARM_AM::no_shift:
230     case ARM_AM::lsl: return 0;
231     case ARM_AM::lsr: return 1;
232     case ARM_AM::asr: return 2;
233     case ARM_AM::ror:
234     case ARM_AM::rrx: return 3;
235     }
236     llvm_unreachable("Invalid ShiftOpc!");
237   }
238 
239   /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
240   uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
241                                      SmallVectorImpl<MCFixup> &Fixups,
242                                      const MCSubtargetInfo &STI) const;
243 
244   /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
245   uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
246                                 SmallVectorImpl<MCFixup> &Fixups,
247                                 const MCSubtargetInfo &STI) const;
248 
249   /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
250   uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
251                                      SmallVectorImpl<MCFixup> &Fixups,
252                                      const MCSubtargetInfo &STI) const;
253 
254   /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
255   uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
256                                SmallVectorImpl<MCFixup> &Fixups,
257                                const MCSubtargetInfo &STI) const;
258 
259   /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
260   /// operand.
261   uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
262                                      SmallVectorImpl<MCFixup> &Fixups,
263                                      const MCSubtargetInfo &STI) const;
264 
265   /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
266   uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
267                                 SmallVectorImpl<MCFixup> &Fixups,
268                                 const MCSubtargetInfo &STI) const;
269 
270   /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
271   uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
272                                 SmallVectorImpl<MCFixup> &Fixups,
273                                 const MCSubtargetInfo &STI) const;
274 
275   /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
276   uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
277                                SmallVectorImpl<MCFixup> &Fixups,
278                                const MCSubtargetInfo &STI) const;
279 
280   /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
281   uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
282                                SmallVectorImpl<MCFixup> &Fixups,
283                                const MCSubtargetInfo &STI) const;
284 
285   /// getCCOutOpValue - Return encoding of the 's' bit.
286   unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
287                            SmallVectorImpl<MCFixup> &Fixups,
288                            const MCSubtargetInfo &STI) const {
289     // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
290     // '1' respectively.
291     return MI.getOperand(Op).getReg() == ARM::CPSR;
292   }
293 
294   unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
295                             SmallVectorImpl<MCFixup> &Fixups,
296                             const MCSubtargetInfo &ST) const {
297     const MCOperand &MO = MI.getOperand(Op);
298 
299     // Support for fixups (MCFixup)
300     if (MO.isExpr()) {
301       const MCExpr *Expr = MO.getExpr();
302       // Fixups resolve to plain values that need to be encoded.
303       MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_mod_imm);
304       Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
305       return 0;
306     }
307 
308     // Immediate is already in its encoded format
309     return MO.getImm();
310   }
311 
312   /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
313   unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
314                            SmallVectorImpl<MCFixup> &Fixups,
315                            const MCSubtargetInfo &STI) const {
316     const MCOperand &MO = MI.getOperand(Op);
317 
318     // Support for fixups (MCFixup)
319     if (MO.isExpr()) {
320       const MCExpr *Expr = MO.getExpr();
321       // Fixups resolve to plain values that need to be encoded.
322       MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_so_imm);
323       Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
324       return 0;
325     }
326     unsigned SoImm = MO.getImm();
327     unsigned Encoded =  ARM_AM::getT2SOImmVal(SoImm);
328     assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
329     return Encoded;
330   }
331 
332   unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
333     SmallVectorImpl<MCFixup> &Fixups,
334     const MCSubtargetInfo &STI) const;
335   unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
336     SmallVectorImpl<MCFixup> &Fixups,
337     const MCSubtargetInfo &STI) const;
338   unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
339     SmallVectorImpl<MCFixup> &Fixups,
340     const MCSubtargetInfo &STI) const;
341 
342   /// getSORegOpValue - Return an encoded so_reg shifted register value.
343   unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
344                            SmallVectorImpl<MCFixup> &Fixups,
345                            const MCSubtargetInfo &STI) const;
346   unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
347                            SmallVectorImpl<MCFixup> &Fixups,
348                            const MCSubtargetInfo &STI) const;
349   unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
350                              SmallVectorImpl<MCFixup> &Fixups,
351                              const MCSubtargetInfo &STI) const;
352 
353   unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
354                                    SmallVectorImpl<MCFixup> &Fixups,
355                                    const MCSubtargetInfo &STI) const {
356     return 64 - MI.getOperand(Op).getImm();
357   }
358 
359   unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
360                                       SmallVectorImpl<MCFixup> &Fixups,
361                                       const MCSubtargetInfo &STI) const;
362 
363   unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
364                                   SmallVectorImpl<MCFixup> &Fixups,
365                                   const MCSubtargetInfo &STI) const;
366   unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
367                                       SmallVectorImpl<MCFixup> &Fixups,
368                                       const MCSubtargetInfo &STI) const;
369   unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
370                                         SmallVectorImpl<MCFixup> &Fixups,
371                                         const MCSubtargetInfo &STI) const;
372   unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
373                                         SmallVectorImpl<MCFixup> &Fixups,
374                                         const MCSubtargetInfo &STI) const;
375   unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
376                                      SmallVectorImpl<MCFixup> &Fixups,
377                                      const MCSubtargetInfo &STI) const;
378 
379   unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
380                              SmallVectorImpl<MCFixup> &Fixups,
381                              const MCSubtargetInfo &STI) const;
382   unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
383                               SmallVectorImpl<MCFixup> &Fixups,
384                               const MCSubtargetInfo &STI) const;
385   unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
386                               SmallVectorImpl<MCFixup> &Fixups,
387                               const MCSubtargetInfo &STI) const;
388   unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
389                               SmallVectorImpl<MCFixup> &Fixups,
390                               const MCSubtargetInfo &STI) const;
391 
392   unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
393                                  SmallVectorImpl<MCFixup> &Fixups,
394                                  const MCSubtargetInfo &STI) const;
395 
396   unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
397                                       unsigned EncodedValue,
398                                       const MCSubtargetInfo &STI) const;
399   unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
400                                           unsigned EncodedValue,
401                                           const MCSubtargetInfo &STI) const;
402   unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
403                                     unsigned EncodedValue,
404                                     const MCSubtargetInfo &STI) const;
405   unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
406                                    unsigned EncodedValue,
407                                    const MCSubtargetInfo &STI) const;
408 
409   unsigned VFPThumb2PostEncoder(const MCInst &MI,
410                                 unsigned EncodedValue,
411                                 const MCSubtargetInfo &STI) const;
412 
413   void EmitByte(unsigned char C, raw_ostream &OS) const {
414     OS << (char)C;
415   }
416 
417   void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
418     // Output the constant in little endian byte order.
419     for (unsigned i = 0; i != Size; ++i) {
420       unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
421       EmitByte((Val >> Shift) & 0xff, OS);
422     }
423   }
424 
425   void encodeInstruction(const MCInst &MI, raw_ostream &OS,
426                          SmallVectorImpl<MCFixup> &Fixups,
427                          const MCSubtargetInfo &STI) const override;
428 
429   template <bool isNeg, ARM::Fixups fixup>
430   uint32_t getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
431                               SmallVectorImpl<MCFixup> &Fixups,
432                               const MCSubtargetInfo &STI) const;
433 
434   uint32_t getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
435                                    SmallVectorImpl<MCFixup> &Fixups,
436                                    const MCSubtargetInfo &STI) const;
437 
438   uint32_t getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
439                              SmallVectorImpl<MCFixup> &Fixups,
440                              const MCSubtargetInfo &STI) const;
441   uint32_t getRestrictedCondCodeOpValue(const MCInst &MI, unsigned OpIdx,
442                                         SmallVectorImpl<MCFixup> &Fixups,
443                                         const MCSubtargetInfo &STI) const;
444 };
445 
446 } // end anonymous namespace
447 
448 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
449 /// instructions, and rewrite them to their Thumb2 form if we are currently in
450 /// Thumb2 mode.
451 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
452                                                  unsigned EncodedValue,
453                                                  const MCSubtargetInfo &STI) const {
454   if (isThumb2(STI)) {
455     // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
456     // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
457     // set to 1111.
458     unsigned Bit24 = EncodedValue & 0x01000000;
459     unsigned Bit28 = Bit24 << 4;
460     EncodedValue &= 0xEFFFFFFF;
461     EncodedValue |= Bit28;
462     EncodedValue |= 0x0F000000;
463   }
464 
465   return EncodedValue;
466 }
467 
468 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
469 /// instructions, and rewrite them to their Thumb2 form if we are currently in
470 /// Thumb2 mode.
471 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
472                                                  unsigned EncodedValue,
473                                                  const MCSubtargetInfo &STI) const {
474   if (isThumb2(STI)) {
475     EncodedValue &= 0xF0FFFFFF;
476     EncodedValue |= 0x09000000;
477   }
478 
479   return EncodedValue;
480 }
481 
482 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
483 /// instructions, and rewrite them to their Thumb2 form if we are currently in
484 /// Thumb2 mode.
485 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
486                                                  unsigned EncodedValue,
487                                                  const MCSubtargetInfo &STI) const {
488   if (isThumb2(STI)) {
489     EncodedValue &= 0x00FFFFFF;
490     EncodedValue |= 0xEE000000;
491   }
492 
493   return EncodedValue;
494 }
495 
496 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
497 /// if we are in Thumb2.
498 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
499                                                  unsigned EncodedValue,
500                                                  const MCSubtargetInfo &STI) const {
501   if (isThumb2(STI)) {
502     EncodedValue |= 0xC000000; // Set bits 27-26
503   }
504 
505   return EncodedValue;
506 }
507 
508 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
509 /// them to their Thumb2 form if we are currently in Thumb2 mode.
510 unsigned ARMMCCodeEmitter::
511 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
512                      const MCSubtargetInfo &STI) const {
513   if (isThumb2(STI)) {
514     EncodedValue &= 0x0FFFFFFF;
515     EncodedValue |= 0xE0000000;
516   }
517   return EncodedValue;
518 }
519 
520 /// getMachineOpValue - Return binary encoding of operand. If the machine
521 /// operand requires relocation, record the relocation and return zero.
522 unsigned ARMMCCodeEmitter::
523 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
524                   SmallVectorImpl<MCFixup> &Fixups,
525                   const MCSubtargetInfo &STI) const {
526   if (MO.isReg()) {
527     unsigned Reg = MO.getReg();
528     unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
529 
530     // In NEON, Q registers are encoded as 2x their register number,
531     // because they're using the same indices as the D registers they
532     // overlap. In MVE, there are no 64-bit vector instructions, so
533     // the encodings all refer to Q-registers by their literal
534     // register number.
535 
536     if (STI.getFeatureBits()[ARM::HasMVEIntegerOps])
537       return RegNo;
538 
539     switch (Reg) {
540     default:
541       return RegNo;
542     case ARM::Q0:  case ARM::Q1:  case ARM::Q2:  case ARM::Q3:
543     case ARM::Q4:  case ARM::Q5:  case ARM::Q6:  case ARM::Q7:
544     case ARM::Q8:  case ARM::Q9:  case ARM::Q10: case ARM::Q11:
545     case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
546       return 2 * RegNo;
547     }
548   } else if (MO.isImm()) {
549     return static_cast<unsigned>(MO.getImm());
550   } else if (MO.isFPImm()) {
551     return static_cast<unsigned>(APFloat(MO.getFPImm())
552                      .bitcastToAPInt().getHiBits(32).getLimitedValue());
553   }
554 
555   llvm_unreachable("Unable to encode MCOperand!");
556 }
557 
558 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
559 bool ARMMCCodeEmitter::
560 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
561                        unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
562                        const MCSubtargetInfo &STI) const {
563   const MCOperand &MO  = MI.getOperand(OpIdx);
564   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
565 
566   Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
567 
568   int32_t SImm = MO1.getImm();
569   bool isAdd = true;
570 
571   // Special value for #-0
572   if (SImm == INT32_MIN) {
573     SImm = 0;
574     isAdd = false;
575   }
576 
577   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
578   if (SImm < 0) {
579     SImm = -SImm;
580     isAdd = false;
581   }
582 
583   Imm = SImm;
584   return isAdd;
585 }
586 
587 /// getBranchTargetOpValue - Helper function to get the branch target operand,
588 /// which is either an immediate or requires a fixup.
589 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
590                                        unsigned FixupKind,
591                                        SmallVectorImpl<MCFixup> &Fixups,
592                                        const MCSubtargetInfo &STI) {
593   const MCOperand &MO = MI.getOperand(OpIdx);
594 
595   // If the destination is an immediate, we have nothing to do.
596   if (MO.isImm()) return MO.getImm();
597   assert(MO.isExpr() && "Unexpected branch target type!");
598   const MCExpr *Expr = MO.getExpr();
599   MCFixupKind Kind = MCFixupKind(FixupKind);
600   Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
601 
602   // All of the information is in the fixup.
603   return 0;
604 }
605 
606 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
607 // determined by negating them and XOR'ing them with bit 23.
608 static int32_t encodeThumbBLOffset(int32_t offset) {
609   offset >>= 1;
610   uint32_t S  = (offset & 0x800000) >> 23;
611   uint32_t J1 = (offset & 0x400000) >> 22;
612   uint32_t J2 = (offset & 0x200000) >> 21;
613   J1 = (~J1 & 0x1);
614   J2 = (~J2 & 0x1);
615   J1 ^= S;
616   J2 ^= S;
617 
618   offset &= ~0x600000;
619   offset |= J1 << 22;
620   offset |= J2 << 21;
621 
622   return offset;
623 }
624 
625 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
626 uint32_t ARMMCCodeEmitter::
627 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
628                         SmallVectorImpl<MCFixup> &Fixups,
629                         const MCSubtargetInfo &STI) const {
630   const MCOperand MO = MI.getOperand(OpIdx);
631   if (MO.isExpr())
632     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
633                                     Fixups, STI);
634   return encodeThumbBLOffset(MO.getImm());
635 }
636 
637 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
638 /// BLX branch target.
639 uint32_t ARMMCCodeEmitter::
640 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
641                          SmallVectorImpl<MCFixup> &Fixups,
642                          const MCSubtargetInfo &STI) const {
643   const MCOperand MO = MI.getOperand(OpIdx);
644   if (MO.isExpr())
645     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
646                                     Fixups, STI);
647   return encodeThumbBLOffset(MO.getImm());
648 }
649 
650 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
651 uint32_t ARMMCCodeEmitter::
652 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
653                         SmallVectorImpl<MCFixup> &Fixups,
654                         const MCSubtargetInfo &STI) const {
655   const MCOperand MO = MI.getOperand(OpIdx);
656   if (MO.isExpr())
657     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
658                                     Fixups, STI);
659   return (MO.getImm() >> 1);
660 }
661 
662 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
663 uint32_t ARMMCCodeEmitter::
664 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
665                          SmallVectorImpl<MCFixup> &Fixups,
666                          const MCSubtargetInfo &STI) const {
667   const MCOperand MO = MI.getOperand(OpIdx);
668   if (MO.isExpr())
669     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
670                                     Fixups, STI);
671   return (MO.getImm() >> 1);
672 }
673 
674 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
675 uint32_t ARMMCCodeEmitter::
676 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
677                         SmallVectorImpl<MCFixup> &Fixups,
678                         const MCSubtargetInfo &STI) const {
679   const MCOperand MO = MI.getOperand(OpIdx);
680   if (MO.isExpr())
681     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI);
682   return (MO.getImm() >> 1);
683 }
684 
685 /// Return true if this branch has a non-always predication
686 static bool HasConditionalBranch(const MCInst &MI) {
687   int NumOp = MI.getNumOperands();
688   if (NumOp >= 2) {
689     for (int i = 0; i < NumOp-1; ++i) {
690       const MCOperand &MCOp1 = MI.getOperand(i);
691       const MCOperand &MCOp2 = MI.getOperand(i + 1);
692       if (MCOp1.isImm() && MCOp2.isReg() &&
693           (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
694         if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
695           return true;
696       }
697     }
698   }
699   return false;
700 }
701 
702 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
703 /// target.
704 uint32_t ARMMCCodeEmitter::
705 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
706                        SmallVectorImpl<MCFixup> &Fixups,
707                        const MCSubtargetInfo &STI) const {
708   // FIXME: This really, really shouldn't use TargetMachine. We don't want
709   // coupling between MC and TM anywhere we can help it.
710   if (isThumb2(STI))
711     return
712       ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI);
713   return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
714 }
715 
716 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
717 /// target.
718 uint32_t ARMMCCodeEmitter::
719 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
720                           SmallVectorImpl<MCFixup> &Fixups,
721                           const MCSubtargetInfo &STI) const {
722   const MCOperand MO = MI.getOperand(OpIdx);
723   if (MO.isExpr()) {
724     if (HasConditionalBranch(MI))
725       return ::getBranchTargetOpValue(MI, OpIdx,
726                                       ARM::fixup_arm_condbranch, Fixups, STI);
727     return ::getBranchTargetOpValue(MI, OpIdx,
728                                     ARM::fixup_arm_uncondbranch, Fixups, STI);
729   }
730 
731   return MO.getImm() >> 2;
732 }
733 
734 uint32_t ARMMCCodeEmitter::
735 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
736                           SmallVectorImpl<MCFixup> &Fixups,
737                           const MCSubtargetInfo &STI) const {
738   const MCOperand MO = MI.getOperand(OpIdx);
739   if (MO.isExpr()) {
740     if (HasConditionalBranch(MI))
741       return ::getBranchTargetOpValue(MI, OpIdx,
742                                       ARM::fixup_arm_condbl, Fixups, STI);
743     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI);
744   }
745 
746   return MO.getImm() >> 2;
747 }
748 
749 uint32_t ARMMCCodeEmitter::
750 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
751                           SmallVectorImpl<MCFixup> &Fixups,
752                           const MCSubtargetInfo &STI) const {
753   const MCOperand MO = MI.getOperand(OpIdx);
754   if (MO.isExpr())
755     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI);
756 
757   return MO.getImm() >> 1;
758 }
759 
760 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
761 /// immediate branch target.
762 uint32_t ARMMCCodeEmitter::getThumbBranchTargetOpValue(
763     const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
764     const MCSubtargetInfo &STI) const {
765   unsigned Val = 0;
766   const MCOperand MO = MI.getOperand(OpIdx);
767 
768   if(MO.isExpr())
769     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI);
770   else
771     Val = MO.getImm() >> 1;
772 
773   bool I  = (Val & 0x800000);
774   bool J1 = (Val & 0x400000);
775   bool J2 = (Val & 0x200000);
776   if (I ^ J1)
777     Val &= ~0x400000;
778   else
779     Val |= 0x400000;
780 
781   if (I ^ J2)
782     Val &= ~0x200000;
783   else
784     Val |= 0x200000;
785 
786   return Val;
787 }
788 
789 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
790 /// ADR label target.
791 uint32_t ARMMCCodeEmitter::
792 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
793                    SmallVectorImpl<MCFixup> &Fixups,
794                    const MCSubtargetInfo &STI) const {
795   const MCOperand MO = MI.getOperand(OpIdx);
796   if (MO.isExpr())
797     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
798                                     Fixups, STI);
799   int64_t offset = MO.getImm();
800   uint32_t Val = 0x2000;
801 
802   int SoImmVal;
803   if (offset == INT32_MIN) {
804     Val = 0x1000;
805     SoImmVal = 0;
806   } else if (offset < 0) {
807     Val = 0x1000;
808     offset *= -1;
809     SoImmVal = ARM_AM::getSOImmVal(offset);
810     if(SoImmVal == -1) {
811       Val = 0x2000;
812       offset *= -1;
813       SoImmVal = ARM_AM::getSOImmVal(offset);
814     }
815   } else {
816     SoImmVal = ARM_AM::getSOImmVal(offset);
817     if(SoImmVal == -1) {
818       Val = 0x1000;
819       offset *= -1;
820       SoImmVal = ARM_AM::getSOImmVal(offset);
821     }
822   }
823 
824   assert(SoImmVal != -1 && "Not a valid so_imm value!");
825 
826   Val |= SoImmVal;
827   return Val;
828 }
829 
830 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
831 /// target.
832 uint32_t ARMMCCodeEmitter::
833 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
834                    SmallVectorImpl<MCFixup> &Fixups,
835                    const MCSubtargetInfo &STI) const {
836   const MCOperand MO = MI.getOperand(OpIdx);
837   if (MO.isExpr())
838     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
839                                     Fixups, STI);
840   int32_t Val = MO.getImm();
841   if (Val == INT32_MIN)
842     Val = 0x1000;
843   else if (Val < 0) {
844     Val *= -1;
845     Val |= 0x1000;
846   }
847   return Val;
848 }
849 
850 /// getITMaskOpValue - Return the architectural encoding of an IT
851 /// predication mask, given the MCOperand format.
852 uint32_t ARMMCCodeEmitter::
853 getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
854                  SmallVectorImpl<MCFixup> &Fixups,
855                  const MCSubtargetInfo &STI) const {
856   const MCOperand MaskMO = MI.getOperand(OpIdx);
857   assert(MaskMO.isImm() && "Unexpected operand type!");
858 
859   unsigned Mask = MaskMO.getImm();
860 
861   // IT masks are encoded as a sequence of replacement low-order bits
862   // for the condition code. So if the low bit of the starting
863   // condition code is 1, then we have to flip all the bits above the
864   // terminating bit (which is the lowest 1 bit).
865   assert(OpIdx > 0 && "IT mask appears first!");
866   const MCOperand CondMO = MI.getOperand(OpIdx-1);
867   assert(CondMO.isImm() && "Unexpected operand type!");
868   if (CondMO.getImm() & 1) {
869     unsigned LowBit = Mask & -Mask;
870     unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
871     Mask ^= BitsAboveLowBit;
872   }
873 
874   return Mask;
875 }
876 
877 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
878 /// target.
879 uint32_t ARMMCCodeEmitter::
880 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
881                    SmallVectorImpl<MCFixup> &Fixups,
882                    const MCSubtargetInfo &STI) const {
883   const MCOperand MO = MI.getOperand(OpIdx);
884   if (MO.isExpr())
885     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
886                                     Fixups, STI);
887   return MO.getImm();
888 }
889 
890 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
891 /// operand.
892 uint32_t ARMMCCodeEmitter::
893 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
894                               SmallVectorImpl<MCFixup> &,
895                               const MCSubtargetInfo &STI) const {
896   // [Rn, Rm]
897   //   {5-3} = Rm
898   //   {2-0} = Rn
899   const MCOperand &MO1 = MI.getOperand(OpIdx);
900   const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
901   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
902   unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
903   return (Rm << 3) | Rn;
904 }
905 
906 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
907 uint32_t ARMMCCodeEmitter::
908 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
909                         SmallVectorImpl<MCFixup> &Fixups,
910                         const MCSubtargetInfo &STI) const {
911   // {17-13} = reg
912   // {12}    = (U)nsigned (add == '1', sub == '0')
913   // {11-0}  = imm12
914   unsigned Reg, Imm12;
915   bool isAdd = true;
916   // If The first operand isn't a register, we have a label reference.
917   const MCOperand &MO = MI.getOperand(OpIdx);
918   if (!MO.isReg()) {
919     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
920     Imm12 = 0;
921 
922     if (MO.isExpr()) {
923       const MCExpr *Expr = MO.getExpr();
924       isAdd = false ; // 'U' bit is set as part of the fixup.
925 
926       MCFixupKind Kind;
927       if (isThumb2(STI))
928         Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
929       else
930         Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
931       Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
932 
933       ++MCNumCPRelocations;
934     } else {
935       Reg = ARM::PC;
936       int32_t Offset = MO.getImm();
937       if (Offset == INT32_MIN) {
938         Offset = 0;
939         isAdd = false;
940       } else if (Offset < 0) {
941         Offset *= -1;
942         isAdd = false;
943       }
944       Imm12 = Offset;
945     }
946   } else
947     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
948 
949   uint32_t Binary = Imm12 & 0xfff;
950   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
951   if (isAdd)
952     Binary |= (1 << 12);
953   Binary |= (Reg << 13);
954   return Binary;
955 }
956 
957 template<unsigned Bits, unsigned Shift>
958 uint32_t ARMMCCodeEmitter::
959 getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
960                       SmallVectorImpl<MCFixup> &Fixups,
961                       const MCSubtargetInfo &STI) const {
962   // FIXME: The immediate operand should have already been encoded like this
963   // before ever getting here. The encoder method should just need to combine
964   // the MI operands for the register and the offset into a single
965   // representation for the complex operand in the .td file. This isn't just
966   // style, unfortunately. As-is, we can't represent the distinct encoding
967   // for #-0.
968 
969   // {Bits}    = (U)nsigned (add == '1', sub == '0')
970   // {(Bits-1)-0}  = immediate
971   int32_t Imm = MI.getOperand(OpIdx).getImm();
972   bool isAdd = Imm >= 0;
973 
974   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
975   if (Imm < 0)
976     Imm = -(uint32_t)Imm;
977 
978   Imm >>= Shift;
979 
980   uint32_t Binary = Imm & ((1U << Bits) - 1);
981   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
982   if (isAdd)
983     Binary |= (1U << Bits);
984   return Binary;
985 }
986 /// getT2AddrModeImm8s4OpValue - Return encoding info for
987 /// 'reg +/- imm8<<2' operand.
988 uint32_t ARMMCCodeEmitter::
989 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
990                         SmallVectorImpl<MCFixup> &Fixups,
991                         const MCSubtargetInfo &STI) const {
992   // {12-9} = reg
993   // {8}    = (U)nsigned (add == '1', sub == '0')
994   // {7-0}  = imm8
995   unsigned Reg, Imm8;
996   bool isAdd = true;
997   // If The first operand isn't a register, we have a label reference.
998   const MCOperand &MO = MI.getOperand(OpIdx);
999   if (!MO.isReg()) {
1000     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1001     Imm8 = 0;
1002     isAdd = false ; // 'U' bit is set as part of the fixup.
1003 
1004     assert(MO.isExpr() && "Unexpected machine operand type!");
1005     const MCExpr *Expr = MO.getExpr();
1006     MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1007     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1008 
1009     ++MCNumCPRelocations;
1010   } else
1011     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1012 
1013   // FIXME: The immediate operand should have already been encoded like this
1014   // before ever getting here. The encoder method should just need to combine
1015   // the MI operands for the register and the offset into a single
1016   // representation for the complex operand in the .td file. This isn't just
1017   // style, unfortunately. As-is, we can't represent the distinct encoding
1018   // for #-0.
1019   uint32_t Binary = (Imm8 >> 2) & 0xff;
1020   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1021   if (isAdd)
1022     Binary |= (1 << 8);
1023   Binary |= (Reg << 9);
1024   return Binary;
1025 }
1026 
1027 /// getT2AddrModeImm7s4OpValue - Return encoding info for
1028 /// 'reg +/- imm7<<2' operand.
1029 uint32_t
1030 ARMMCCodeEmitter::getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
1031                                              SmallVectorImpl<MCFixup> &Fixups,
1032                                              const MCSubtargetInfo &STI) const {
1033   // {11-8} = reg
1034   // {7}    = (A)dd (add == '1', sub == '0')
1035   // {6-0}  = imm7
1036   unsigned Reg, Imm7;
1037   // If The first operand isn't a register, we have a label reference.
1038   bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm7, Fixups, STI);
1039 
1040   // FIXME: The immediate operand should have already been encoded like this
1041   // before ever getting here. The encoder method should just need to combine
1042   // the MI operands for the register and the offset into a single
1043   // representation for the complex operand in the .td file. This isn't just
1044   // style, unfortunately. As-is, we can't represent the distinct encoding
1045   // for #-0.
1046   uint32_t Binary = (Imm7 >> 2) & 0xff;
1047   // Immediate is always encoded as positive. The 'A' bit controls add vs sub.
1048   if (isAdd)
1049     Binary |= (1 << 7);
1050   Binary |= (Reg << 8);
1051   return Binary;
1052 }
1053 
1054 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
1055 /// 'reg + imm8<<2' operand.
1056 uint32_t ARMMCCodeEmitter::
1057 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
1058                         SmallVectorImpl<MCFixup> &Fixups,
1059                         const MCSubtargetInfo &STI) const {
1060   // {11-8} = reg
1061   // {7-0}  = imm8
1062   const MCOperand &MO = MI.getOperand(OpIdx);
1063   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1064   unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1065   unsigned Imm8 = MO1.getImm();
1066   return (Reg << 8) | Imm8;
1067 }
1068 
1069 uint32_t
1070 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
1071                                       SmallVectorImpl<MCFixup> &Fixups,
1072                                       const MCSubtargetInfo &STI) const {
1073   // {20-16} = imm{15-12}
1074   // {11-0}  = imm{11-0}
1075   const MCOperand &MO = MI.getOperand(OpIdx);
1076   if (MO.isImm())
1077     // Hi / lo 16 bits already extracted during earlier passes.
1078     return static_cast<unsigned>(MO.getImm());
1079 
1080   // Handle :upper16: and :lower16: assembly prefixes.
1081   const MCExpr *E = MO.getExpr();
1082   MCFixupKind Kind;
1083   if (E->getKind() == MCExpr::Target) {
1084     const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
1085     E = ARM16Expr->getSubExpr();
1086 
1087     if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) {
1088       const int64_t Value = MCE->getValue();
1089       if (Value > UINT32_MAX)
1090         report_fatal_error("constant value truncated (limited to 32-bit)");
1091 
1092       switch (ARM16Expr->getKind()) {
1093       case ARMMCExpr::VK_ARM_HI16:
1094         return (int32_t(Value) & 0xffff0000) >> 16;
1095       case ARMMCExpr::VK_ARM_LO16:
1096         return (int32_t(Value) & 0x0000ffff);
1097       default: llvm_unreachable("Unsupported ARMFixup");
1098       }
1099     }
1100 
1101     switch (ARM16Expr->getKind()) {
1102     default: llvm_unreachable("Unsupported ARMFixup");
1103     case ARMMCExpr::VK_ARM_HI16:
1104       Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movt_hi16
1105                                       : ARM::fixup_arm_movt_hi16);
1106       break;
1107     case ARMMCExpr::VK_ARM_LO16:
1108       Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movw_lo16
1109                                       : ARM::fixup_arm_movw_lo16);
1110       break;
1111     }
1112 
1113     Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc()));
1114     return 0;
1115   }
1116   // If the expression doesn't have :upper16: or :lower16: on it,
1117   // it's just a plain immediate expression, previously those evaluated to
1118   // the lower 16 bits of the expression regardless of whether
1119   // we have a movt or a movw, but that led to misleadingly results.
1120   // This is disallowed in the AsmParser in validateInstruction()
1121   // so this should never happen.
1122   llvm_unreachable("expression without :upper16: or :lower16:");
1123 }
1124 
1125 uint32_t ARMMCCodeEmitter::
1126 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1127                     SmallVectorImpl<MCFixup> &Fixups,
1128                     const MCSubtargetInfo &STI) const {
1129   const MCOperand &MO = MI.getOperand(OpIdx);
1130   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1131   const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1132   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1133   unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1134   unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
1135   bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
1136   ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
1137   unsigned SBits = getShiftOp(ShOp);
1138 
1139   // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1140   // amount. However, it would be an easy mistake to make so check here.
1141   assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
1142 
1143   // {16-13} = Rn
1144   // {12}    = isAdd
1145   // {11-0}  = shifter
1146   //  {3-0}  = Rm
1147   //  {4}    = 0
1148   //  {6-5}  = type
1149   //  {11-7} = imm
1150   uint32_t Binary = Rm;
1151   Binary |= Rn << 13;
1152   Binary |= SBits << 5;
1153   Binary |= ShImm << 7;
1154   if (isAdd)
1155     Binary |= 1 << 12;
1156   return Binary;
1157 }
1158 
1159 uint32_t ARMMCCodeEmitter::
1160 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1161                           SmallVectorImpl<MCFixup> &Fixups,
1162                           const MCSubtargetInfo &STI) const {
1163   // {13}     1 == imm12, 0 == Rm
1164   // {12}     isAdd
1165   // {11-0}   imm12/Rm
1166   const MCOperand &MO = MI.getOperand(OpIdx);
1167   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1168   unsigned Imm = MO1.getImm();
1169   bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1170   bool isReg = MO.getReg() != 0;
1171   uint32_t Binary = ARM_AM::getAM2Offset(Imm);
1172   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
1173   if (isReg) {
1174     ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
1175     Binary <<= 7;                    // Shift amount is bits [11:7]
1176     Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1177     Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1178   }
1179   return Binary | (isAdd << 12) | (isReg << 13);
1180 }
1181 
1182 uint32_t ARMMCCodeEmitter::
1183 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1184                      SmallVectorImpl<MCFixup> &Fixups,
1185                      const MCSubtargetInfo &STI) const {
1186   // {4}      isAdd
1187   // {3-0}    Rm
1188   const MCOperand &MO = MI.getOperand(OpIdx);
1189   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1190   bool isAdd = MO1.getImm() != 0;
1191   return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
1192 }
1193 
1194 uint32_t ARMMCCodeEmitter::
1195 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1196                           SmallVectorImpl<MCFixup> &Fixups,
1197                           const MCSubtargetInfo &STI) const {
1198   // {9}      1 == imm8, 0 == Rm
1199   // {8}      isAdd
1200   // {7-4}    imm7_4/zero
1201   // {3-0}    imm3_0/Rm
1202   const MCOperand &MO = MI.getOperand(OpIdx);
1203   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1204   unsigned Imm = MO1.getImm();
1205   bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1206   bool isImm = MO.getReg() == 0;
1207   uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1208   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1209   if (!isImm)
1210     Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1211   return Imm8 | (isAdd << 8) | (isImm << 9);
1212 }
1213 
1214 uint32_t ARMMCCodeEmitter::
1215 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1216                     SmallVectorImpl<MCFixup> &Fixups,
1217                     const MCSubtargetInfo &STI) const {
1218   // {13}     1 == imm8, 0 == Rm
1219   // {12-9}   Rn
1220   // {8}      isAdd
1221   // {7-4}    imm7_4/zero
1222   // {3-0}    imm3_0/Rm
1223   const MCOperand &MO = MI.getOperand(OpIdx);
1224   const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1225   const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1226 
1227   // If The first operand isn't a register, we have a label reference.
1228   if (!MO.isReg()) {
1229     unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1230 
1231     assert(MO.isExpr() && "Unexpected machine operand type!");
1232     const MCExpr *Expr = MO.getExpr();
1233     MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1234     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1235 
1236     ++MCNumCPRelocations;
1237     return (Rn << 9) | (1 << 13);
1238   }
1239   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1240   unsigned Imm = MO2.getImm();
1241   bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1242   bool isImm = MO1.getReg() == 0;
1243   uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1244   // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1245   if (!isImm)
1246     Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1247   return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1248 }
1249 
1250 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1251 uint32_t ARMMCCodeEmitter::
1252 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1253                           SmallVectorImpl<MCFixup> &Fixups,
1254                           const MCSubtargetInfo &STI) const {
1255   // [SP, #imm]
1256   //   {7-0} = imm8
1257   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1258   assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1259          "Unexpected base register!");
1260 
1261   // The immediate is already shifted for the implicit zeroes, so no change
1262   // here.
1263   return MO1.getImm() & 0xff;
1264 }
1265 
1266 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1267 uint32_t ARMMCCodeEmitter::
1268 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1269                      SmallVectorImpl<MCFixup> &Fixups,
1270                      const MCSubtargetInfo &STI) const {
1271   // [Rn, #imm]
1272   //   {7-3} = imm5
1273   //   {2-0} = Rn
1274   const MCOperand &MO = MI.getOperand(OpIdx);
1275   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1276   unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1277   unsigned Imm5 = MO1.getImm();
1278   return ((Imm5 & 0x1f) << 3) | Rn;
1279 }
1280 
1281 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1282 uint32_t ARMMCCodeEmitter::
1283 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1284                      SmallVectorImpl<MCFixup> &Fixups,
1285                      const MCSubtargetInfo &STI) const {
1286   const MCOperand MO = MI.getOperand(OpIdx);
1287   if (MO.isExpr())
1288     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI);
1289   return (MO.getImm() >> 2);
1290 }
1291 
1292 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
1293 uint32_t ARMMCCodeEmitter::
1294 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1295                     SmallVectorImpl<MCFixup> &Fixups,
1296                     const MCSubtargetInfo &STI) const {
1297   // {12-9} = reg
1298   // {8}    = (U)nsigned (add == '1', sub == '0')
1299   // {7-0}  = imm8
1300   unsigned Reg, Imm8;
1301   bool isAdd;
1302   // If The first operand isn't a register, we have a label reference.
1303   const MCOperand &MO = MI.getOperand(OpIdx);
1304   if (!MO.isReg()) {
1305     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1306     Imm8 = 0;
1307     isAdd = false; // 'U' bit is handled as part of the fixup.
1308 
1309     assert(MO.isExpr() && "Unexpected machine operand type!");
1310     const MCExpr *Expr = MO.getExpr();
1311     MCFixupKind Kind;
1312     if (isThumb2(STI))
1313       Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1314     else
1315       Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1316     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1317 
1318     ++MCNumCPRelocations;
1319   } else {
1320     EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1321     isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1322   }
1323 
1324   uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1325   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1326   if (isAdd)
1327     Binary |= (1 << 8);
1328   Binary |= (Reg << 9);
1329   return Binary;
1330 }
1331 
1332 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
1333 uint32_t ARMMCCodeEmitter::
1334 getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
1335                     SmallVectorImpl<MCFixup> &Fixups,
1336                     const MCSubtargetInfo &STI) const {
1337   // {12-9} = reg
1338   // {8}    = (U)nsigned (add == '1', sub == '0')
1339   // {7-0}  = imm8
1340   unsigned Reg, Imm8;
1341   bool isAdd;
1342   // If The first operand isn't a register, we have a label reference.
1343   const MCOperand &MO = MI.getOperand(OpIdx);
1344   if (!MO.isReg()) {
1345     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1346     Imm8 = 0;
1347     isAdd = false; // 'U' bit is handled as part of the fixup.
1348 
1349     assert(MO.isExpr() && "Unexpected machine operand type!");
1350     const MCExpr *Expr = MO.getExpr();
1351     MCFixupKind Kind;
1352     if (isThumb2(STI))
1353       Kind = MCFixupKind(ARM::fixup_t2_pcrel_9);
1354     else
1355       Kind = MCFixupKind(ARM::fixup_arm_pcrel_9);
1356     Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1357 
1358     ++MCNumCPRelocations;
1359   } else {
1360     EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1361     isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1362   }
1363 
1364   uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1365   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1366   if (isAdd)
1367     Binary |= (1 << 8);
1368   Binary |= (Reg << 9);
1369   return Binary;
1370 }
1371 
1372 unsigned ARMMCCodeEmitter::
1373 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1374                 SmallVectorImpl<MCFixup> &Fixups,
1375                 const MCSubtargetInfo &STI) const {
1376   // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1377   // shifted. The second is Rs, the amount to shift by, and the third specifies
1378   // the type of the shift.
1379   //
1380   // {3-0} = Rm.
1381   // {4}   = 1
1382   // {6-5} = type
1383   // {11-8} = Rs
1384   // {7}    = 0
1385 
1386   const MCOperand &MO  = MI.getOperand(OpIdx);
1387   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1388   const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1389   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1390 
1391   // Encode Rm.
1392   unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1393 
1394   // Encode the shift opcode.
1395   unsigned SBits = 0;
1396   unsigned Rs = MO1.getReg();
1397   if (Rs) {
1398     // Set shift operand (bit[7:4]).
1399     // LSL - 0001
1400     // LSR - 0011
1401     // ASR - 0101
1402     // ROR - 0111
1403     switch (SOpc) {
1404     default: llvm_unreachable("Unknown shift opc!");
1405     case ARM_AM::lsl: SBits = 0x1; break;
1406     case ARM_AM::lsr: SBits = 0x3; break;
1407     case ARM_AM::asr: SBits = 0x5; break;
1408     case ARM_AM::ror: SBits = 0x7; break;
1409     }
1410   }
1411 
1412   Binary |= SBits << 4;
1413 
1414   // Encode the shift operation Rs.
1415   // Encode Rs bit[11:8].
1416   assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1417   return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
1418 }
1419 
1420 unsigned ARMMCCodeEmitter::
1421 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1422                 SmallVectorImpl<MCFixup> &Fixups,
1423                 const MCSubtargetInfo &STI) const {
1424   // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1425   // shifted. The second is the amount to shift by.
1426   //
1427   // {3-0} = Rm.
1428   // {4}   = 0
1429   // {6-5} = type
1430   // {11-7} = imm
1431 
1432   const MCOperand &MO  = MI.getOperand(OpIdx);
1433   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1434   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1435 
1436   // Encode Rm.
1437   unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1438 
1439   // Encode the shift opcode.
1440   unsigned SBits = 0;
1441 
1442   // Set shift operand (bit[6:4]).
1443   // LSL - 000
1444   // LSR - 010
1445   // ASR - 100
1446   // ROR - 110
1447   // RRX - 110 and bit[11:8] clear.
1448   switch (SOpc) {
1449   default: llvm_unreachable("Unknown shift opc!");
1450   case ARM_AM::lsl: SBits = 0x0; break;
1451   case ARM_AM::lsr: SBits = 0x2; break;
1452   case ARM_AM::asr: SBits = 0x4; break;
1453   case ARM_AM::ror: SBits = 0x6; break;
1454   case ARM_AM::rrx:
1455     Binary |= 0x60;
1456     return Binary;
1457   }
1458 
1459   // Encode shift_imm bit[11:7].
1460   Binary |= SBits << 4;
1461   unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1462   assert(Offset < 32 && "Offset must be in range 0-31!");
1463   return Binary | (Offset << 7);
1464 }
1465 
1466 
1467 unsigned ARMMCCodeEmitter::
1468 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1469                 SmallVectorImpl<MCFixup> &Fixups,
1470                 const MCSubtargetInfo &STI) const {
1471   const MCOperand &MO1 = MI.getOperand(OpNum);
1472   const MCOperand &MO2 = MI.getOperand(OpNum+1);
1473   const MCOperand &MO3 = MI.getOperand(OpNum+2);
1474 
1475   // Encoded as [Rn, Rm, imm].
1476   // FIXME: Needs fixup support.
1477   unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1478   Value <<= 4;
1479   Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1480   Value <<= 2;
1481   Value |= MO3.getImm();
1482 
1483   return Value;
1484 }
1485 
1486 unsigned ARMMCCodeEmitter::
1487 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1488                          SmallVectorImpl<MCFixup> &Fixups,
1489                          const MCSubtargetInfo &STI) const {
1490   const MCOperand &MO1 = MI.getOperand(OpNum);
1491   const MCOperand &MO2 = MI.getOperand(OpNum+1);
1492 
1493   // FIXME: Needs fixup support.
1494   unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1495 
1496   // Even though the immediate is 8 bits long, we need 9 bits in order
1497   // to represent the (inverse of the) sign bit.
1498   Value <<= 9;
1499   int32_t tmp = (int32_t)MO2.getImm();
1500   if (tmp < 0)
1501     tmp = abs(tmp);
1502   else
1503     Value |= 256; // Set the ADD bit
1504   Value |= tmp & 255;
1505   return Value;
1506 }
1507 
1508 unsigned ARMMCCodeEmitter::
1509 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1510                          SmallVectorImpl<MCFixup> &Fixups,
1511                          const MCSubtargetInfo &STI) const {
1512   const MCOperand &MO1 = MI.getOperand(OpNum);
1513 
1514   // FIXME: Needs fixup support.
1515   unsigned Value = 0;
1516   int32_t tmp = (int32_t)MO1.getImm();
1517   if (tmp < 0)
1518     tmp = abs(tmp);
1519   else
1520     Value |= 256; // Set the ADD bit
1521   Value |= tmp & 255;
1522   return Value;
1523 }
1524 
1525 unsigned ARMMCCodeEmitter::
1526 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1527                 SmallVectorImpl<MCFixup> &Fixups,
1528                 const MCSubtargetInfo &STI) const {
1529   // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1530   // shifted. The second is the amount to shift by.
1531   //
1532   // {3-0} = Rm.
1533   // {4}   = 0
1534   // {6-5} = type
1535   // {11-7} = imm
1536 
1537   const MCOperand &MO  = MI.getOperand(OpIdx);
1538   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1539   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1540 
1541   // Encode Rm.
1542   unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1543 
1544   // Encode the shift opcode.
1545   unsigned SBits = 0;
1546   // Set shift operand (bit[6:4]).
1547   // LSL - 000
1548   // LSR - 010
1549   // ASR - 100
1550   // ROR - 110
1551   switch (SOpc) {
1552   default: llvm_unreachable("Unknown shift opc!");
1553   case ARM_AM::lsl: SBits = 0x0; break;
1554   case ARM_AM::lsr: SBits = 0x2; break;
1555   case ARM_AM::asr: SBits = 0x4; break;
1556   case ARM_AM::rrx: LLVM_FALLTHROUGH;
1557   case ARM_AM::ror: SBits = 0x6; break;
1558   }
1559 
1560   Binary |= SBits << 4;
1561   if (SOpc == ARM_AM::rrx)
1562     return Binary;
1563 
1564   // Encode shift_imm bit[11:7].
1565   return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1566 }
1567 
1568 unsigned ARMMCCodeEmitter::
1569 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1570                                SmallVectorImpl<MCFixup> &Fixups,
1571                                const MCSubtargetInfo &STI) const {
1572   // 10 bits. lower 5 bits are the lsb of the mask, high five bits are the
1573   // msb of the mask.
1574   const MCOperand &MO = MI.getOperand(Op);
1575   uint32_t v = ~MO.getImm();
1576   uint32_t lsb = countTrailingZeros(v);
1577   uint32_t msb = (32 - countLeadingZeros (v)) - 1;
1578   assert(v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1579   return lsb | (msb << 5);
1580 }
1581 
1582 unsigned ARMMCCodeEmitter::
1583 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1584                        SmallVectorImpl<MCFixup> &Fixups,
1585                        const MCSubtargetInfo &STI) const {
1586   // VLDM/VSTM/VSCCLRM:
1587   //   {12-8} = Vd
1588   //   {7-0}  = Number of registers
1589   //
1590   // LDM/STM:
1591   //   {15-0}  = Bitfield of GPRs.
1592   unsigned Reg = MI.getOperand(Op).getReg();
1593   bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1594   bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1595   bool CLRMRegs = MI.getOpcode() == ARM::t2CLRM;
1596 
1597   unsigned Binary = 0;
1598 
1599   if (SPRRegs || DPRRegs) {
1600     // VLDM/VSTM/VSCCLRM
1601     unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1602     unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1603     Binary |= (RegNo & 0x1f) << 8;
1604 
1605     // Ignore VPR
1606     if (MI.getOpcode() == ARM::VSCCLRMD || MI.getOpcode() == ARM::VSCCLRMS)
1607       --NumRegs;
1608     if (SPRRegs)
1609       Binary |= NumRegs;
1610     else
1611       Binary |= NumRegs * 2;
1612   } else {
1613     const MCRegisterInfo &MRI = *CTX.getRegisterInfo();
1614     if (!CLRMRegs) {
1615       assert(std::is_sorted(MI.begin() + Op, MI.end(),
1616                             [&](const MCOperand &LHS, const MCOperand &RHS) {
1617                               return MRI.getEncodingValue(LHS.getReg()) <
1618                                      MRI.getEncodingValue(RHS.getReg());
1619                             }));
1620     }
1621 
1622     for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1623       unsigned RegNo;
1624       if (CLRMRegs && MI.getOperand(I).getReg() == ARM::APSR) {
1625         RegNo = 15;
1626       } else {
1627         RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
1628       }
1629       Binary |= 1 << RegNo;
1630     }
1631   }
1632 
1633   return Binary;
1634 }
1635 
1636 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1637 /// with the alignment operand.
1638 unsigned ARMMCCodeEmitter::
1639 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1640                            SmallVectorImpl<MCFixup> &Fixups,
1641                            const MCSubtargetInfo &STI) const {
1642   const MCOperand &Reg = MI.getOperand(Op);
1643   const MCOperand &Imm = MI.getOperand(Op + 1);
1644 
1645   unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1646   unsigned Align = 0;
1647 
1648   switch (Imm.getImm()) {
1649   default: break;
1650   case 2:
1651   case 4:
1652   case 8:  Align = 0x01; break;
1653   case 16: Align = 0x02; break;
1654   case 32: Align = 0x03; break;
1655   }
1656 
1657   return RegNo | (Align << 4);
1658 }
1659 
1660 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1661 /// along  with the alignment operand for use in VST1 and VLD1 with size 32.
1662 unsigned ARMMCCodeEmitter::
1663 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1664                                     SmallVectorImpl<MCFixup> &Fixups,
1665                                     const MCSubtargetInfo &STI) const {
1666   const MCOperand &Reg = MI.getOperand(Op);
1667   const MCOperand &Imm = MI.getOperand(Op + 1);
1668 
1669   unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1670   unsigned Align = 0;
1671 
1672   switch (Imm.getImm()) {
1673   default: break;
1674   case 8:
1675   case 16:
1676   case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1677   case 2: Align = 0x00; break;
1678   case 4: Align = 0x03; break;
1679   }
1680 
1681   return RegNo | (Align << 4);
1682 }
1683 
1684 
1685 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1686 /// alignment operand for use in VLD-dup instructions.  This is the same as
1687 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1688 /// different for VLD4-dup.
1689 unsigned ARMMCCodeEmitter::
1690 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1691                               SmallVectorImpl<MCFixup> &Fixups,
1692                               const MCSubtargetInfo &STI) const {
1693   const MCOperand &Reg = MI.getOperand(Op);
1694   const MCOperand &Imm = MI.getOperand(Op + 1);
1695 
1696   unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1697   unsigned Align = 0;
1698 
1699   switch (Imm.getImm()) {
1700   default: break;
1701   case 2:
1702   case 4:
1703   case 8:  Align = 0x01; break;
1704   case 16: Align = 0x03; break;
1705   }
1706 
1707   return RegNo | (Align << 4);
1708 }
1709 
1710 unsigned ARMMCCodeEmitter::
1711 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1712                           SmallVectorImpl<MCFixup> &Fixups,
1713                           const MCSubtargetInfo &STI) const {
1714   const MCOperand &MO = MI.getOperand(Op);
1715   if (MO.getReg() == 0) return 0x0D;
1716   return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1717 }
1718 
1719 unsigned ARMMCCodeEmitter::
1720 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1721                   SmallVectorImpl<MCFixup> &Fixups,
1722                   const MCSubtargetInfo &STI) const {
1723   return 8 - MI.getOperand(Op).getImm();
1724 }
1725 
1726 unsigned ARMMCCodeEmitter::
1727 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1728                    SmallVectorImpl<MCFixup> &Fixups,
1729                    const MCSubtargetInfo &STI) const {
1730   return 16 - MI.getOperand(Op).getImm();
1731 }
1732 
1733 unsigned ARMMCCodeEmitter::
1734 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1735                    SmallVectorImpl<MCFixup> &Fixups,
1736                    const MCSubtargetInfo &STI) const {
1737   return 32 - MI.getOperand(Op).getImm();
1738 }
1739 
1740 unsigned ARMMCCodeEmitter::
1741 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1742                    SmallVectorImpl<MCFixup> &Fixups,
1743                    const MCSubtargetInfo &STI) const {
1744   return 64 - MI.getOperand(Op).getImm();
1745 }
1746 
1747 void ARMMCCodeEmitter::
1748 encodeInstruction(const MCInst &MI, raw_ostream &OS,
1749                   SmallVectorImpl<MCFixup> &Fixups,
1750                   const MCSubtargetInfo &STI) const {
1751   // Pseudo instructions don't get encoded.
1752   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1753   uint64_t TSFlags = Desc.TSFlags;
1754   if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1755     return;
1756 
1757   int Size;
1758   if (Desc.getSize() == 2 || Desc.getSize() == 4)
1759     Size = Desc.getSize();
1760   else
1761     llvm_unreachable("Unexpected instruction size!");
1762 
1763   uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1764   // Thumb 32-bit wide instructions need to emit the high order halfword
1765   // first.
1766   if (isThumb(STI) && Size == 4) {
1767     EmitConstant(Binary >> 16, 2, OS);
1768     EmitConstant(Binary & 0xffff, 2, OS);
1769   } else
1770     EmitConstant(Binary, Size, OS);
1771   ++MCNumEmitted;  // Keep track of the # of mi's emitted.
1772 }
1773 
1774 template <bool isNeg, ARM::Fixups fixup>
1775 uint32_t
1776 ARMMCCodeEmitter::getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
1777                                      SmallVectorImpl<MCFixup> &Fixups,
1778                                      const MCSubtargetInfo &STI) const {
1779   const MCOperand MO = MI.getOperand(OpIdx);
1780   if (MO.isExpr())
1781     return ::getBranchTargetOpValue(MI, OpIdx, fixup, Fixups, STI);
1782   return isNeg ? -(MO.getImm() >> 1) : (MO.getImm() >> 1);
1783 }
1784 
1785 uint32_t
1786 ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
1787                                           SmallVectorImpl<MCFixup> &Fixups,
1788                                           const MCSubtargetInfo &STI) const {
1789   const MCOperand MO = MI.getOperand(OpIdx);
1790   const MCOperand BranchMO = MI.getOperand(0);
1791 
1792   if (MO.isExpr()) {
1793     assert(BranchMO.isExpr());
1794     const MCExpr *DiffExpr = MCBinaryExpr::createSub(
1795         MO.getExpr(), BranchMO.getExpr(), CTX);
1796     MCFixupKind Kind = MCFixupKind(ARM::fixup_bfcsel_else_target);
1797     Fixups.push_back(llvm::MCFixup::create(0, DiffExpr, Kind, MI.getLoc()));
1798     return 0;
1799   }
1800 
1801   assert(MO.isImm() && BranchMO.isImm());
1802   int Diff = MO.getImm() - BranchMO.getImm();
1803   assert(Diff == 4 || Diff == 2);
1804 
1805   return Diff == 4;
1806 }
1807 
1808 uint32_t ARMMCCodeEmitter::getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
1809                                              SmallVectorImpl<MCFixup> &Fixups,
1810                                              const MCSubtargetInfo &STI)const {
1811   const MCOperand MO = MI.getOperand(OpIdx);
1812   assert(MO.isImm() && "Unexpected operand type!");
1813 
1814   int Value = MO.getImm();
1815   int Imm = 0;
1816 
1817   // VPT Masks are actually encoded as a series of invert/don't invert bits,
1818   // rather than true/false bits.
1819   unsigned PrevBit = 0;
1820   for (int i = 3; i >= 0; --i) {
1821     unsigned Bit = (Value >> i) & 1;
1822 
1823     // Check if we are at the end of the mask.
1824     if ((Value & ~(~0U << i)) == 0) {
1825       Imm |= (1 << i);
1826       break;
1827     }
1828 
1829     // Convert the bit in the mask based on the previous bit.
1830     if (Bit != PrevBit)
1831       Imm |= (1 << i);
1832 
1833     PrevBit = Bit;
1834   }
1835 
1836   return Imm;
1837 }
1838 
1839 uint32_t ARMMCCodeEmitter::getRestrictedCondCodeOpValue(
1840     const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
1841     const MCSubtargetInfo &STI) const {
1842 
1843   const MCOperand MO = MI.getOperand(OpIdx);
1844   assert(MO.isImm() && "Unexpected operand type!");
1845 
1846   switch (MO.getImm()) {
1847   default:
1848     assert(0 && "Unexpected Condition!");
1849     return 0;
1850   case ARMCC::HS:
1851   case ARMCC::EQ:
1852     return 0;
1853   case ARMCC::HI:
1854   case ARMCC::NE:
1855     return 1;
1856   case ARMCC::GE:
1857     return 4;
1858   case ARMCC::LT:
1859     return 5;
1860   case ARMCC::GT:
1861     return 6;
1862   case ARMCC::LE:
1863     return 7;
1864   }
1865 }
1866 
1867 #include "ARMGenMCCodeEmitter.inc"
1868 
1869 MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
1870                                               const MCRegisterInfo &MRI,
1871                                               MCContext &Ctx) {
1872   return new ARMMCCodeEmitter(MCII, Ctx, true);
1873 }
1874 
1875 MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
1876                                               const MCRegisterInfo &MRI,
1877                                               MCContext &Ctx) {
1878   return new ARMMCCodeEmitter(MCII, Ctx, false);
1879 }
1880