1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/ARMMCTargetDesc.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "MCTargetDesc/ARMAsmBackend.h" 13 #include "MCTargetDesc/ARMAsmBackendDarwin.h" 14 #include "MCTargetDesc/ARMAsmBackendELF.h" 15 #include "MCTargetDesc/ARMAsmBackendWinCOFF.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "MCTargetDesc/ARMFixupKinds.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/MC/MCAsmBackend.h" 20 #include "llvm/MC/MCAssembler.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCDirectives.h" 23 #include "llvm/MC/MCELFObjectWriter.h" 24 #include "llvm/MC/MCExpr.h" 25 #include "llvm/MC/MCFixupKindInfo.h" 26 #include "llvm/MC/MCMachObjectWriter.h" 27 #include "llvm/MC/MCObjectWriter.h" 28 #include "llvm/MC/MCRegisterInfo.h" 29 #include "llvm/MC/MCSectionELF.h" 30 #include "llvm/MC/MCSectionMachO.h" 31 #include "llvm/MC/MCSubtargetInfo.h" 32 #include "llvm/MC/MCValue.h" 33 #include "llvm/Support/Debug.h" 34 #include "llvm/Support/ELF.h" 35 #include "llvm/Support/ErrorHandling.h" 36 #include "llvm/Support/Format.h" 37 #include "llvm/Support/MachO.h" 38 #include "llvm/Support/TargetParser.h" 39 #include "llvm/Support/raw_ostream.h" 40 using namespace llvm; 41 42 namespace { 43 class ARMELFObjectWriter : public MCELFObjectTargetWriter { 44 public: 45 ARMELFObjectWriter(uint8_t OSABI) 46 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM, 47 /*HasRelocationAddend*/ false) {} 48 }; 49 } // end anonymous namespace 50 51 const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { 52 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = { 53 // This table *must* be in the order that the fixup_* kinds are defined in 54 // ARMFixupKinds.h. 55 // 56 // Name Offset (bits) Size (bits) Flags 57 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 58 {"fixup_t2_ldst_pcrel_12", 0, 32, 59 MCFixupKindInfo::FKF_IsPCRel | 60 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 61 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 62 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 63 {"fixup_t2_pcrel_10", 0, 32, 64 MCFixupKindInfo::FKF_IsPCRel | 65 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 66 {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 67 {"fixup_t2_pcrel_9", 0, 32, 68 MCFixupKindInfo::FKF_IsPCRel | 69 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 70 {"fixup_thumb_adr_pcrel_10", 0, 8, 71 MCFixupKindInfo::FKF_IsPCRel | 72 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 73 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 74 {"fixup_t2_adr_pcrel_12", 0, 32, 75 MCFixupKindInfo::FKF_IsPCRel | 76 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 77 {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 78 {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 79 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 80 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 81 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 82 {"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 83 {"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 84 {"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 85 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 86 {"fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 87 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 88 {"fixup_arm_thumb_cp", 0, 8, 89 MCFixupKindInfo::FKF_IsPCRel | 90 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 91 {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel}, 92 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 93 // - 19. 94 {"fixup_arm_movt_hi16", 0, 20, 0}, 95 {"fixup_arm_movw_lo16", 0, 20, 0}, 96 {"fixup_t2_movt_hi16", 0, 20, 0}, 97 {"fixup_t2_movw_lo16", 0, 20, 0}, 98 {"fixup_arm_mod_imm", 0, 12, 0}, 99 }; 100 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = { 101 // This table *must* be in the order that the fixup_* kinds are defined in 102 // ARMFixupKinds.h. 103 // 104 // Name Offset (bits) Size (bits) Flags 105 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 106 {"fixup_t2_ldst_pcrel_12", 0, 32, 107 MCFixupKindInfo::FKF_IsPCRel | 108 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 109 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 110 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 111 {"fixup_t2_pcrel_10", 0, 32, 112 MCFixupKindInfo::FKF_IsPCRel | 113 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 114 {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 115 {"fixup_t2_pcrel_9", 0, 32, 116 MCFixupKindInfo::FKF_IsPCRel | 117 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 118 {"fixup_thumb_adr_pcrel_10", 8, 8, 119 MCFixupKindInfo::FKF_IsPCRel | 120 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 121 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 122 {"fixup_t2_adr_pcrel_12", 0, 32, 123 MCFixupKindInfo::FKF_IsPCRel | 124 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 125 {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 126 {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 127 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 128 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 129 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 130 {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 131 {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 132 {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 133 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 134 {"fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 135 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 136 {"fixup_arm_thumb_cp", 8, 8, 137 MCFixupKindInfo::FKF_IsPCRel | 138 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 139 {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel}, 140 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 141 // - 19. 142 {"fixup_arm_movt_hi16", 12, 20, 0}, 143 {"fixup_arm_movw_lo16", 12, 20, 0}, 144 {"fixup_t2_movt_hi16", 12, 20, 0}, 145 {"fixup_t2_movw_lo16", 12, 20, 0}, 146 {"fixup_arm_mod_imm", 20, 12, 0}, 147 }; 148 149 if (Kind < FirstTargetFixupKind) 150 return MCAsmBackend::getFixupKindInfo(Kind); 151 152 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 153 "Invalid kind!"); 154 return (IsLittleEndian ? InfosLE : InfosBE)[Kind - FirstTargetFixupKind]; 155 } 156 157 void ARMAsmBackend::handleAssemblerFlag(MCAssemblerFlag Flag) { 158 switch (Flag) { 159 default: 160 break; 161 case MCAF_Code16: 162 setIsThumb(true); 163 break; 164 case MCAF_Code32: 165 setIsThumb(false); 166 break; 167 } 168 } 169 170 unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op) const { 171 bool HasThumb2 = STI->getFeatureBits()[ARM::FeatureThumb2]; 172 bool HasV8MBaselineOps = STI->getFeatureBits()[ARM::HasV8MBaselineOps]; 173 174 switch (Op) { 175 default: 176 return Op; 177 case ARM::tBcc: 178 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op; 179 case ARM::tLDRpci: 180 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op; 181 case ARM::tADR: 182 return HasThumb2 ? (unsigned)ARM::t2ADR : Op; 183 case ARM::tB: 184 return HasV8MBaselineOps ? (unsigned)ARM::t2B : Op; 185 case ARM::tCBZ: 186 return ARM::tHINT; 187 case ARM::tCBNZ: 188 return ARM::tHINT; 189 } 190 } 191 192 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 193 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode()) 194 return true; 195 return false; 196 } 197 198 const char *ARMAsmBackend::reasonForFixupRelaxation(const MCFixup &Fixup, 199 uint64_t Value) const { 200 switch ((unsigned)Fixup.getKind()) { 201 case ARM::fixup_arm_thumb_br: { 202 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the 203 // low bit being an implied zero. There's an implied +4 offset for the 204 // branch, so we adjust the other way here to determine what's 205 // encodable. 206 // 207 // Relax if the value is too big for a (signed) i8. 208 int64_t Offset = int64_t(Value) - 4; 209 if (Offset > 2046 || Offset < -2048) 210 return "out of range pc-relative fixup value"; 211 break; 212 } 213 case ARM::fixup_arm_thumb_bcc: { 214 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the 215 // low bit being an implied zero. There's an implied +4 offset for the 216 // branch, so we adjust the other way here to determine what's 217 // encodable. 218 // 219 // Relax if the value is too big for a (signed) i8. 220 int64_t Offset = int64_t(Value) - 4; 221 if (Offset > 254 || Offset < -256) 222 return "out of range pc-relative fixup value"; 223 break; 224 } 225 case ARM::fixup_thumb_adr_pcrel_10: 226 case ARM::fixup_arm_thumb_cp: { 227 // If the immediate is negative, greater than 1020, or not a multiple 228 // of four, the wide version of the instruction must be used. 229 int64_t Offset = int64_t(Value) - 4; 230 if (Offset & 3) 231 return "misaligned pc-relative fixup value"; 232 else if (Offset > 1020 || Offset < 0) 233 return "out of range pc-relative fixup value"; 234 break; 235 } 236 case ARM::fixup_arm_thumb_cb: { 237 // If we have a Thumb CBZ or CBNZ instruction and its target is the next 238 // instruction it is is actually out of range for the instruction. 239 // It will be changed to a NOP. 240 int64_t Offset = (Value & ~1); 241 if (Offset == 2) 242 return "will be converted to nop"; 243 break; 244 } 245 default: 246 llvm_unreachable("Unexpected fixup kind in reasonForFixupRelaxation()!"); 247 } 248 return nullptr; 249 } 250 251 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, 252 const MCRelaxableFragment *DF, 253 const MCAsmLayout &Layout) const { 254 return reasonForFixupRelaxation(Fixup, Value); 255 } 256 257 void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const { 258 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode()); 259 260 // Sanity check w/ diagnostic if we get here w/ a bogus instruction. 261 if (RelaxedOp == Inst.getOpcode()) { 262 SmallString<256> Tmp; 263 raw_svector_ostream OS(Tmp); 264 Inst.dump_pretty(OS); 265 OS << "\n"; 266 report_fatal_error("unexpected instruction to relax: " + OS.str()); 267 } 268 269 // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we 270 // have to change the operands too. 271 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) && 272 RelaxedOp == ARM::tHINT) { 273 Res.setOpcode(RelaxedOp); 274 Res.addOperand(MCOperand::createImm(0)); 275 Res.addOperand(MCOperand::createImm(14)); 276 Res.addOperand(MCOperand::createReg(0)); 277 return; 278 } 279 280 // The rest of instructions we're relaxing have the same operands. 281 // We just need to update to the proper opcode. 282 Res = Inst; 283 Res.setOpcode(RelaxedOp); 284 } 285 286 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 287 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8 288 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP 289 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0 290 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP 291 if (isThumb()) { 292 const uint16_t nopEncoding = 293 hasNOP() ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding; 294 uint64_t NumNops = Count / 2; 295 for (uint64_t i = 0; i != NumNops; ++i) 296 OW->write16(nopEncoding); 297 if (Count & 1) 298 OW->write8(0); 299 return true; 300 } 301 // ARM mode 302 const uint32_t nopEncoding = 303 hasNOP() ? ARMv6T2_NopEncoding : ARMv4_NopEncoding; 304 uint64_t NumNops = Count / 4; 305 for (uint64_t i = 0; i != NumNops; ++i) 306 OW->write32(nopEncoding); 307 // FIXME: should this function return false when unable to write exactly 308 // 'Count' bytes with NOP encodings? 309 switch (Count % 4) { 310 default: 311 break; // No leftover bytes to write 312 case 1: 313 OW->write8(0); 314 break; 315 case 2: 316 OW->write16(0); 317 break; 318 case 3: 319 OW->write16(0); 320 OW->write8(0xa0); 321 break; 322 } 323 324 return true; 325 } 326 327 static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) { 328 if (IsLittleEndian) { 329 // Note that the halfwords are stored high first and low second in thumb; 330 // so we need to swap the fixup value here to map properly. 331 uint32_t Swapped = (Value & 0xFFFF0000) >> 16; 332 Swapped |= (Value & 0x0000FFFF) << 16; 333 return Swapped; 334 } else 335 return Value; 336 } 337 338 static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf, 339 bool IsLittleEndian) { 340 uint32_t Value; 341 342 if (IsLittleEndian) { 343 Value = (SecondHalf & 0xFFFF) << 16; 344 Value |= (FirstHalf & 0xFFFF); 345 } else { 346 Value = (SecondHalf & 0xFFFF); 347 Value |= (FirstHalf & 0xFFFF) << 16; 348 } 349 350 return Value; 351 } 352 353 unsigned ARMAsmBackend::adjustFixupValue(const MCFixup &Fixup, uint64_t Value, 354 bool IsPCRel, MCContext *Ctx, 355 bool IsLittleEndian, 356 bool IsResolved) const { 357 unsigned Kind = Fixup.getKind(); 358 switch (Kind) { 359 default: 360 llvm_unreachable("Unknown fixup kind!"); 361 case FK_Data_1: 362 case FK_Data_2: 363 case FK_Data_4: 364 return Value; 365 case FK_SecRel_2: 366 return Value; 367 case FK_SecRel_4: 368 return Value; 369 case ARM::fixup_arm_movt_hi16: 370 if (!IsPCRel) 371 Value >>= 16; 372 // Fallthrough 373 case ARM::fixup_arm_movw_lo16: { 374 unsigned Hi4 = (Value & 0xF000) >> 12; 375 unsigned Lo12 = Value & 0x0FFF; 376 // inst{19-16} = Hi4; 377 // inst{11-0} = Lo12; 378 Value = (Hi4 << 16) | (Lo12); 379 return Value; 380 } 381 case ARM::fixup_t2_movt_hi16: 382 if (!IsPCRel) 383 Value >>= 16; 384 // Fallthrough 385 case ARM::fixup_t2_movw_lo16: { 386 unsigned Hi4 = (Value & 0xF000) >> 12; 387 unsigned i = (Value & 0x800) >> 11; 388 unsigned Mid3 = (Value & 0x700) >> 8; 389 unsigned Lo8 = Value & 0x0FF; 390 // inst{19-16} = Hi4; 391 // inst{26} = i; 392 // inst{14-12} = Mid3; 393 // inst{7-0} = Lo8; 394 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8); 395 return swapHalfWords(Value, IsLittleEndian); 396 } 397 case ARM::fixup_arm_ldst_pcrel_12: 398 // ARM PC-relative values are offset by 8. 399 Value -= 4; 400 // FALLTHROUGH 401 case ARM::fixup_t2_ldst_pcrel_12: { 402 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 403 Value -= 4; 404 bool isAdd = true; 405 if ((int64_t)Value < 0) { 406 Value = -Value; 407 isAdd = false; 408 } 409 if (Ctx && Value >= 4096) { 410 Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 411 return 0; 412 } 413 Value |= isAdd << 23; 414 415 // Same addressing mode as fixup_arm_pcrel_10, 416 // but with 16-bit halfwords swapped. 417 if (Kind == ARM::fixup_t2_ldst_pcrel_12) 418 return swapHalfWords(Value, IsLittleEndian); 419 420 return Value; 421 } 422 case ARM::fixup_arm_adr_pcrel_12: { 423 // ARM PC-relative values are offset by 8. 424 Value -= 8; 425 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 426 if ((int64_t)Value < 0) { 427 Value = -Value; 428 opc = 2; // 0b0010 429 } 430 if (Ctx && ARM_AM::getSOImmVal(Value) == -1) { 431 Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 432 return 0; 433 } 434 // Encode the immediate and shift the opcode into place. 435 return ARM_AM::getSOImmVal(Value) | (opc << 21); 436 } 437 438 case ARM::fixup_t2_adr_pcrel_12: { 439 Value -= 4; 440 unsigned opc = 0; 441 if ((int64_t)Value < 0) { 442 Value = -Value; 443 opc = 5; 444 } 445 446 uint32_t out = (opc << 21); 447 out |= (Value & 0x800) << 15; 448 out |= (Value & 0x700) << 4; 449 out |= (Value & 0x0FF); 450 451 return swapHalfWords(out, IsLittleEndian); 452 } 453 454 case ARM::fixup_arm_condbranch: 455 case ARM::fixup_arm_uncondbranch: 456 case ARM::fixup_arm_uncondbl: 457 case ARM::fixup_arm_condbl: 458 case ARM::fixup_arm_blx: 459 // These values don't encode the low two bits since they're always zero. 460 // Offset by 8 just as above. 461 if (const MCSymbolRefExpr *SRE = 462 dyn_cast<MCSymbolRefExpr>(Fixup.getValue())) 463 if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL) 464 return 0; 465 return 0xffffff & ((Value - 8) >> 2); 466 case ARM::fixup_t2_uncondbranch: { 467 Value = Value - 4; 468 Value >>= 1; // Low bit is not encoded. 469 470 uint32_t out = 0; 471 bool I = Value & 0x800000; 472 bool J1 = Value & 0x400000; 473 bool J2 = Value & 0x200000; 474 J1 ^= I; 475 J2 ^= I; 476 477 out |= I << 26; // S bit 478 out |= !J1 << 13; // J1 bit 479 out |= !J2 << 11; // J2 bit 480 out |= (Value & 0x1FF800) << 5; // imm6 field 481 out |= (Value & 0x0007FF); // imm11 field 482 483 return swapHalfWords(out, IsLittleEndian); 484 } 485 case ARM::fixup_t2_condbranch: { 486 Value = Value - 4; 487 Value >>= 1; // Low bit is not encoded. 488 489 uint64_t out = 0; 490 out |= (Value & 0x80000) << 7; // S bit 491 out |= (Value & 0x40000) >> 7; // J2 bit 492 out |= (Value & 0x20000) >> 4; // J1 bit 493 out |= (Value & 0x1F800) << 5; // imm6 field 494 out |= (Value & 0x007FF); // imm11 field 495 496 return swapHalfWords(out, IsLittleEndian); 497 } 498 case ARM::fixup_arm_thumb_bl: { 499 // The value doesn't encode the low bit (always zero) and is offset by 500 // four. The 32-bit immediate value is encoded as 501 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0) 502 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S). 503 // The value is encoded into disjoint bit positions in the destination 504 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit, 505 // J = either J1 or J2 bit 506 // 507 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII 508 // 509 // Note that the halfwords are stored high first, low second; so we need 510 // to transpose the fixup value here to map properly. 511 uint32_t offset = (Value - 4) >> 1; 512 uint32_t signBit = (offset & 0x800000) >> 23; 513 uint32_t I1Bit = (offset & 0x400000) >> 22; 514 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit; 515 uint32_t I2Bit = (offset & 0x200000) >> 21; 516 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit; 517 uint32_t imm10Bits = (offset & 0x1FF800) >> 11; 518 uint32_t imm11Bits = (offset & 0x000007FF); 519 520 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits); 521 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) | 522 (uint16_t)imm11Bits); 523 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian); 524 } 525 case ARM::fixup_arm_thumb_blx: { 526 // The value doesn't encode the low two bits (always zero) and is offset by 527 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as 528 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00) 529 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S). 530 // The value is encoded into disjoint bit positions in the destination 531 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit, 532 // J = either J1 or J2 bit, 0 = zero. 533 // 534 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0 535 // 536 // Note that the halfwords are stored high first, low second; so we need 537 // to transpose the fixup value here to map properly. 538 uint32_t offset = (Value - 2) >> 2; 539 if (const MCSymbolRefExpr *SRE = 540 dyn_cast<MCSymbolRefExpr>(Fixup.getValue())) 541 if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL) 542 offset = 0; 543 uint32_t signBit = (offset & 0x400000) >> 22; 544 uint32_t I1Bit = (offset & 0x200000) >> 21; 545 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit; 546 uint32_t I2Bit = (offset & 0x100000) >> 20; 547 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit; 548 uint32_t imm10HBits = (offset & 0xFFC00) >> 10; 549 uint32_t imm10LBits = (offset & 0x3FF); 550 551 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits); 552 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) | 553 ((uint16_t)imm10LBits) << 1); 554 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian); 555 } 556 case ARM::fixup_thumb_adr_pcrel_10: 557 case ARM::fixup_arm_thumb_cp: 558 // On CPUs supporting Thumb2, this will be relaxed to an ldr.w, otherwise we 559 // could have an error on our hands. 560 if (Ctx && !STI->getFeatureBits()[ARM::FeatureThumb2] && IsResolved) { 561 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value); 562 if (FixupDiagnostic) { 563 Ctx->reportError(Fixup.getLoc(), FixupDiagnostic); 564 return 0; 565 } 566 } 567 // Offset by 4, and don't encode the low two bits. 568 return ((Value - 4) >> 2) & 0xff; 569 case ARM::fixup_arm_thumb_cb: { 570 // Offset by 4 and don't encode the lower bit, which is always 0. 571 // FIXME: diagnose if no Thumb2 572 uint32_t Binary = (Value - 4) >> 1; 573 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3); 574 } 575 case ARM::fixup_arm_thumb_br: 576 // Offset by 4 and don't encode the lower bit, which is always 0. 577 if (Ctx && !STI->getFeatureBits()[ARM::FeatureThumb2] && 578 !STI->getFeatureBits()[ARM::HasV8MBaselineOps]) { 579 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value); 580 if (FixupDiagnostic) { 581 Ctx->reportError(Fixup.getLoc(), FixupDiagnostic); 582 return 0; 583 } 584 } 585 return ((Value - 4) >> 1) & 0x7ff; 586 case ARM::fixup_arm_thumb_bcc: 587 // Offset by 4 and don't encode the lower bit, which is always 0. 588 if (Ctx && !STI->getFeatureBits()[ARM::FeatureThumb2]) { 589 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value); 590 if (FixupDiagnostic) { 591 Ctx->reportError(Fixup.getLoc(), FixupDiagnostic); 592 return 0; 593 } 594 } 595 return ((Value - 4) >> 1) & 0xff; 596 case ARM::fixup_arm_pcrel_10_unscaled: { 597 Value = Value - 8; // ARM fixups offset by an additional word and don't 598 // need to adjust for the half-word ordering. 599 bool isAdd = true; 600 if ((int64_t)Value < 0) { 601 Value = -Value; 602 isAdd = false; 603 } 604 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8]. 605 if (Ctx && Value >= 256) { 606 Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 607 return 0; 608 } 609 Value = (Value & 0xf) | ((Value & 0xf0) << 4); 610 return Value | (isAdd << 23); 611 } 612 case ARM::fixup_arm_pcrel_10: 613 Value = Value - 4; // ARM fixups offset by an additional word and don't 614 // need to adjust for the half-word ordering. 615 // Fall through. 616 case ARM::fixup_t2_pcrel_10: { 617 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 618 Value = Value - 4; 619 bool isAdd = true; 620 if ((int64_t)Value < 0) { 621 Value = -Value; 622 isAdd = false; 623 } 624 // These values don't encode the low two bits since they're always zero. 625 Value >>= 2; 626 if (Ctx && Value >= 256) { 627 Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 628 return 0; 629 } 630 Value |= isAdd << 23; 631 632 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords 633 // swapped. 634 if (Kind == ARM::fixup_t2_pcrel_10) 635 return swapHalfWords(Value, IsLittleEndian); 636 637 return Value; 638 } 639 case ARM::fixup_arm_pcrel_9: 640 Value = Value - 4; // ARM fixups offset by an additional word and don't 641 // need to adjust for the half-word ordering. 642 // Fall through. 643 case ARM::fixup_t2_pcrel_9: { 644 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 645 Value = Value - 4; 646 bool isAdd = true; 647 if ((int64_t)Value < 0) { 648 Value = -Value; 649 isAdd = false; 650 } 651 // These values don't encode the low bit since it's always zero. 652 if (Ctx && (Value & 1)) { 653 Ctx->reportError(Fixup.getLoc(), "invalid value for this fixup"); 654 return 0; 655 } 656 Value >>= 1; 657 if (Ctx && Value >= 256) { 658 Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 659 return 0; 660 } 661 Value |= isAdd << 23; 662 663 // Same addressing mode as fixup_arm_pcrel_9, but with 16-bit halfwords 664 // swapped. 665 if (Kind == ARM::fixup_t2_pcrel_9) 666 return swapHalfWords(Value, IsLittleEndian); 667 668 return Value; 669 } 670 case ARM::fixup_arm_mod_imm: 671 Value = ARM_AM::getSOImmVal(Value); 672 if (Ctx && Value >> 12) { 673 Ctx->reportError(Fixup.getLoc(), "out of range immediate fixup value"); 674 return 0; 675 } 676 return Value; 677 } 678 } 679 680 void ARMAsmBackend::processFixupValue(const MCAssembler &Asm, 681 const MCAsmLayout &Layout, 682 const MCFixup &Fixup, 683 const MCFragment *DF, 684 const MCValue &Target, uint64_t &Value, 685 bool &IsResolved) { 686 const MCSymbolRefExpr *A = Target.getSymA(); 687 const MCSymbol *Sym = A ? &A->getSymbol() : nullptr; 688 // Some fixups to thumb function symbols need the low bit (thumb bit) 689 // twiddled. 690 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 && 691 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 && 692 (unsigned)Fixup.getKind() != ARM::fixup_arm_adr_pcrel_12 && 693 (unsigned)Fixup.getKind() != ARM::fixup_thumb_adr_pcrel_10 && 694 (unsigned)Fixup.getKind() != ARM::fixup_t2_adr_pcrel_12 && 695 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) { 696 if (Sym) { 697 if (Asm.isThumbFunc(Sym)) 698 Value |= 1; 699 } 700 } 701 if (IsResolved && (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl) { 702 assert(Sym && "How did we resolve this?"); 703 704 // If the symbol is external the linker will handle it. 705 // FIXME: Should we handle it as an optimization? 706 707 // If the symbol is out of range, produce a relocation and hope the 708 // linker can handle it. GNU AS produces an error in this case. 709 if (Sym->isExternal() || Value >= 0x400004) 710 IsResolved = false; 711 } 712 // We must always generate a relocation for BL/BLX instructions if we have 713 // a symbol to reference, as the linker relies on knowing the destination 714 // symbol's thumb-ness to get interworking right. 715 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx || 716 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx || 717 (unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl || 718 (unsigned)Fixup.getKind() == ARM::fixup_arm_condbl)) 719 IsResolved = false; 720 721 // Try to get the encoded value for the fixup as-if we're mapping it into 722 // the instruction. This allows adjustFixupValue() to issue a diagnostic 723 // if the value aren't invalid. 724 (void)adjustFixupValue(Fixup, Value, false, &Asm.getContext(), 725 IsLittleEndian, IsResolved); 726 } 727 728 /// getFixupKindNumBytes - The number of bytes the fixup may change. 729 static unsigned getFixupKindNumBytes(unsigned Kind) { 730 switch (Kind) { 731 default: 732 llvm_unreachable("Unknown fixup kind!"); 733 734 case FK_Data_1: 735 case ARM::fixup_arm_thumb_bcc: 736 case ARM::fixup_arm_thumb_cp: 737 case ARM::fixup_thumb_adr_pcrel_10: 738 return 1; 739 740 case FK_Data_2: 741 case ARM::fixup_arm_thumb_br: 742 case ARM::fixup_arm_thumb_cb: 743 case ARM::fixup_arm_mod_imm: 744 return 2; 745 746 case ARM::fixup_arm_pcrel_10_unscaled: 747 case ARM::fixup_arm_ldst_pcrel_12: 748 case ARM::fixup_arm_pcrel_10: 749 case ARM::fixup_arm_pcrel_9: 750 case ARM::fixup_arm_adr_pcrel_12: 751 case ARM::fixup_arm_uncondbl: 752 case ARM::fixup_arm_condbl: 753 case ARM::fixup_arm_blx: 754 case ARM::fixup_arm_condbranch: 755 case ARM::fixup_arm_uncondbranch: 756 return 3; 757 758 case FK_Data_4: 759 case ARM::fixup_t2_ldst_pcrel_12: 760 case ARM::fixup_t2_condbranch: 761 case ARM::fixup_t2_uncondbranch: 762 case ARM::fixup_t2_pcrel_10: 763 case ARM::fixup_t2_pcrel_9: 764 case ARM::fixup_t2_adr_pcrel_12: 765 case ARM::fixup_arm_thumb_bl: 766 case ARM::fixup_arm_thumb_blx: 767 case ARM::fixup_arm_movt_hi16: 768 case ARM::fixup_arm_movw_lo16: 769 case ARM::fixup_t2_movt_hi16: 770 case ARM::fixup_t2_movw_lo16: 771 return 4; 772 773 case FK_SecRel_2: 774 return 2; 775 case FK_SecRel_4: 776 return 4; 777 } 778 } 779 780 /// getFixupKindContainerSizeBytes - The number of bytes of the 781 /// container involved in big endian. 782 static unsigned getFixupKindContainerSizeBytes(unsigned Kind) { 783 switch (Kind) { 784 default: 785 llvm_unreachable("Unknown fixup kind!"); 786 787 case FK_Data_1: 788 return 1; 789 case FK_Data_2: 790 return 2; 791 case FK_Data_4: 792 return 4; 793 794 case ARM::fixup_arm_thumb_bcc: 795 case ARM::fixup_arm_thumb_cp: 796 case ARM::fixup_thumb_adr_pcrel_10: 797 case ARM::fixup_arm_thumb_br: 798 case ARM::fixup_arm_thumb_cb: 799 // Instruction size is 2 bytes. 800 return 2; 801 802 case ARM::fixup_arm_pcrel_10_unscaled: 803 case ARM::fixup_arm_ldst_pcrel_12: 804 case ARM::fixup_arm_pcrel_10: 805 case ARM::fixup_arm_adr_pcrel_12: 806 case ARM::fixup_arm_uncondbl: 807 case ARM::fixup_arm_condbl: 808 case ARM::fixup_arm_blx: 809 case ARM::fixup_arm_condbranch: 810 case ARM::fixup_arm_uncondbranch: 811 case ARM::fixup_t2_ldst_pcrel_12: 812 case ARM::fixup_t2_condbranch: 813 case ARM::fixup_t2_uncondbranch: 814 case ARM::fixup_t2_pcrel_10: 815 case ARM::fixup_t2_adr_pcrel_12: 816 case ARM::fixup_arm_thumb_bl: 817 case ARM::fixup_arm_thumb_blx: 818 case ARM::fixup_arm_movt_hi16: 819 case ARM::fixup_arm_movw_lo16: 820 case ARM::fixup_t2_movt_hi16: 821 case ARM::fixup_t2_movw_lo16: 822 case ARM::fixup_arm_mod_imm: 823 // Instruction size is 4 bytes. 824 return 4; 825 } 826 } 827 828 void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 829 unsigned DataSize, uint64_t Value, 830 bool IsPCRel) const { 831 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 832 Value = 833 adjustFixupValue(Fixup, Value, IsPCRel, nullptr, IsLittleEndian, true); 834 if (!Value) 835 return; // Doesn't change encoding. 836 837 unsigned Offset = Fixup.getOffset(); 838 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!"); 839 840 // Used to point to big endian bytes. 841 unsigned FullSizeBytes; 842 if (!IsLittleEndian) { 843 FullSizeBytes = getFixupKindContainerSizeBytes(Fixup.getKind()); 844 assert((Offset + FullSizeBytes) <= DataSize && "Invalid fixup size!"); 845 assert(NumBytes <= FullSizeBytes && "Invalid fixup size!"); 846 } 847 848 // For each byte of the fragment that the fixup touches, mask in the bits from 849 // the fixup value. The Value has been "split up" into the appropriate 850 // bitfields above. 851 for (unsigned i = 0; i != NumBytes; ++i) { 852 unsigned Idx = IsLittleEndian ? i : (FullSizeBytes - 1 - i); 853 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff); 854 } 855 } 856 857 namespace CU { 858 859 /// \brief Compact unwind encoding values. 860 enum CompactUnwindEncodings { 861 UNWIND_ARM_MODE_MASK = 0x0F000000, 862 UNWIND_ARM_MODE_FRAME = 0x01000000, 863 UNWIND_ARM_MODE_FRAME_D = 0x02000000, 864 UNWIND_ARM_MODE_DWARF = 0x04000000, 865 866 UNWIND_ARM_FRAME_STACK_ADJUST_MASK = 0x00C00000, 867 868 UNWIND_ARM_FRAME_FIRST_PUSH_R4 = 0x00000001, 869 UNWIND_ARM_FRAME_FIRST_PUSH_R5 = 0x00000002, 870 UNWIND_ARM_FRAME_FIRST_PUSH_R6 = 0x00000004, 871 872 UNWIND_ARM_FRAME_SECOND_PUSH_R8 = 0x00000008, 873 UNWIND_ARM_FRAME_SECOND_PUSH_R9 = 0x00000010, 874 UNWIND_ARM_FRAME_SECOND_PUSH_R10 = 0x00000020, 875 UNWIND_ARM_FRAME_SECOND_PUSH_R11 = 0x00000040, 876 UNWIND_ARM_FRAME_SECOND_PUSH_R12 = 0x00000080, 877 878 UNWIND_ARM_FRAME_D_REG_COUNT_MASK = 0x00000F00, 879 880 UNWIND_ARM_DWARF_SECTION_OFFSET = 0x00FFFFFF 881 }; 882 883 } // end CU namespace 884 885 /// Generate compact unwind encoding for the function based on the CFI 886 /// instructions. If the CFI instructions describe a frame that cannot be 887 /// encoded in compact unwind, the method returns UNWIND_ARM_MODE_DWARF which 888 /// tells the runtime to fallback and unwind using dwarf. 889 uint32_t ARMAsmBackendDarwin::generateCompactUnwindEncoding( 890 ArrayRef<MCCFIInstruction> Instrs) const { 891 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "generateCU()\n"); 892 // Only armv7k uses CFI based unwinding. 893 if (Subtype != MachO::CPU_SUBTYPE_ARM_V7K) 894 return 0; 895 // No .cfi directives means no frame. 896 if (Instrs.empty()) 897 return 0; 898 // Start off assuming CFA is at SP+0. 899 int CFARegister = ARM::SP; 900 int CFARegisterOffset = 0; 901 // Mark savable registers as initially unsaved 902 DenseMap<unsigned, int> RegOffsets; 903 int FloatRegCount = 0; 904 // Process each .cfi directive and build up compact unwind info. 905 for (size_t i = 0, e = Instrs.size(); i != e; ++i) { 906 int Reg; 907 const MCCFIInstruction &Inst = Instrs[i]; 908 switch (Inst.getOperation()) { 909 case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa 910 CFARegisterOffset = -Inst.getOffset(); 911 CFARegister = MRI.getLLVMRegNum(Inst.getRegister(), true); 912 break; 913 case MCCFIInstruction::OpDefCfaOffset: // DW_CFA_def_cfa_offset 914 CFARegisterOffset = -Inst.getOffset(); 915 break; 916 case MCCFIInstruction::OpDefCfaRegister: // DW_CFA_def_cfa_register 917 CFARegister = MRI.getLLVMRegNum(Inst.getRegister(), true); 918 break; 919 case MCCFIInstruction::OpOffset: // DW_CFA_offset 920 Reg = MRI.getLLVMRegNum(Inst.getRegister(), true); 921 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 922 RegOffsets[Reg] = Inst.getOffset(); 923 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 924 RegOffsets[Reg] = Inst.getOffset(); 925 ++FloatRegCount; 926 } else { 927 DEBUG_WITH_TYPE("compact-unwind", 928 llvm::dbgs() << ".cfi_offset on unknown register=" 929 << Inst.getRegister() << "\n"); 930 return CU::UNWIND_ARM_MODE_DWARF; 931 } 932 break; 933 case MCCFIInstruction::OpRelOffset: // DW_CFA_advance_loc 934 // Ignore 935 break; 936 default: 937 // Directive not convertable to compact unwind, bail out. 938 DEBUG_WITH_TYPE("compact-unwind", 939 llvm::dbgs() 940 << "CFI directive not compatiable with comact " 941 "unwind encoding, opcode=" << Inst.getOperation() 942 << "\n"); 943 return CU::UNWIND_ARM_MODE_DWARF; 944 break; 945 } 946 } 947 948 // If no frame set up, return no unwind info. 949 if ((CFARegister == ARM::SP) && (CFARegisterOffset == 0)) 950 return 0; 951 952 // Verify standard frame (lr/r7) was used. 953 if (CFARegister != ARM::R7) { 954 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "frame register is " 955 << CFARegister 956 << " instead of r7\n"); 957 return CU::UNWIND_ARM_MODE_DWARF; 958 } 959 int StackAdjust = CFARegisterOffset - 8; 960 if (RegOffsets.lookup(ARM::LR) != (-4 - StackAdjust)) { 961 DEBUG_WITH_TYPE("compact-unwind", 962 llvm::dbgs() 963 << "LR not saved as standard frame, StackAdjust=" 964 << StackAdjust 965 << ", CFARegisterOffset=" << CFARegisterOffset 966 << ", lr save at offset=" << RegOffsets[14] << "\n"); 967 return CU::UNWIND_ARM_MODE_DWARF; 968 } 969 if (RegOffsets.lookup(ARM::R7) != (-8 - StackAdjust)) { 970 DEBUG_WITH_TYPE("compact-unwind", 971 llvm::dbgs() << "r7 not saved as standard frame\n"); 972 return CU::UNWIND_ARM_MODE_DWARF; 973 } 974 uint32_t CompactUnwindEncoding = CU::UNWIND_ARM_MODE_FRAME; 975 976 // If var-args are used, there may be a stack adjust required. 977 switch (StackAdjust) { 978 case 0: 979 break; 980 case 4: 981 CompactUnwindEncoding |= 0x00400000; 982 break; 983 case 8: 984 CompactUnwindEncoding |= 0x00800000; 985 break; 986 case 12: 987 CompactUnwindEncoding |= 0x00C00000; 988 break; 989 default: 990 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() 991 << ".cfi_def_cfa stack adjust (" 992 << StackAdjust << ") out of range\n"); 993 return CU::UNWIND_ARM_MODE_DWARF; 994 } 995 996 // If r6 is saved, it must be right below r7. 997 static struct { 998 unsigned Reg; 999 unsigned Encoding; 1000 } GPRCSRegs[] = {{ARM::R6, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R6}, 1001 {ARM::R5, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R5}, 1002 {ARM::R4, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R4}, 1003 {ARM::R12, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R12}, 1004 {ARM::R11, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R11}, 1005 {ARM::R10, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R10}, 1006 {ARM::R9, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R9}, 1007 {ARM::R8, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R8}}; 1008 1009 int CurOffset = -8 - StackAdjust; 1010 for (auto CSReg : GPRCSRegs) { 1011 auto Offset = RegOffsets.find(CSReg.Reg); 1012 if (Offset == RegOffsets.end()) 1013 continue; 1014 1015 int RegOffset = Offset->second; 1016 if (RegOffset != CurOffset - 4) { 1017 DEBUG_WITH_TYPE("compact-unwind", 1018 llvm::dbgs() << MRI.getName(CSReg.Reg) << " saved at " 1019 << RegOffset << " but only supported at " 1020 << CurOffset << "\n"); 1021 return CU::UNWIND_ARM_MODE_DWARF; 1022 } 1023 CompactUnwindEncoding |= CSReg.Encoding; 1024 CurOffset -= 4; 1025 } 1026 1027 // If no floats saved, we are done. 1028 if (FloatRegCount == 0) 1029 return CompactUnwindEncoding; 1030 1031 // Switch mode to include D register saving. 1032 CompactUnwindEncoding &= ~CU::UNWIND_ARM_MODE_MASK; 1033 CompactUnwindEncoding |= CU::UNWIND_ARM_MODE_FRAME_D; 1034 1035 // FIXME: supporting more than 4 saved D-registers compactly would be trivial, 1036 // but needs coordination with the linker and libunwind. 1037 if (FloatRegCount > 4) { 1038 DEBUG_WITH_TYPE("compact-unwind", 1039 llvm::dbgs() << "unsupported number of D registers saved (" 1040 << FloatRegCount << ")\n"); 1041 return CU::UNWIND_ARM_MODE_DWARF; 1042 } 1043 1044 // Floating point registers must either be saved sequentially, or we defer to 1045 // DWARF. No gaps allowed here so check that each saved d-register is 1046 // precisely where it should be. 1047 static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 }; 1048 for (int Idx = FloatRegCount - 1; Idx >= 0; --Idx) { 1049 auto Offset = RegOffsets.find(FPRCSRegs[Idx]); 1050 if (Offset == RegOffsets.end()) { 1051 DEBUG_WITH_TYPE("compact-unwind", 1052 llvm::dbgs() << FloatRegCount << " D-regs saved, but " 1053 << MRI.getName(FPRCSRegs[Idx]) 1054 << " not saved\n"); 1055 return CU::UNWIND_ARM_MODE_DWARF; 1056 } else if (Offset->second != CurOffset - 8) { 1057 DEBUG_WITH_TYPE("compact-unwind", 1058 llvm::dbgs() << FloatRegCount << " D-regs saved, but " 1059 << MRI.getName(FPRCSRegs[Idx]) 1060 << " saved at " << Offset->second 1061 << ", expected at " << CurOffset - 8 1062 << "\n"); 1063 return CU::UNWIND_ARM_MODE_DWARF; 1064 } 1065 CurOffset -= 8; 1066 } 1067 1068 return CompactUnwindEncoding | ((FloatRegCount - 1) << 8); 1069 } 1070 1071 static MachO::CPUSubTypeARM getMachOSubTypeFromArch(StringRef Arch) { 1072 unsigned AK = ARM::parseArch(Arch); 1073 switch (AK) { 1074 default: 1075 return MachO::CPU_SUBTYPE_ARM_V7; 1076 case ARM::AK_ARMV4T: 1077 return MachO::CPU_SUBTYPE_ARM_V4T; 1078 case ARM::AK_ARMV5T: 1079 case ARM::AK_ARMV5TE: 1080 case ARM::AK_ARMV5TEJ: 1081 return MachO::CPU_SUBTYPE_ARM_V5; 1082 case ARM::AK_ARMV6: 1083 case ARM::AK_ARMV6K: 1084 return MachO::CPU_SUBTYPE_ARM_V6; 1085 case ARM::AK_ARMV7A: 1086 return MachO::CPU_SUBTYPE_ARM_V7; 1087 case ARM::AK_ARMV7S: 1088 return MachO::CPU_SUBTYPE_ARM_V7S; 1089 case ARM::AK_ARMV7K: 1090 return MachO::CPU_SUBTYPE_ARM_V7K; 1091 case ARM::AK_ARMV6M: 1092 return MachO::CPU_SUBTYPE_ARM_V6M; 1093 case ARM::AK_ARMV7M: 1094 return MachO::CPU_SUBTYPE_ARM_V7M; 1095 case ARM::AK_ARMV7EM: 1096 return MachO::CPU_SUBTYPE_ARM_V7EM; 1097 } 1098 } 1099 1100 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, 1101 const MCRegisterInfo &MRI, 1102 const Triple &TheTriple, StringRef CPU, 1103 bool isLittle) { 1104 switch (TheTriple.getObjectFormat()) { 1105 default: 1106 llvm_unreachable("unsupported object format"); 1107 case Triple::MachO: { 1108 MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TheTriple.getArchName()); 1109 return new ARMAsmBackendDarwin(T, TheTriple, MRI, CS); 1110 } 1111 case Triple::COFF: 1112 assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported"); 1113 return new ARMAsmBackendWinCOFF(T, TheTriple); 1114 case Triple::ELF: 1115 assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target"); 1116 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); 1117 return new ARMAsmBackendELF(T, TheTriple, OSABI, isLittle); 1118 } 1119 } 1120 1121 MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T, 1122 const MCRegisterInfo &MRI, 1123 const Triple &TT, StringRef CPU) { 1124 return createARMAsmBackend(T, MRI, TT, CPU, true); 1125 } 1126 1127 MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T, 1128 const MCRegisterInfo &MRI, 1129 const Triple &TT, StringRef CPU) { 1130 return createARMAsmBackend(T, MRI, TT, CPU, false); 1131 } 1132 1133 MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T, 1134 const MCRegisterInfo &MRI, 1135 const Triple &TT, StringRef CPU) { 1136 return createARMAsmBackend(T, MRI, TT, CPU, true); 1137 } 1138 1139 MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T, 1140 const MCRegisterInfo &MRI, 1141 const Triple &TT, StringRef CPU) { 1142 return createARMAsmBackend(T, MRI, TT, CPU, false); 1143 } 1144