1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/ARMMCTargetDesc.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "MCTargetDesc/ARMAsmBackend.h" 13 #include "MCTargetDesc/ARMAsmBackendDarwin.h" 14 #include "MCTargetDesc/ARMAsmBackendELF.h" 15 #include "MCTargetDesc/ARMAsmBackendWinCOFF.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "MCTargetDesc/ARMFixupKinds.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/MC/MCAsmBackend.h" 20 #include "llvm/MC/MCAssembler.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCDirectives.h" 23 #include "llvm/MC/MCELFObjectWriter.h" 24 #include "llvm/MC/MCExpr.h" 25 #include "llvm/MC/MCFixupKindInfo.h" 26 #include "llvm/MC/MCMachObjectWriter.h" 27 #include "llvm/MC/MCObjectWriter.h" 28 #include "llvm/MC/MCSectionELF.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/MC/MCSubtargetInfo.h" 31 #include "llvm/MC/MCValue.h" 32 #include "llvm/Support/ELF.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include "llvm/Support/MachO.h" 35 #include "llvm/Support/TargetParser.h" 36 #include "llvm/Support/raw_ostream.h" 37 using namespace llvm; 38 39 namespace { 40 class ARMELFObjectWriter : public MCELFObjectTargetWriter { 41 public: 42 ARMELFObjectWriter(uint8_t OSABI) 43 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM, 44 /*HasRelocationAddend*/ false) {} 45 }; 46 47 const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { 48 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = { 49 // This table *must* be in the order that the fixup_* kinds are defined in 50 // ARMFixupKinds.h. 51 // 52 // Name Offset (bits) Size (bits) Flags 53 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 54 {"fixup_t2_ldst_pcrel_12", 0, 32, 55 MCFixupKindInfo::FKF_IsPCRel | 56 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 57 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 58 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 59 {"fixup_t2_pcrel_10", 0, 32, 60 MCFixupKindInfo::FKF_IsPCRel | 61 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 62 {"fixup_thumb_adr_pcrel_10", 0, 8, 63 MCFixupKindInfo::FKF_IsPCRel | 64 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 65 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 66 {"fixup_t2_adr_pcrel_12", 0, 32, 67 MCFixupKindInfo::FKF_IsPCRel | 68 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 69 {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 70 {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 71 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 72 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 73 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 74 {"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 75 {"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 76 {"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 77 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 78 {"fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 79 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 80 {"fixup_arm_thumb_cp", 0, 8, 81 MCFixupKindInfo::FKF_IsPCRel | 82 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 83 {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel}, 84 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 85 // - 19. 86 {"fixup_arm_movt_hi16", 0, 20, 0}, 87 {"fixup_arm_movw_lo16", 0, 20, 0}, 88 {"fixup_t2_movt_hi16", 0, 20, 0}, 89 {"fixup_t2_movw_lo16", 0, 20, 0}, 90 }; 91 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = { 92 // This table *must* be in the order that the fixup_* kinds are defined in 93 // ARMFixupKinds.h. 94 // 95 // Name Offset (bits) Size (bits) Flags 96 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 97 {"fixup_t2_ldst_pcrel_12", 0, 32, 98 MCFixupKindInfo::FKF_IsPCRel | 99 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 100 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 101 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 102 {"fixup_t2_pcrel_10", 0, 32, 103 MCFixupKindInfo::FKF_IsPCRel | 104 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 105 {"fixup_thumb_adr_pcrel_10", 8, 8, 106 MCFixupKindInfo::FKF_IsPCRel | 107 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 108 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 109 {"fixup_t2_adr_pcrel_12", 0, 32, 110 MCFixupKindInfo::FKF_IsPCRel | 111 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 112 {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 113 {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 114 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 115 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 116 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 117 {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 118 {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 119 {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 120 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 121 {"fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 122 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 123 {"fixup_arm_thumb_cp", 8, 8, 124 MCFixupKindInfo::FKF_IsPCRel | 125 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 126 {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel}, 127 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 128 // - 19. 129 {"fixup_arm_movt_hi16", 12, 20, 0}, 130 {"fixup_arm_movw_lo16", 12, 20, 0}, 131 {"fixup_t2_movt_hi16", 12, 20, 0}, 132 {"fixup_t2_movw_lo16", 12, 20, 0}, 133 }; 134 135 if (Kind < FirstTargetFixupKind) 136 return MCAsmBackend::getFixupKindInfo(Kind); 137 138 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 139 "Invalid kind!"); 140 return (IsLittleEndian ? InfosLE : InfosBE)[Kind - FirstTargetFixupKind]; 141 } 142 143 void ARMAsmBackend::handleAssemblerFlag(MCAssemblerFlag Flag) { 144 switch (Flag) { 145 default: 146 break; 147 case MCAF_Code16: 148 setIsThumb(true); 149 break; 150 case MCAF_Code32: 151 setIsThumb(false); 152 break; 153 } 154 } 155 } // end anonymous namespace 156 157 unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op) const { 158 bool HasThumb2 = STI->getFeatureBits()[ARM::FeatureThumb2]; 159 160 switch (Op) { 161 default: 162 return Op; 163 case ARM::tBcc: 164 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op; 165 case ARM::tLDRpci: 166 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op; 167 case ARM::tADR: 168 return HasThumb2 ? (unsigned)ARM::t2ADR : Op; 169 case ARM::tB: 170 return HasThumb2 ? (unsigned)ARM::t2B : Op; 171 case ARM::tCBZ: 172 return ARM::tHINT; 173 case ARM::tCBNZ: 174 return ARM::tHINT; 175 } 176 } 177 178 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 179 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode()) 180 return true; 181 return false; 182 } 183 184 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, 185 const MCRelaxableFragment *DF, 186 const MCAsmLayout &Layout) const { 187 switch ((unsigned)Fixup.getKind()) { 188 case ARM::fixup_arm_thumb_br: { 189 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the 190 // low bit being an implied zero. There's an implied +4 offset for the 191 // branch, so we adjust the other way here to determine what's 192 // encodable. 193 // 194 // Relax if the value is too big for a (signed) i8. 195 int64_t Offset = int64_t(Value) - 4; 196 return Offset > 2046 || Offset < -2048; 197 } 198 case ARM::fixup_arm_thumb_bcc: { 199 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the 200 // low bit being an implied zero. There's an implied +4 offset for the 201 // branch, so we adjust the other way here to determine what's 202 // encodable. 203 // 204 // Relax if the value is too big for a (signed) i8. 205 int64_t Offset = int64_t(Value) - 4; 206 return Offset > 254 || Offset < -256; 207 } 208 case ARM::fixup_thumb_adr_pcrel_10: 209 case ARM::fixup_arm_thumb_cp: { 210 // If the immediate is negative, greater than 1020, or not a multiple 211 // of four, the wide version of the instruction must be used. 212 int64_t Offset = int64_t(Value) - 4; 213 return Offset > 1020 || Offset < 0 || Offset & 3; 214 } 215 case ARM::fixup_arm_thumb_cb: 216 // If we have a Thumb CBZ or CBNZ instruction and its target is the next 217 // instruction it is is actually out of range for the instruction. 218 // It will be changed to a NOP. 219 int64_t Offset = (Value & ~1); 220 return Offset == 2; 221 } 222 llvm_unreachable("Unexpected fixup kind in fixupNeedsRelaxation()!"); 223 } 224 225 void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const { 226 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode()); 227 228 // Sanity check w/ diagnostic if we get here w/ a bogus instruction. 229 if (RelaxedOp == Inst.getOpcode()) { 230 SmallString<256> Tmp; 231 raw_svector_ostream OS(Tmp); 232 Inst.dump_pretty(OS); 233 OS << "\n"; 234 report_fatal_error("unexpected instruction to relax: " + OS.str()); 235 } 236 237 // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we 238 // have to change the operands too. 239 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) && 240 RelaxedOp == ARM::tHINT) { 241 Res.setOpcode(RelaxedOp); 242 Res.addOperand(MCOperand::createImm(0)); 243 Res.addOperand(MCOperand::createImm(14)); 244 Res.addOperand(MCOperand::createReg(0)); 245 return; 246 } 247 248 // The rest of instructions we're relaxing have the same operands. 249 // We just need to update to the proper opcode. 250 Res = Inst; 251 Res.setOpcode(RelaxedOp); 252 } 253 254 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 255 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8 256 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP 257 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0 258 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP 259 if (isThumb()) { 260 const uint16_t nopEncoding = 261 hasNOP() ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding; 262 uint64_t NumNops = Count / 2; 263 for (uint64_t i = 0; i != NumNops; ++i) 264 OW->write16(nopEncoding); 265 if (Count & 1) 266 OW->write8(0); 267 return true; 268 } 269 // ARM mode 270 const uint32_t nopEncoding = 271 hasNOP() ? ARMv6T2_NopEncoding : ARMv4_NopEncoding; 272 uint64_t NumNops = Count / 4; 273 for (uint64_t i = 0; i != NumNops; ++i) 274 OW->write32(nopEncoding); 275 // FIXME: should this function return false when unable to write exactly 276 // 'Count' bytes with NOP encodings? 277 switch (Count % 4) { 278 default: 279 break; // No leftover bytes to write 280 case 1: 281 OW->write8(0); 282 break; 283 case 2: 284 OW->write16(0); 285 break; 286 case 3: 287 OW->write16(0); 288 OW->write8(0xa0); 289 break; 290 } 291 292 return true; 293 } 294 295 static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) { 296 if (IsLittleEndian) { 297 // Note that the halfwords are stored high first and low second in thumb; 298 // so we need to swap the fixup value here to map properly. 299 uint32_t Swapped = (Value & 0xFFFF0000) >> 16; 300 Swapped |= (Value & 0x0000FFFF) << 16; 301 return Swapped; 302 } else 303 return Value; 304 } 305 306 static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf, 307 bool IsLittleEndian) { 308 uint32_t Value; 309 310 if (IsLittleEndian) { 311 Value = (SecondHalf & 0xFFFF) << 16; 312 Value |= (FirstHalf & 0xFFFF); 313 } else { 314 Value = (SecondHalf & 0xFFFF); 315 Value |= (FirstHalf & 0xFFFF) << 16; 316 } 317 318 return Value; 319 } 320 321 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, 322 bool IsPCRel, MCContext *Ctx, 323 bool IsLittleEndian) { 324 unsigned Kind = Fixup.getKind(); 325 switch (Kind) { 326 default: 327 llvm_unreachable("Unknown fixup kind!"); 328 case FK_Data_1: 329 case FK_Data_2: 330 case FK_Data_4: 331 return Value; 332 case FK_SecRel_2: 333 return Value; 334 case FK_SecRel_4: 335 return Value; 336 case ARM::fixup_arm_movt_hi16: 337 if (!IsPCRel) 338 Value >>= 16; 339 // Fallthrough 340 case ARM::fixup_arm_movw_lo16: { 341 unsigned Hi4 = (Value & 0xF000) >> 12; 342 unsigned Lo12 = Value & 0x0FFF; 343 // inst{19-16} = Hi4; 344 // inst{11-0} = Lo12; 345 Value = (Hi4 << 16) | (Lo12); 346 return Value; 347 } 348 case ARM::fixup_t2_movt_hi16: 349 if (!IsPCRel) 350 Value >>= 16; 351 // Fallthrough 352 case ARM::fixup_t2_movw_lo16: { 353 unsigned Hi4 = (Value & 0xF000) >> 12; 354 unsigned i = (Value & 0x800) >> 11; 355 unsigned Mid3 = (Value & 0x700) >> 8; 356 unsigned Lo8 = Value & 0x0FF; 357 // inst{19-16} = Hi4; 358 // inst{26} = i; 359 // inst{14-12} = Mid3; 360 // inst{7-0} = Lo8; 361 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8); 362 return swapHalfWords(Value, IsLittleEndian); 363 } 364 case ARM::fixup_arm_ldst_pcrel_12: 365 // ARM PC-relative values are offset by 8. 366 Value -= 4; 367 // FALLTHROUGH 368 case ARM::fixup_t2_ldst_pcrel_12: { 369 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 370 Value -= 4; 371 bool isAdd = true; 372 if ((int64_t)Value < 0) { 373 Value = -Value; 374 isAdd = false; 375 } 376 if (Ctx && Value >= 4096) 377 Ctx->reportFatalError(Fixup.getLoc(), "out of range pc-relative fixup value"); 378 Value |= isAdd << 23; 379 380 // Same addressing mode as fixup_arm_pcrel_10, 381 // but with 16-bit halfwords swapped. 382 if (Kind == ARM::fixup_t2_ldst_pcrel_12) 383 return swapHalfWords(Value, IsLittleEndian); 384 385 return Value; 386 } 387 case ARM::fixup_thumb_adr_pcrel_10: 388 return ((Value - 4) >> 2) & 0xff; 389 case ARM::fixup_arm_adr_pcrel_12: { 390 // ARM PC-relative values are offset by 8. 391 Value -= 8; 392 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 393 if ((int64_t)Value < 0) { 394 Value = -Value; 395 opc = 2; // 0b0010 396 } 397 if (Ctx && ARM_AM::getSOImmVal(Value) == -1) 398 Ctx->reportFatalError(Fixup.getLoc(), "out of range pc-relative fixup value"); 399 // Encode the immediate and shift the opcode into place. 400 return ARM_AM::getSOImmVal(Value) | (opc << 21); 401 } 402 403 case ARM::fixup_t2_adr_pcrel_12: { 404 Value -= 4; 405 unsigned opc = 0; 406 if ((int64_t)Value < 0) { 407 Value = -Value; 408 opc = 5; 409 } 410 411 uint32_t out = (opc << 21); 412 out |= (Value & 0x800) << 15; 413 out |= (Value & 0x700) << 4; 414 out |= (Value & 0x0FF); 415 416 return swapHalfWords(out, IsLittleEndian); 417 } 418 419 case ARM::fixup_arm_condbranch: 420 case ARM::fixup_arm_uncondbranch: 421 case ARM::fixup_arm_uncondbl: 422 case ARM::fixup_arm_condbl: 423 case ARM::fixup_arm_blx: 424 // These values don't encode the low two bits since they're always zero. 425 // Offset by 8 just as above. 426 if (const MCSymbolRefExpr *SRE = 427 dyn_cast<MCSymbolRefExpr>(Fixup.getValue())) 428 if (SRE->getKind() == MCSymbolRefExpr::VK_ARM_TLSCALL) 429 return 0; 430 return 0xffffff & ((Value - 8) >> 2); 431 case ARM::fixup_t2_uncondbranch: { 432 Value = Value - 4; 433 Value >>= 1; // Low bit is not encoded. 434 435 uint32_t out = 0; 436 bool I = Value & 0x800000; 437 bool J1 = Value & 0x400000; 438 bool J2 = Value & 0x200000; 439 J1 ^= I; 440 J2 ^= I; 441 442 out |= I << 26; // S bit 443 out |= !J1 << 13; // J1 bit 444 out |= !J2 << 11; // J2 bit 445 out |= (Value & 0x1FF800) << 5; // imm6 field 446 out |= (Value & 0x0007FF); // imm11 field 447 448 return swapHalfWords(out, IsLittleEndian); 449 } 450 case ARM::fixup_t2_condbranch: { 451 Value = Value - 4; 452 Value >>= 1; // Low bit is not encoded. 453 454 uint64_t out = 0; 455 out |= (Value & 0x80000) << 7; // S bit 456 out |= (Value & 0x40000) >> 7; // J2 bit 457 out |= (Value & 0x20000) >> 4; // J1 bit 458 out |= (Value & 0x1F800) << 5; // imm6 field 459 out |= (Value & 0x007FF); // imm11 field 460 461 return swapHalfWords(out, IsLittleEndian); 462 } 463 case ARM::fixup_arm_thumb_bl: { 464 // The value doesn't encode the low bit (always zero) and is offset by 465 // four. The 32-bit immediate value is encoded as 466 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0) 467 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S). 468 // The value is encoded into disjoint bit positions in the destination 469 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit, 470 // J = either J1 or J2 bit 471 // 472 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII 473 // 474 // Note that the halfwords are stored high first, low second; so we need 475 // to transpose the fixup value here to map properly. 476 uint32_t offset = (Value - 4) >> 1; 477 uint32_t signBit = (offset & 0x800000) >> 23; 478 uint32_t I1Bit = (offset & 0x400000) >> 22; 479 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit; 480 uint32_t I2Bit = (offset & 0x200000) >> 21; 481 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit; 482 uint32_t imm10Bits = (offset & 0x1FF800) >> 11; 483 uint32_t imm11Bits = (offset & 0x000007FF); 484 485 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits); 486 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) | 487 (uint16_t)imm11Bits); 488 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian); 489 } 490 case ARM::fixup_arm_thumb_blx: { 491 // The value doesn't encode the low two bits (always zero) and is offset by 492 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as 493 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00) 494 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S). 495 // The value is encoded into disjoint bit positions in the destination 496 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit, 497 // J = either J1 or J2 bit, 0 = zero. 498 // 499 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0 500 // 501 // Note that the halfwords are stored high first, low second; so we need 502 // to transpose the fixup value here to map properly. 503 uint32_t offset = (Value - 2) >> 2; 504 if (const MCSymbolRefExpr *SRE = 505 dyn_cast<MCSymbolRefExpr>(Fixup.getValue())) 506 if (SRE->getKind() == MCSymbolRefExpr::VK_ARM_TLSCALL) 507 offset = 0; 508 uint32_t signBit = (offset & 0x400000) >> 22; 509 uint32_t I1Bit = (offset & 0x200000) >> 21; 510 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit; 511 uint32_t I2Bit = (offset & 0x100000) >> 20; 512 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit; 513 uint32_t imm10HBits = (offset & 0xFFC00) >> 10; 514 uint32_t imm10LBits = (offset & 0x3FF); 515 516 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits); 517 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) | 518 ((uint16_t)imm10LBits) << 1); 519 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian); 520 } 521 case ARM::fixup_arm_thumb_cp: 522 // Offset by 4, and don't encode the low two bits. Two bytes of that 523 // 'off by 4' is implicitly handled by the half-word ordering of the 524 // Thumb encoding, so we only need to adjust by 2 here. 525 return ((Value - 2) >> 2) & 0xff; 526 case ARM::fixup_arm_thumb_cb: { 527 // Offset by 4 and don't encode the lower bit, which is always 0. 528 uint32_t Binary = (Value - 4) >> 1; 529 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3); 530 } 531 case ARM::fixup_arm_thumb_br: 532 // Offset by 4 and don't encode the lower bit, which is always 0. 533 return ((Value - 4) >> 1) & 0x7ff; 534 case ARM::fixup_arm_thumb_bcc: 535 // Offset by 4 and don't encode the lower bit, which is always 0. 536 return ((Value - 4) >> 1) & 0xff; 537 case ARM::fixup_arm_pcrel_10_unscaled: { 538 Value = Value - 8; // ARM fixups offset by an additional word and don't 539 // need to adjust for the half-word ordering. 540 bool isAdd = true; 541 if ((int64_t)Value < 0) { 542 Value = -Value; 543 isAdd = false; 544 } 545 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8]. 546 if (Ctx && Value >= 256) 547 Ctx->reportFatalError(Fixup.getLoc(), "out of range pc-relative fixup value"); 548 Value = (Value & 0xf) | ((Value & 0xf0) << 4); 549 return Value | (isAdd << 23); 550 } 551 case ARM::fixup_arm_pcrel_10: 552 Value = Value - 4; // ARM fixups offset by an additional word and don't 553 // need to adjust for the half-word ordering. 554 // Fall through. 555 case ARM::fixup_t2_pcrel_10: { 556 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 557 Value = Value - 4; 558 bool isAdd = true; 559 if ((int64_t)Value < 0) { 560 Value = -Value; 561 isAdd = false; 562 } 563 // These values don't encode the low two bits since they're always zero. 564 Value >>= 2; 565 if (Ctx && Value >= 256) 566 Ctx->reportFatalError(Fixup.getLoc(), "out of range pc-relative fixup value"); 567 Value |= isAdd << 23; 568 569 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords 570 // swapped. 571 if (Kind == ARM::fixup_t2_pcrel_10) 572 return swapHalfWords(Value, IsLittleEndian); 573 574 return Value; 575 } 576 } 577 } 578 579 void ARMAsmBackend::processFixupValue(const MCAssembler &Asm, 580 const MCAsmLayout &Layout, 581 const MCFixup &Fixup, 582 const MCFragment *DF, 583 const MCValue &Target, uint64_t &Value, 584 bool &IsResolved) { 585 const MCSymbolRefExpr *A = Target.getSymA(); 586 // Some fixups to thumb function symbols need the low bit (thumb bit) 587 // twiddled. 588 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 && 589 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 && 590 (unsigned)Fixup.getKind() != ARM::fixup_arm_adr_pcrel_12 && 591 (unsigned)Fixup.getKind() != ARM::fixup_thumb_adr_pcrel_10 && 592 (unsigned)Fixup.getKind() != ARM::fixup_t2_adr_pcrel_12 && 593 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) { 594 if (A) { 595 const MCSymbol &Sym = A->getSymbol(); 596 if (Asm.isThumbFunc(&Sym)) 597 Value |= 1; 598 } 599 } 600 // For Thumb1 BL instruction, it is possible to be a long jump between 601 // the basic blocks of the same function. Thus, we would like to resolve 602 // the offset when the destination has the same MCFragment. 603 if (A && (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl) { 604 const MCSymbol &Sym = A->getSymbol(); 605 IsResolved = (Sym.getFragment() == DF); 606 } 607 // We must always generate a relocation for BL/BLX instructions if we have 608 // a symbol to reference, as the linker relies on knowing the destination 609 // symbol's thumb-ness to get interworking right. 610 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx || 611 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx || 612 (unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl || 613 (unsigned)Fixup.getKind() == ARM::fixup_arm_condbl)) 614 IsResolved = false; 615 616 // Try to get the encoded value for the fixup as-if we're mapping it into 617 // the instruction. This allows adjustFixupValue() to issue a diagnostic 618 // if the value aren't invalid. 619 (void)adjustFixupValue(Fixup, Value, false, &Asm.getContext(), 620 IsLittleEndian); 621 } 622 623 /// getFixupKindNumBytes - The number of bytes the fixup may change. 624 static unsigned getFixupKindNumBytes(unsigned Kind) { 625 switch (Kind) { 626 default: 627 llvm_unreachable("Unknown fixup kind!"); 628 629 case FK_Data_1: 630 case ARM::fixup_arm_thumb_bcc: 631 case ARM::fixup_arm_thumb_cp: 632 case ARM::fixup_thumb_adr_pcrel_10: 633 return 1; 634 635 case FK_Data_2: 636 case ARM::fixup_arm_thumb_br: 637 case ARM::fixup_arm_thumb_cb: 638 return 2; 639 640 case ARM::fixup_arm_pcrel_10_unscaled: 641 case ARM::fixup_arm_ldst_pcrel_12: 642 case ARM::fixup_arm_pcrel_10: 643 case ARM::fixup_arm_adr_pcrel_12: 644 case ARM::fixup_arm_uncondbl: 645 case ARM::fixup_arm_condbl: 646 case ARM::fixup_arm_blx: 647 case ARM::fixup_arm_condbranch: 648 case ARM::fixup_arm_uncondbranch: 649 return 3; 650 651 case FK_Data_4: 652 case ARM::fixup_t2_ldst_pcrel_12: 653 case ARM::fixup_t2_condbranch: 654 case ARM::fixup_t2_uncondbranch: 655 case ARM::fixup_t2_pcrel_10: 656 case ARM::fixup_t2_adr_pcrel_12: 657 case ARM::fixup_arm_thumb_bl: 658 case ARM::fixup_arm_thumb_blx: 659 case ARM::fixup_arm_movt_hi16: 660 case ARM::fixup_arm_movw_lo16: 661 case ARM::fixup_t2_movt_hi16: 662 case ARM::fixup_t2_movw_lo16: 663 return 4; 664 665 case FK_SecRel_2: 666 return 2; 667 case FK_SecRel_4: 668 return 4; 669 } 670 } 671 672 /// getFixupKindContainerSizeBytes - The number of bytes of the 673 /// container involved in big endian. 674 static unsigned getFixupKindContainerSizeBytes(unsigned Kind) { 675 switch (Kind) { 676 default: 677 llvm_unreachable("Unknown fixup kind!"); 678 679 case FK_Data_1: 680 return 1; 681 case FK_Data_2: 682 return 2; 683 case FK_Data_4: 684 return 4; 685 686 case ARM::fixup_arm_thumb_bcc: 687 case ARM::fixup_arm_thumb_cp: 688 case ARM::fixup_thumb_adr_pcrel_10: 689 case ARM::fixup_arm_thumb_br: 690 case ARM::fixup_arm_thumb_cb: 691 // Instruction size is 2 bytes. 692 return 2; 693 694 case ARM::fixup_arm_pcrel_10_unscaled: 695 case ARM::fixup_arm_ldst_pcrel_12: 696 case ARM::fixup_arm_pcrel_10: 697 case ARM::fixup_arm_adr_pcrel_12: 698 case ARM::fixup_arm_uncondbl: 699 case ARM::fixup_arm_condbl: 700 case ARM::fixup_arm_blx: 701 case ARM::fixup_arm_condbranch: 702 case ARM::fixup_arm_uncondbranch: 703 case ARM::fixup_t2_ldst_pcrel_12: 704 case ARM::fixup_t2_condbranch: 705 case ARM::fixup_t2_uncondbranch: 706 case ARM::fixup_t2_pcrel_10: 707 case ARM::fixup_t2_adr_pcrel_12: 708 case ARM::fixup_arm_thumb_bl: 709 case ARM::fixup_arm_thumb_blx: 710 case ARM::fixup_arm_movt_hi16: 711 case ARM::fixup_arm_movw_lo16: 712 case ARM::fixup_t2_movt_hi16: 713 case ARM::fixup_t2_movw_lo16: 714 // Instruction size is 4 bytes. 715 return 4; 716 } 717 } 718 719 void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 720 unsigned DataSize, uint64_t Value, 721 bool IsPCRel) const { 722 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 723 Value = adjustFixupValue(Fixup, Value, IsPCRel, nullptr, IsLittleEndian); 724 if (!Value) 725 return; // Doesn't change encoding. 726 727 unsigned Offset = Fixup.getOffset(); 728 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!"); 729 730 // Used to point to big endian bytes. 731 unsigned FullSizeBytes; 732 if (!IsLittleEndian) { 733 FullSizeBytes = getFixupKindContainerSizeBytes(Fixup.getKind()); 734 assert((Offset + FullSizeBytes) <= DataSize && "Invalid fixup size!"); 735 assert(NumBytes <= FullSizeBytes && "Invalid fixup size!"); 736 } 737 738 // For each byte of the fragment that the fixup touches, mask in the bits from 739 // the fixup value. The Value has been "split up" into the appropriate 740 // bitfields above. 741 for (unsigned i = 0; i != NumBytes; ++i) { 742 unsigned Idx = IsLittleEndian ? i : (FullSizeBytes - 1 - i); 743 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff); 744 } 745 } 746 747 static MachO::CPUSubTypeARM getMachOSubTypeFromArch(StringRef Arch) { 748 unsigned AK = ARM::parseArch(Arch); 749 switch (AK) { 750 default: 751 return MachO::CPU_SUBTYPE_ARM_V7; 752 case ARM::AK_ARMV4T: 753 return MachO::CPU_SUBTYPE_ARM_V4T; 754 case ARM::AK_ARMV6: 755 case ARM::AK_ARMV6K: 756 return MachO::CPU_SUBTYPE_ARM_V6; 757 case ARM::AK_ARMV5: 758 return MachO::CPU_SUBTYPE_ARM_V5; 759 case ARM::AK_ARMV5T: 760 case ARM::AK_ARMV5E: 761 case ARM::AK_ARMV5TE: 762 case ARM::AK_ARMV5TEJ: 763 return MachO::CPU_SUBTYPE_ARM_V5TEJ; 764 case ARM::AK_ARMV7: 765 return MachO::CPU_SUBTYPE_ARM_V7; 766 case ARM::AK_ARMV7S: 767 return MachO::CPU_SUBTYPE_ARM_V7S; 768 case ARM::AK_ARMV7K: 769 return MachO::CPU_SUBTYPE_ARM_V7K; 770 case ARM::AK_ARMV6M: 771 case ARM::AK_ARMV6SM: 772 return MachO::CPU_SUBTYPE_ARM_V6M; 773 case ARM::AK_ARMV7M: 774 return MachO::CPU_SUBTYPE_ARM_V7M; 775 case ARM::AK_ARMV7EM: 776 return MachO::CPU_SUBTYPE_ARM_V7EM; 777 } 778 } 779 780 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, 781 const MCRegisterInfo &MRI, 782 const Triple &TheTriple, StringRef CPU, 783 bool isLittle) { 784 switch (TheTriple.getObjectFormat()) { 785 default: 786 llvm_unreachable("unsupported object format"); 787 case Triple::MachO: { 788 MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TheTriple.getArchName()); 789 return new ARMAsmBackendDarwin(T, TheTriple, CS); 790 } 791 case Triple::COFF: 792 assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported"); 793 return new ARMAsmBackendWinCOFF(T, TheTriple); 794 case Triple::ELF: 795 assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target"); 796 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); 797 return new ARMAsmBackendELF(T, TheTriple, OSABI, isLittle); 798 } 799 } 800 801 MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T, 802 const MCRegisterInfo &MRI, 803 const Triple &TT, StringRef CPU) { 804 return createARMAsmBackend(T, MRI, TT, CPU, true); 805 } 806 807 MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T, 808 const MCRegisterInfo &MRI, 809 const Triple &TT, StringRef CPU) { 810 return createARMAsmBackend(T, MRI, TT, CPU, false); 811 } 812 813 MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T, 814 const MCRegisterInfo &MRI, 815 const Triple &TT, StringRef CPU) { 816 return createARMAsmBackend(T, MRI, TT, CPU, true); 817 } 818 819 MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T, 820 const MCRegisterInfo &MRI, 821 const Triple &TT, StringRef CPU) { 822 return createARMAsmBackend(T, MRI, TT, CPU, false); 823 } 824