1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/ARMMCTargetDesc.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMFixupKinds.h" 13 #include "MCTargetDesc/ARMAddressingModes.h" 14 #include "llvm/ADT/Twine.h" 15 #include "llvm/MC/MCAssembler.h" 16 #include "llvm/MC/MCDirectives.h" 17 #include "llvm/MC/MCELFObjectWriter.h" 18 #include "llvm/MC/MCExpr.h" 19 #include "llvm/MC/MCMachObjectWriter.h" 20 #include "llvm/MC/MCObjectWriter.h" 21 #include "llvm/MC/MCSectionELF.h" 22 #include "llvm/MC/MCSectionMachO.h" 23 #include "llvm/MC/MCAsmBackend.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/Object/MachOFormat.h" 26 #include "llvm/Support/ELF.h" 27 #include "llvm/Support/ErrorHandling.h" 28 #include "llvm/Support/raw_ostream.h" 29 using namespace llvm; 30 31 namespace { 32 class ARMELFObjectWriter : public MCELFObjectTargetWriter { 33 public: 34 ARMELFObjectWriter(Triple::OSType OSType) 35 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSType, ELF::EM_ARM, 36 /*HasRelocationAddend*/ false) {} 37 }; 38 39 class ARMAsmBackend : public MCAsmBackend { 40 const MCSubtargetInfo* STI; 41 bool isThumbMode; // Currently emitting Thumb code. 42 public: 43 ARMAsmBackend(const Target &T, const StringRef TT) 44 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")), 45 isThumbMode(TT.startswith("thumb")) {} 46 47 ~ARMAsmBackend() { 48 delete STI; 49 } 50 51 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; } 52 53 bool hasNOP() const { 54 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0; 55 } 56 57 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { 58 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = { 59 // This table *must* be in the order that the fixup_* kinds are defined in 60 // ARMFixupKinds.h. 61 // 62 // Name Offset (bits) Size (bits) Flags 63 { "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, 64 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 65 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 66 { "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, 67 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 68 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 69 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel | 70 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 71 { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, 72 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 73 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 74 { "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 75 { "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 76 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 77 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 78 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 79 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 80 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 81 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 82 { "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel }, 83 { "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel }, 84 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19. 85 { "fixup_arm_movt_hi16", 0, 20, 0 }, 86 { "fixup_arm_movw_lo16", 0, 20, 0 }, 87 { "fixup_t2_movt_hi16", 0, 20, 0 }, 88 { "fixup_t2_movw_lo16", 0, 20, 0 }, 89 { "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 90 { "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 91 { "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 92 { "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 93 }; 94 95 if (Kind < FirstTargetFixupKind) 96 return MCAsmBackend::getFixupKindInfo(Kind); 97 98 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 99 "Invalid kind!"); 100 return Infos[Kind - FirstTargetFixupKind]; 101 } 102 103 bool MayNeedRelaxation(const MCInst &Inst) const; 104 105 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const; 106 107 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const; 108 109 void HandleAssemblerFlag(MCAssemblerFlag Flag) { 110 switch (Flag) { 111 default: break; 112 case MCAF_Code16: 113 setIsThumb(true); 114 break; 115 case MCAF_Code32: 116 setIsThumb(false); 117 break; 118 } 119 } 120 121 unsigned getPointerSize() const { return 4; } 122 bool isThumb() const { return isThumbMode; } 123 void setIsThumb(bool it) { isThumbMode = it; } 124 }; 125 } // end anonymous namespace 126 127 bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const { 128 // FIXME: Thumb targets, different move constant targets.. 129 return false; 130 } 131 132 void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const { 133 assert(0 && "ARMAsmBackend::RelaxInstruction() unimplemented"); 134 return; 135 } 136 137 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const { 138 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8 139 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP 140 const uint32_t ARMv4_NopEncoding = 0xe1a0000; // using MOV r0,r0 141 const uint32_t ARMv6T2_NopEncoding = 0xe3207800; // NOP 142 if (isThumb()) { 143 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding 144 : Thumb1_16bitNopEncoding; 145 uint64_t NumNops = Count / 2; 146 for (uint64_t i = 0; i != NumNops; ++i) 147 OW->Write16(nopEncoding); 148 if (Count & 1) 149 OW->Write8(0); 150 return true; 151 } 152 // ARM mode 153 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding 154 : ARMv4_NopEncoding; 155 uint64_t NumNops = Count / 4; 156 for (uint64_t i = 0; i != NumNops; ++i) 157 OW->Write32(nopEncoding); 158 // FIXME: should this function return false when unable to write exactly 159 // 'Count' bytes with NOP encodings? 160 switch (Count % 4) { 161 default: break; // No leftover bytes to write 162 case 1: OW->Write8(0); break; 163 case 2: OW->Write16(0); break; 164 case 3: OW->Write16(0); OW->Write8(0xa0); break; 165 } 166 167 return true; 168 } 169 170 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { 171 switch (Kind) { 172 default: 173 llvm_unreachable("Unknown fixup kind!"); 174 case FK_Data_1: 175 case FK_Data_2: 176 case FK_Data_4: 177 return Value; 178 case ARM::fixup_arm_movt_hi16: 179 Value >>= 16; 180 // Fallthrough 181 case ARM::fixup_arm_movw_lo16: 182 case ARM::fixup_arm_movt_hi16_pcrel: 183 case ARM::fixup_arm_movw_lo16_pcrel: { 184 unsigned Hi4 = (Value & 0xF000) >> 12; 185 unsigned Lo12 = Value & 0x0FFF; 186 assert ((((int64_t)Value) >= -0x8000) && (((int64_t)Value) <= 0x7fff) && 187 "Out of range pc-relative fixup value!"); 188 // inst{19-16} = Hi4; 189 // inst{11-0} = Lo12; 190 Value = (Hi4 << 16) | (Lo12); 191 return Value; 192 } 193 case ARM::fixup_t2_movt_hi16: 194 Value >>= 16; 195 // Fallthrough 196 case ARM::fixup_t2_movw_lo16: 197 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like 198 // the other hi16 fixup? 199 case ARM::fixup_t2_movw_lo16_pcrel: { 200 unsigned Hi4 = (Value & 0xF000) >> 12; 201 unsigned i = (Value & 0x800) >> 11; 202 unsigned Mid3 = (Value & 0x700) >> 8; 203 unsigned Lo8 = Value & 0x0FF; 204 // inst{19-16} = Hi4; 205 // inst{26} = i; 206 // inst{14-12} = Mid3; 207 // inst{7-0} = Lo8; 208 // The value comes in as the whole thing, not just the portion required 209 // for this fixup, so we need to mask off the bits not handled by this 210 // portion (lo vs. hi). 211 Value &= 0xffff; 212 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8); 213 uint64_t swapped = (Value & 0xFFFF0000) >> 16; 214 swapped |= (Value & 0x0000FFFF) << 16; 215 return swapped; 216 } 217 case ARM::fixup_arm_ldst_pcrel_12: 218 // ARM PC-relative values are offset by 8. 219 Value -= 4; 220 // FALLTHROUGH 221 case ARM::fixup_t2_ldst_pcrel_12: { 222 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 223 Value -= 4; 224 bool isAdd = true; 225 if ((int64_t)Value < 0) { 226 Value = -Value; 227 isAdd = false; 228 } 229 assert ((Value < 4096) && "Out of range pc-relative fixup value!"); 230 Value |= isAdd << 23; 231 232 // Same addressing mode as fixup_arm_pcrel_10, 233 // but with 16-bit halfwords swapped. 234 if (Kind == ARM::fixup_t2_ldst_pcrel_12) { 235 uint64_t swapped = (Value & 0xFFFF0000) >> 16; 236 swapped |= (Value & 0x0000FFFF) << 16; 237 return swapped; 238 } 239 240 return Value; 241 } 242 case ARM::fixup_thumb_adr_pcrel_10: 243 return ((Value - 4) >> 2) & 0xff; 244 case ARM::fixup_arm_adr_pcrel_12: { 245 // ARM PC-relative values are offset by 8. 246 Value -= 8; 247 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 248 if ((int64_t)Value < 0) { 249 Value = -Value; 250 opc = 2; // 0b0010 251 } 252 assert(ARM_AM::getSOImmVal(Value) != -1 && 253 "Out of range pc-relative fixup value!"); 254 // Encode the immediate and shift the opcode into place. 255 return ARM_AM::getSOImmVal(Value) | (opc << 21); 256 } 257 258 case ARM::fixup_t2_adr_pcrel_12: { 259 Value -= 4; 260 unsigned opc = 0; 261 if ((int64_t)Value < 0) { 262 Value = -Value; 263 opc = 5; 264 } 265 266 uint32_t out = (opc << 21); 267 out |= (Value & 0x800) << 15; 268 out |= (Value & 0x700) << 4; 269 out |= (Value & 0x0FF); 270 271 uint64_t swapped = (out & 0xFFFF0000) >> 16; 272 swapped |= (out & 0x0000FFFF) << 16; 273 return swapped; 274 } 275 276 case ARM::fixup_arm_condbranch: 277 case ARM::fixup_arm_uncondbranch: 278 // These values don't encode the low two bits since they're always zero. 279 // Offset by 8 just as above. 280 return 0xffffff & ((Value - 8) >> 2); 281 case ARM::fixup_t2_uncondbranch: { 282 Value = Value - 4; 283 Value >>= 1; // Low bit is not encoded. 284 285 uint32_t out = 0; 286 bool I = Value & 0x800000; 287 bool J1 = Value & 0x400000; 288 bool J2 = Value & 0x200000; 289 J1 ^= I; 290 J2 ^= I; 291 292 out |= I << 26; // S bit 293 out |= !J1 << 13; // J1 bit 294 out |= !J2 << 11; // J2 bit 295 out |= (Value & 0x1FF800) << 5; // imm6 field 296 out |= (Value & 0x0007FF); // imm11 field 297 298 uint64_t swapped = (out & 0xFFFF0000) >> 16; 299 swapped |= (out & 0x0000FFFF) << 16; 300 return swapped; 301 } 302 case ARM::fixup_t2_condbranch: { 303 Value = Value - 4; 304 Value >>= 1; // Low bit is not encoded. 305 306 uint64_t out = 0; 307 out |= (Value & 0x80000) << 7; // S bit 308 out |= (Value & 0x40000) >> 7; // J2 bit 309 out |= (Value & 0x20000) >> 4; // J1 bit 310 out |= (Value & 0x1F800) << 5; // imm6 field 311 out |= (Value & 0x007FF); // imm11 field 312 313 uint32_t swapped = (out & 0xFFFF0000) >> 16; 314 swapped |= (out & 0x0000FFFF) << 16; 315 return swapped; 316 } 317 case ARM::fixup_arm_thumb_bl: { 318 // The value doesn't encode the low bit (always zero) and is offset by 319 // four. The value is encoded into disjoint bit positions in the destination 320 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit 321 // 322 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII 323 // 324 // Note that the halfwords are stored high first, low second; so we need 325 // to transpose the fixup value here to map properly. 326 unsigned isNeg = (int64_t(Value - 4) < 0) ? 1 : 0; 327 uint32_t Binary = 0; 328 Value = 0x3fffff & ((Value - 4) >> 1); 329 Binary = (Value & 0x7ff) << 16; // Low imm11 value. 330 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value. 331 Binary |= isNeg << 10; // Sign bit. 332 return Binary; 333 } 334 case ARM::fixup_arm_thumb_blx: { 335 // The value doesn't encode the low two bits (always zero) and is offset by 336 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit 337 // positions in the destination opcode. x = unchanged, I = immediate value 338 // bit, S = sign extension bit, 0 = zero. 339 // 340 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0 341 // 342 // Note that the halfwords are stored high first, low second; so we need 343 // to transpose the fixup value here to map properly. 344 unsigned isNeg = (int64_t(Value-4) < 0) ? 1 : 0; 345 uint32_t Binary = 0; 346 Value = 0xfffff & ((Value - 2) >> 2); 347 Binary = (Value & 0x3ff) << 17; // Low imm10L value. 348 Binary |= (Value & 0xffc00) >> 10; // High imm10H value. 349 Binary |= isNeg << 10; // Sign bit. 350 return Binary; 351 } 352 case ARM::fixup_arm_thumb_cp: 353 // Offset by 4, and don't encode the low two bits. Two bytes of that 354 // 'off by 4' is implicitly handled by the half-word ordering of the 355 // Thumb encoding, so we only need to adjust by 2 here. 356 return ((Value - 2) >> 2) & 0xff; 357 case ARM::fixup_arm_thumb_cb: { 358 // Offset by 4 and don't encode the lower bit, which is always 0. 359 uint32_t Binary = (Value - 4) >> 1; 360 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3); 361 } 362 case ARM::fixup_arm_thumb_br: 363 // Offset by 4 and don't encode the lower bit, which is always 0. 364 return ((Value - 4) >> 1) & 0x7ff; 365 case ARM::fixup_arm_thumb_bcc: 366 // Offset by 4 and don't encode the lower bit, which is always 0. 367 return ((Value - 4) >> 1) & 0xff; 368 case ARM::fixup_arm_pcrel_10: 369 Value = Value - 4; // ARM fixups offset by an additional word and don't 370 // need to adjust for the half-word ordering. 371 // Fall through. 372 case ARM::fixup_t2_pcrel_10: { 373 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 374 Value = Value - 4; 375 bool isAdd = true; 376 if ((int64_t)Value < 0) { 377 Value = -Value; 378 isAdd = false; 379 } 380 // These values don't encode the low two bits since they're always zero. 381 Value >>= 2; 382 assert ((Value < 256) && "Out of range pc-relative fixup value!"); 383 Value |= isAdd << 23; 384 385 // Same addressing mode as fixup_arm_pcrel_10, 386 // but with 16-bit halfwords swapped. 387 if (Kind == ARM::fixup_t2_pcrel_10) { 388 uint32_t swapped = (Value & 0xFFFF0000) >> 16; 389 swapped |= (Value & 0x0000FFFF) << 16; 390 return swapped; 391 } 392 393 return Value; 394 } 395 } 396 } 397 398 namespace { 399 400 // FIXME: This should be in a separate file. 401 // ELF is an ELF of course... 402 class ELFARMAsmBackend : public ARMAsmBackend { 403 public: 404 Triple::OSType OSType; 405 ELFARMAsmBackend(const Target &T, const StringRef TT, 406 Triple::OSType _OSType) 407 : ARMAsmBackend(T, TT), OSType(_OSType) { } 408 409 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 410 uint64_t Value) const; 411 412 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 413 return createELFObjectWriter(new ARMELFObjectWriter(OSType), OS, 414 /*IsLittleEndian*/ true); 415 } 416 }; 417 418 // FIXME: Raise this to share code between Darwin and ELF. 419 void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data, 420 unsigned DataSize, uint64_t Value) const { 421 unsigned NumBytes = 4; // FIXME: 2 for Thumb 422 Value = adjustFixupValue(Fixup.getKind(), Value); 423 if (!Value) return; // Doesn't change encoding. 424 425 unsigned Offset = Fixup.getOffset(); 426 427 // For each byte of the fragment that the fixup touches, mask in the bits from 428 // the fixup value. The Value has been "split up" into the appropriate 429 // bitfields above. 430 for (unsigned i = 0; i != NumBytes; ++i) 431 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 432 } 433 434 // FIXME: This should be in a separate file. 435 class DarwinARMAsmBackend : public ARMAsmBackend { 436 public: 437 const object::mach::CPUSubtypeARM Subtype; 438 DarwinARMAsmBackend(const Target &T, const StringRef TT, 439 object::mach::CPUSubtypeARM st) 440 : ARMAsmBackend(T, TT), Subtype(st) { } 441 442 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 443 return createARMMachObjectWriter(OS, /*Is64Bit=*/false, 444 object::mach::CTM_ARM, 445 Subtype); 446 } 447 448 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 449 uint64_t Value) const; 450 451 virtual bool doesSectionRequireSymbols(const MCSection &Section) const { 452 return false; 453 } 454 }; 455 456 /// getFixupKindNumBytes - The number of bytes the fixup may change. 457 static unsigned getFixupKindNumBytes(unsigned Kind) { 458 switch (Kind) { 459 default: 460 llvm_unreachable("Unknown fixup kind!"); 461 462 case FK_Data_1: 463 case ARM::fixup_arm_thumb_bcc: 464 case ARM::fixup_arm_thumb_cp: 465 case ARM::fixup_thumb_adr_pcrel_10: 466 return 1; 467 468 case FK_Data_2: 469 case ARM::fixup_arm_thumb_br: 470 case ARM::fixup_arm_thumb_cb: 471 return 2; 472 473 case ARM::fixup_arm_ldst_pcrel_12: 474 case ARM::fixup_arm_pcrel_10: 475 case ARM::fixup_arm_adr_pcrel_12: 476 case ARM::fixup_arm_condbranch: 477 case ARM::fixup_arm_uncondbranch: 478 return 3; 479 480 case FK_Data_4: 481 case ARM::fixup_t2_ldst_pcrel_12: 482 case ARM::fixup_t2_condbranch: 483 case ARM::fixup_t2_uncondbranch: 484 case ARM::fixup_t2_pcrel_10: 485 case ARM::fixup_t2_adr_pcrel_12: 486 case ARM::fixup_arm_thumb_bl: 487 case ARM::fixup_arm_thumb_blx: 488 case ARM::fixup_arm_movt_hi16: 489 case ARM::fixup_arm_movw_lo16: 490 case ARM::fixup_arm_movt_hi16_pcrel: 491 case ARM::fixup_arm_movw_lo16_pcrel: 492 case ARM::fixup_t2_movt_hi16: 493 case ARM::fixup_t2_movw_lo16: 494 case ARM::fixup_t2_movt_hi16_pcrel: 495 case ARM::fixup_t2_movw_lo16_pcrel: 496 return 4; 497 } 498 } 499 500 void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data, 501 unsigned DataSize, uint64_t Value) const { 502 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 503 Value = adjustFixupValue(Fixup.getKind(), Value); 504 if (!Value) return; // Doesn't change encoding. 505 506 unsigned Offset = Fixup.getOffset(); 507 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!"); 508 509 // For each byte of the fragment that the fixup touches, mask in the 510 // bits from the fixup value. 511 for (unsigned i = 0; i != NumBytes; ++i) 512 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 513 } 514 515 } // end anonymous namespace 516 517 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, StringRef TT) { 518 Triple TheTriple(TT); 519 520 if (TheTriple.isOSDarwin()) { 521 if (TheTriple.getArchName() == "armv4t" || 522 TheTriple.getArchName() == "thumbv4t") 523 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V4T); 524 else if (TheTriple.getArchName() == "armv5e" || 525 TheTriple.getArchName() == "thumbv5e") 526 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V5TEJ); 527 else if (TheTriple.getArchName() == "armv6" || 528 TheTriple.getArchName() == "thumbv6") 529 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V6); 530 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7); 531 } 532 533 if (TheTriple.isOSWindows()) 534 assert(0 && "Windows not supported on ARM"); 535 536 return new ELFARMAsmBackend(T, TT, Triple(TT).getOS()); 537 } 538