1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/ARMMCTargetDesc.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "MCTargetDesc/ARMBaseInfo.h" 13 #include "MCTargetDesc/ARMFixupKinds.h" 14 #include "llvm/ADT/StringSwitch.h" 15 #include "llvm/MC/MCAsmBackend.h" 16 #include "llvm/MC/MCAssembler.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDirectives.h" 19 #include "llvm/MC/MCELFObjectWriter.h" 20 #include "llvm/MC/MCExpr.h" 21 #include "llvm/MC/MCFixupKindInfo.h" 22 #include "llvm/MC/MCMachObjectWriter.h" 23 #include "llvm/MC/MCObjectWriter.h" 24 #include "llvm/MC/MCSectionELF.h" 25 #include "llvm/MC/MCSectionMachO.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/MC/MCValue.h" 28 #include "llvm/Support/ELF.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/MachO.h" 31 #include "llvm/Support/raw_ostream.h" 32 using namespace llvm; 33 34 namespace { 35 class ARMELFObjectWriter : public MCELFObjectTargetWriter { 36 public: 37 ARMELFObjectWriter(uint8_t OSABI) 38 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM, 39 /*HasRelocationAddend*/ false) {} 40 }; 41 42 class ARMAsmBackend : public MCAsmBackend { 43 const MCSubtargetInfo* STI; 44 bool isThumbMode; // Currently emitting Thumb code. 45 public: 46 ARMAsmBackend(const Target &T, const StringRef TT) 47 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")), 48 isThumbMode(TT.startswith("thumb")) {} 49 50 ~ARMAsmBackend() { 51 delete STI; 52 } 53 54 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; } 55 56 bool hasNOP() const { 57 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0; 58 } 59 60 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { 61 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = { 62 // This table *must* be in the order that the fixup_* kinds are defined in 63 // ARMFixupKinds.h. 64 // 65 // Name Offset (bits) Size (bits) Flags 66 { "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 67 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 68 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 69 { "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 70 { "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 71 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 72 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 73 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel | 74 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 75 { "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 76 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 77 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 78 { "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 79 { "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 80 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 81 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 82 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 83 { "fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 84 { "fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 85 { "fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 86 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 87 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 88 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 89 { "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel | 90 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 91 { "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel }, 92 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19. 93 { "fixup_arm_movt_hi16", 0, 20, 0 }, 94 { "fixup_arm_movw_lo16", 0, 20, 0 }, 95 { "fixup_t2_movt_hi16", 0, 20, 0 }, 96 { "fixup_t2_movw_lo16", 0, 20, 0 }, 97 { "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 98 { "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 99 { "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 100 { "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 101 }; 102 103 if (Kind < FirstTargetFixupKind) 104 return MCAsmBackend::getFixupKindInfo(Kind); 105 106 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 107 "Invalid kind!"); 108 return Infos[Kind - FirstTargetFixupKind]; 109 } 110 111 /// processFixupValue - Target hook to process the literal value of a fixup 112 /// if necessary. 113 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout, 114 const MCFixup &Fixup, const MCFragment *DF, 115 MCValue &Target, uint64_t &Value, 116 bool &IsResolved); 117 118 119 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 120 uint64_t Value) const; 121 122 bool mayNeedRelaxation(const MCInst &Inst) const; 123 124 bool fixupNeedsRelaxation(const MCFixup &Fixup, 125 uint64_t Value, 126 const MCRelaxableFragment *DF, 127 const MCAsmLayout &Layout) const; 128 129 void relaxInstruction(const MCInst &Inst, MCInst &Res) const; 130 131 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const; 132 133 void handleAssemblerFlag(MCAssemblerFlag Flag) { 134 switch (Flag) { 135 default: break; 136 case MCAF_Code16: 137 setIsThumb(true); 138 break; 139 case MCAF_Code32: 140 setIsThumb(false); 141 break; 142 } 143 } 144 145 unsigned getPointerSize() const { return 4; } 146 bool isThumb() const { return isThumbMode; } 147 void setIsThumb(bool it) { isThumbMode = it; } 148 }; 149 } // end anonymous namespace 150 151 static unsigned getRelaxedOpcode(unsigned Op) { 152 switch (Op) { 153 default: return Op; 154 case ARM::tBcc: return ARM::t2Bcc; 155 case ARM::tLDRpci: return ARM::t2LDRpci; 156 case ARM::tADR: return ARM::t2ADR; 157 case ARM::tB: return ARM::t2B; 158 case ARM::tCBZ: return ARM::tHINT; 159 case ARM::tCBNZ: return ARM::tHINT; 160 } 161 } 162 163 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 164 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode()) 165 return true; 166 return false; 167 } 168 169 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, 170 uint64_t Value, 171 const MCRelaxableFragment *DF, 172 const MCAsmLayout &Layout) const { 173 switch ((unsigned)Fixup.getKind()) { 174 case ARM::fixup_arm_thumb_br: { 175 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the 176 // low bit being an implied zero. There's an implied +4 offset for the 177 // branch, so we adjust the other way here to determine what's 178 // encodable. 179 // 180 // Relax if the value is too big for a (signed) i8. 181 int64_t Offset = int64_t(Value) - 4; 182 return Offset > 2046 || Offset < -2048; 183 } 184 case ARM::fixup_arm_thumb_bcc: { 185 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the 186 // low bit being an implied zero. There's an implied +4 offset for the 187 // branch, so we adjust the other way here to determine what's 188 // encodable. 189 // 190 // Relax if the value is too big for a (signed) i8. 191 int64_t Offset = int64_t(Value) - 4; 192 return Offset > 254 || Offset < -256; 193 } 194 case ARM::fixup_thumb_adr_pcrel_10: 195 case ARM::fixup_arm_thumb_cp: { 196 // If the immediate is negative, greater than 1020, or not a multiple 197 // of four, the wide version of the instruction must be used. 198 int64_t Offset = int64_t(Value) - 4; 199 return Offset > 1020 || Offset < 0 || Offset & 3; 200 } 201 case ARM::fixup_arm_thumb_cb: 202 // If we have a Thumb CBZ or CBNZ instruction and its target is the next 203 // instruction it is is actually out of range for the instruction. 204 // It will be changed to a NOP. 205 int64_t Offset = (Value & ~1); 206 return Offset == 2; 207 } 208 llvm_unreachable("Unexpected fixup kind in fixupNeedsRelaxation()!"); 209 } 210 211 void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const { 212 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode()); 213 214 // Sanity check w/ diagnostic if we get here w/ a bogus instruction. 215 if (RelaxedOp == Inst.getOpcode()) { 216 SmallString<256> Tmp; 217 raw_svector_ostream OS(Tmp); 218 Inst.dump_pretty(OS); 219 OS << "\n"; 220 report_fatal_error("unexpected instruction to relax: " + OS.str()); 221 } 222 223 // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we 224 // have to change the operands too. 225 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) && 226 RelaxedOp == ARM::tHINT) { 227 Res.setOpcode(RelaxedOp); 228 Res.addOperand(MCOperand::CreateImm(0)); 229 Res.addOperand(MCOperand::CreateImm(14)); 230 Res.addOperand(MCOperand::CreateReg(0)); 231 return; 232 } 233 234 // The rest of instructions we're relaxing have the same operands. 235 // We just need to update to the proper opcode. 236 Res = Inst; 237 Res.setOpcode(RelaxedOp); 238 } 239 240 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 241 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8 242 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP 243 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0 244 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP 245 if (isThumb()) { 246 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding 247 : Thumb1_16bitNopEncoding; 248 uint64_t NumNops = Count / 2; 249 for (uint64_t i = 0; i != NumNops; ++i) 250 OW->Write16(nopEncoding); 251 if (Count & 1) 252 OW->Write8(0); 253 return true; 254 } 255 // ARM mode 256 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding 257 : ARMv4_NopEncoding; 258 uint64_t NumNops = Count / 4; 259 for (uint64_t i = 0; i != NumNops; ++i) 260 OW->Write32(nopEncoding); 261 // FIXME: should this function return false when unable to write exactly 262 // 'Count' bytes with NOP encodings? 263 switch (Count % 4) { 264 default: break; // No leftover bytes to write 265 case 1: OW->Write8(0); break; 266 case 2: OW->Write16(0); break; 267 case 3: OW->Write16(0); OW->Write8(0xa0); break; 268 } 269 270 return true; 271 } 272 273 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, 274 MCContext *Ctx = NULL) { 275 unsigned Kind = Fixup.getKind(); 276 switch (Kind) { 277 default: 278 llvm_unreachable("Unknown fixup kind!"); 279 case FK_Data_1: 280 case FK_Data_2: 281 case FK_Data_4: 282 return Value; 283 case ARM::fixup_arm_movt_hi16: 284 Value >>= 16; 285 // Fallthrough 286 case ARM::fixup_arm_movw_lo16: 287 case ARM::fixup_arm_movt_hi16_pcrel: 288 case ARM::fixup_arm_movw_lo16_pcrel: { 289 unsigned Hi4 = (Value & 0xF000) >> 12; 290 unsigned Lo12 = Value & 0x0FFF; 291 // inst{19-16} = Hi4; 292 // inst{11-0} = Lo12; 293 Value = (Hi4 << 16) | (Lo12); 294 return Value; 295 } 296 case ARM::fixup_t2_movt_hi16: 297 Value >>= 16; 298 // Fallthrough 299 case ARM::fixup_t2_movw_lo16: 300 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like 301 // the other hi16 fixup? 302 case ARM::fixup_t2_movw_lo16_pcrel: { 303 unsigned Hi4 = (Value & 0xF000) >> 12; 304 unsigned i = (Value & 0x800) >> 11; 305 unsigned Mid3 = (Value & 0x700) >> 8; 306 unsigned Lo8 = Value & 0x0FF; 307 // inst{19-16} = Hi4; 308 // inst{26} = i; 309 // inst{14-12} = Mid3; 310 // inst{7-0} = Lo8; 311 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8); 312 uint64_t swapped = (Value & 0xFFFF0000) >> 16; 313 swapped |= (Value & 0x0000FFFF) << 16; 314 return swapped; 315 } 316 case ARM::fixup_arm_ldst_pcrel_12: 317 // ARM PC-relative values are offset by 8. 318 Value -= 4; 319 // FALLTHROUGH 320 case ARM::fixup_t2_ldst_pcrel_12: { 321 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 322 Value -= 4; 323 bool isAdd = true; 324 if ((int64_t)Value < 0) { 325 Value = -Value; 326 isAdd = false; 327 } 328 if (Ctx && Value >= 4096) 329 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value"); 330 Value |= isAdd << 23; 331 332 // Same addressing mode as fixup_arm_pcrel_10, 333 // but with 16-bit halfwords swapped. 334 if (Kind == ARM::fixup_t2_ldst_pcrel_12) { 335 uint64_t swapped = (Value & 0xFFFF0000) >> 16; 336 swapped |= (Value & 0x0000FFFF) << 16; 337 return swapped; 338 } 339 340 return Value; 341 } 342 case ARM::fixup_thumb_adr_pcrel_10: 343 return ((Value - 4) >> 2) & 0xff; 344 case ARM::fixup_arm_adr_pcrel_12: { 345 // ARM PC-relative values are offset by 8. 346 Value -= 8; 347 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 348 if ((int64_t)Value < 0) { 349 Value = -Value; 350 opc = 2; // 0b0010 351 } 352 if (Ctx && ARM_AM::getSOImmVal(Value) == -1) 353 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value"); 354 // Encode the immediate and shift the opcode into place. 355 return ARM_AM::getSOImmVal(Value) | (opc << 21); 356 } 357 358 case ARM::fixup_t2_adr_pcrel_12: { 359 Value -= 4; 360 unsigned opc = 0; 361 if ((int64_t)Value < 0) { 362 Value = -Value; 363 opc = 5; 364 } 365 366 uint32_t out = (opc << 21); 367 out |= (Value & 0x800) << 15; 368 out |= (Value & 0x700) << 4; 369 out |= (Value & 0x0FF); 370 371 uint64_t swapped = (out & 0xFFFF0000) >> 16; 372 swapped |= (out & 0x0000FFFF) << 16; 373 return swapped; 374 } 375 376 case ARM::fixup_arm_condbranch: 377 case ARM::fixup_arm_uncondbranch: 378 case ARM::fixup_arm_uncondbl: 379 case ARM::fixup_arm_condbl: 380 case ARM::fixup_arm_blx: 381 // These values don't encode the low two bits since they're always zero. 382 // Offset by 8 just as above. 383 return 0xffffff & ((Value - 8) >> 2); 384 case ARM::fixup_t2_uncondbranch: { 385 Value = Value - 4; 386 Value >>= 1; // Low bit is not encoded. 387 388 uint32_t out = 0; 389 bool I = Value & 0x800000; 390 bool J1 = Value & 0x400000; 391 bool J2 = Value & 0x200000; 392 J1 ^= I; 393 J2 ^= I; 394 395 out |= I << 26; // S bit 396 out |= !J1 << 13; // J1 bit 397 out |= !J2 << 11; // J2 bit 398 out |= (Value & 0x1FF800) << 5; // imm6 field 399 out |= (Value & 0x0007FF); // imm11 field 400 401 uint64_t swapped = (out & 0xFFFF0000) >> 16; 402 swapped |= (out & 0x0000FFFF) << 16; 403 return swapped; 404 } 405 case ARM::fixup_t2_condbranch: { 406 Value = Value - 4; 407 Value >>= 1; // Low bit is not encoded. 408 409 uint64_t out = 0; 410 out |= (Value & 0x80000) << 7; // S bit 411 out |= (Value & 0x40000) >> 7; // J2 bit 412 out |= (Value & 0x20000) >> 4; // J1 bit 413 out |= (Value & 0x1F800) << 5; // imm6 field 414 out |= (Value & 0x007FF); // imm11 field 415 416 uint32_t swapped = (out & 0xFFFF0000) >> 16; 417 swapped |= (out & 0x0000FFFF) << 16; 418 return swapped; 419 } 420 case ARM::fixup_arm_thumb_bl: { 421 // The value doesn't encode the low bit (always zero) and is offset by 422 // four. The 32-bit immediate value is encoded as 423 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0) 424 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S). 425 // The value is encoded into disjoint bit positions in the destination 426 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit, 427 // J = either J1 or J2 bit 428 // 429 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII 430 // 431 // Note that the halfwords are stored high first, low second; so we need 432 // to transpose the fixup value here to map properly. 433 uint32_t offset = (Value - 4) >> 1; 434 uint32_t signBit = (offset & 0x800000) >> 23; 435 uint32_t I1Bit = (offset & 0x400000) >> 22; 436 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit; 437 uint32_t I2Bit = (offset & 0x200000) >> 21; 438 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit; 439 uint32_t imm10Bits = (offset & 0x1FF800) >> 11; 440 uint32_t imm11Bits = (offset & 0x000007FF); 441 442 uint32_t Binary = 0; 443 uint32_t firstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits); 444 uint32_t secondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) | 445 (uint16_t)imm11Bits); 446 Binary |= secondHalf << 16; 447 Binary |= firstHalf; 448 return Binary; 449 } 450 case ARM::fixup_arm_thumb_blx: { 451 // The value doesn't encode the low two bits (always zero) and is offset by 452 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as 453 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00) 454 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S). 455 // The value is encoded into disjoint bit positions in the destination 456 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit, 457 // J = either J1 or J2 bit, 0 = zero. 458 // 459 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0 460 // 461 // Note that the halfwords are stored high first, low second; so we need 462 // to transpose the fixup value here to map properly. 463 uint32_t offset = (Value - 2) >> 2; 464 uint32_t signBit = (offset & 0x400000) >> 22; 465 uint32_t I1Bit = (offset & 0x200000) >> 21; 466 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit; 467 uint32_t I2Bit = (offset & 0x100000) >> 20; 468 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit; 469 uint32_t imm10HBits = (offset & 0xFFC00) >> 10; 470 uint32_t imm10LBits = (offset & 0x3FF); 471 472 uint32_t Binary = 0; 473 uint32_t firstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits); 474 uint32_t secondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) | 475 ((uint16_t)imm10LBits) << 1); 476 Binary |= secondHalf << 16; 477 Binary |= firstHalf; 478 return Binary; 479 } 480 case ARM::fixup_arm_thumb_cp: 481 // Offset by 4, and don't encode the low two bits. Two bytes of that 482 // 'off by 4' is implicitly handled by the half-word ordering of the 483 // Thumb encoding, so we only need to adjust by 2 here. 484 return ((Value - 2) >> 2) & 0xff; 485 case ARM::fixup_arm_thumb_cb: { 486 // Offset by 4 and don't encode the lower bit, which is always 0. 487 uint32_t Binary = (Value - 4) >> 1; 488 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3); 489 } 490 case ARM::fixup_arm_thumb_br: 491 // Offset by 4 and don't encode the lower bit, which is always 0. 492 return ((Value - 4) >> 1) & 0x7ff; 493 case ARM::fixup_arm_thumb_bcc: 494 // Offset by 4 and don't encode the lower bit, which is always 0. 495 return ((Value - 4) >> 1) & 0xff; 496 case ARM::fixup_arm_pcrel_10_unscaled: { 497 Value = Value - 8; // ARM fixups offset by an additional word and don't 498 // need to adjust for the half-word ordering. 499 bool isAdd = true; 500 if ((int64_t)Value < 0) { 501 Value = -Value; 502 isAdd = false; 503 } 504 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8]. 505 if (Ctx && Value >= 256) 506 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value"); 507 Value = (Value & 0xf) | ((Value & 0xf0) << 4); 508 return Value | (isAdd << 23); 509 } 510 case ARM::fixup_arm_pcrel_10: 511 Value = Value - 4; // ARM fixups offset by an additional word and don't 512 // need to adjust for the half-word ordering. 513 // Fall through. 514 case ARM::fixup_t2_pcrel_10: { 515 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 516 Value = Value - 4; 517 bool isAdd = true; 518 if ((int64_t)Value < 0) { 519 Value = -Value; 520 isAdd = false; 521 } 522 // These values don't encode the low two bits since they're always zero. 523 Value >>= 2; 524 if (Ctx && Value >= 256) 525 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value"); 526 Value |= isAdd << 23; 527 528 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords 529 // swapped. 530 if (Kind == ARM::fixup_t2_pcrel_10) { 531 uint32_t swapped = (Value & 0xFFFF0000) >> 16; 532 swapped |= (Value & 0x0000FFFF) << 16; 533 return swapped; 534 } 535 536 return Value; 537 } 538 } 539 } 540 541 void ARMAsmBackend::processFixupValue(const MCAssembler &Asm, 542 const MCAsmLayout &Layout, 543 const MCFixup &Fixup, 544 const MCFragment *DF, 545 MCValue &Target, uint64_t &Value, 546 bool &IsResolved) { 547 const MCSymbolRefExpr *A = Target.getSymA(); 548 // Some fixups to thumb function symbols need the low bit (thumb bit) 549 // twiddled. 550 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 && 551 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 && 552 (unsigned)Fixup.getKind() != ARM::fixup_arm_adr_pcrel_12 && 553 (unsigned)Fixup.getKind() != ARM::fixup_thumb_adr_pcrel_10 && 554 (unsigned)Fixup.getKind() != ARM::fixup_t2_adr_pcrel_12 && 555 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) { 556 if (A) { 557 const MCSymbol &Sym = A->getSymbol().AliasedSymbol(); 558 if (Asm.isThumbFunc(&Sym)) 559 Value |= 1; 560 } 561 } 562 // We must always generate a relocation for BL/BLX instructions if we have 563 // a symbol to reference, as the linker relies on knowing the destination 564 // symbol's thumb-ness to get interworking right. 565 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx || 566 (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl || 567 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx || 568 (unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl || 569 (unsigned)Fixup.getKind() == ARM::fixup_arm_condbl)) 570 IsResolved = false; 571 572 // Try to get the encoded value for the fixup as-if we're mapping it into 573 // the instruction. This allows adjustFixupValue() to issue a diagnostic 574 // if the value aren't invalid. 575 (void)adjustFixupValue(Fixup, Value, &Asm.getContext()); 576 } 577 578 /// getFixupKindNumBytes - The number of bytes the fixup may change. 579 static unsigned getFixupKindNumBytes(unsigned Kind) { 580 switch (Kind) { 581 default: 582 llvm_unreachable("Unknown fixup kind!"); 583 584 case FK_Data_1: 585 case ARM::fixup_arm_thumb_bcc: 586 case ARM::fixup_arm_thumb_cp: 587 case ARM::fixup_thumb_adr_pcrel_10: 588 return 1; 589 590 case FK_Data_2: 591 case ARM::fixup_arm_thumb_br: 592 case ARM::fixup_arm_thumb_cb: 593 return 2; 594 595 case ARM::fixup_arm_pcrel_10_unscaled: 596 case ARM::fixup_arm_ldst_pcrel_12: 597 case ARM::fixup_arm_pcrel_10: 598 case ARM::fixup_arm_adr_pcrel_12: 599 case ARM::fixup_arm_uncondbl: 600 case ARM::fixup_arm_condbl: 601 case ARM::fixup_arm_blx: 602 case ARM::fixup_arm_condbranch: 603 case ARM::fixup_arm_uncondbranch: 604 return 3; 605 606 case FK_Data_4: 607 case ARM::fixup_t2_ldst_pcrel_12: 608 case ARM::fixup_t2_condbranch: 609 case ARM::fixup_t2_uncondbranch: 610 case ARM::fixup_t2_pcrel_10: 611 case ARM::fixup_t2_adr_pcrel_12: 612 case ARM::fixup_arm_thumb_bl: 613 case ARM::fixup_arm_thumb_blx: 614 case ARM::fixup_arm_movt_hi16: 615 case ARM::fixup_arm_movw_lo16: 616 case ARM::fixup_arm_movt_hi16_pcrel: 617 case ARM::fixup_arm_movw_lo16_pcrel: 618 case ARM::fixup_t2_movt_hi16: 619 case ARM::fixup_t2_movw_lo16: 620 case ARM::fixup_t2_movt_hi16_pcrel: 621 case ARM::fixup_t2_movw_lo16_pcrel: 622 return 4; 623 } 624 } 625 626 void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 627 unsigned DataSize, uint64_t Value) const { 628 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 629 Value = adjustFixupValue(Fixup, Value); 630 if (!Value) return; // Doesn't change encoding. 631 632 unsigned Offset = Fixup.getOffset(); 633 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!"); 634 635 // For each byte of the fragment that the fixup touches, mask in the bits from 636 // the fixup value. The Value has been "split up" into the appropriate 637 // bitfields above. 638 for (unsigned i = 0; i != NumBytes; ++i) 639 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 640 } 641 642 namespace { 643 644 // FIXME: This should be in a separate file. 645 // ELF is an ELF of course... 646 class ELFARMAsmBackend : public ARMAsmBackend { 647 public: 648 uint8_t OSABI; 649 ELFARMAsmBackend(const Target &T, const StringRef TT, 650 uint8_t _OSABI) 651 : ARMAsmBackend(T, TT), OSABI(_OSABI) { } 652 653 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 654 return createARMELFObjectWriter(OS, OSABI); 655 } 656 }; 657 658 // FIXME: This should be in a separate file. 659 class DarwinARMAsmBackend : public ARMAsmBackend { 660 public: 661 const MachO::CPUSubTypeARM Subtype; 662 DarwinARMAsmBackend(const Target &T, const StringRef TT, 663 MachO::CPUSubTypeARM st) 664 : ARMAsmBackend(T, TT), Subtype(st) { 665 HasDataInCodeSupport = true; 666 } 667 668 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 669 return createARMMachObjectWriter(OS, /*Is64Bit=*/false, 670 MachO::CPU_TYPE_ARM, 671 Subtype); 672 } 673 674 virtual bool doesSectionRequireSymbols(const MCSection &Section) const { 675 return false; 676 } 677 }; 678 679 } // end anonymous namespace 680 681 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, 682 const MCRegisterInfo &MRI, 683 StringRef TT, StringRef CPU) { 684 Triple TheTriple(TT); 685 686 if (TheTriple.isOSBinFormatMachO()) { 687 MachO::CPUSubTypeARM CS = 688 StringSwitch<MachO::CPUSubTypeARM>(TheTriple.getArchName()) 689 .Cases("armv4t", "thumbv4t", MachO::CPU_SUBTYPE_ARM_V4T) 690 .Cases("armv5e", "thumbv5e", MachO::CPU_SUBTYPE_ARM_V5TEJ) 691 .Cases("armv6", "thumbv6", MachO::CPU_SUBTYPE_ARM_V6) 692 .Cases("armv6m", "thumbv6m", MachO::CPU_SUBTYPE_ARM_V6M) 693 .Cases("armv7em", "thumbv7em", MachO::CPU_SUBTYPE_ARM_V7EM) 694 .Cases("armv7k", "thumbv7k", MachO::CPU_SUBTYPE_ARM_V7K) 695 .Cases("armv7m", "thumbv7m", MachO::CPU_SUBTYPE_ARM_V7M) 696 .Cases("armv7s", "thumbv7s", MachO::CPU_SUBTYPE_ARM_V7S) 697 .Default(MachO::CPU_SUBTYPE_ARM_V7); 698 699 return new DarwinARMAsmBackend(T, TT, CS); 700 } 701 702 #if 0 703 // FIXME: Introduce yet another checker but assert(0). 704 if (TheTriple.isOSBinFormatCOFF()) 705 assert(0 && "Windows not supported on ARM"); 706 #endif 707 708 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS()); 709 return new ELFARMAsmBackend(T, TT, OSABI); 710 } 711