1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/ARMMCTargetDesc.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMFixupKinds.h" 13 #include "MCTargetDesc/ARMAddressingModes.h" 14 #include "llvm/MC/MCAssembler.h" 15 #include "llvm/MC/MCDirectives.h" 16 #include "llvm/MC/MCELFObjectWriter.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCFixupKindInfo.h" 19 #include "llvm/MC/MCMachObjectWriter.h" 20 #include "llvm/MC/MCObjectWriter.h" 21 #include "llvm/MC/MCSectionELF.h" 22 #include "llvm/MC/MCSectionMachO.h" 23 #include "llvm/MC/MCAsmBackend.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/MC/MCValue.h" 26 #include "llvm/Object/MachOFormat.h" 27 #include "llvm/Support/ELF.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/raw_ostream.h" 30 using namespace llvm; 31 32 namespace { 33 class ARMELFObjectWriter : public MCELFObjectTargetWriter { 34 public: 35 ARMELFObjectWriter(uint8_t OSABI) 36 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM, 37 /*HasRelocationAddend*/ false) {} 38 }; 39 40 class ARMAsmBackend : public MCAsmBackend { 41 const MCSubtargetInfo* STI; 42 bool isThumbMode; // Currently emitting Thumb code. 43 public: 44 ARMAsmBackend(const Target &T, const StringRef TT) 45 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")), 46 isThumbMode(TT.startswith("thumb")) {} 47 48 ~ARMAsmBackend() { 49 delete STI; 50 } 51 52 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; } 53 54 bool hasNOP() const { 55 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0; 56 } 57 58 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { 59 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = { 60 // This table *must* be in the order that the fixup_* kinds are defined in 61 // ARMFixupKinds.h. 62 // 63 // Name Offset (bits) Size (bits) Flags 64 { "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 65 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 66 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 67 { "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 68 { "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 69 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 70 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 71 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel | 72 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 73 { "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 74 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 75 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 76 { "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 77 { "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 78 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 79 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 80 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 81 { "fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 82 { "fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 83 { "fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 84 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 85 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 86 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 87 { "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel }, 88 { "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel }, 89 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19. 90 { "fixup_arm_movt_hi16", 0, 20, 0 }, 91 { "fixup_arm_movw_lo16", 0, 20, 0 }, 92 { "fixup_t2_movt_hi16", 0, 20, 0 }, 93 { "fixup_t2_movw_lo16", 0, 20, 0 }, 94 { "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 95 { "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 96 { "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 97 { "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 98 }; 99 100 if (Kind < FirstTargetFixupKind) 101 return MCAsmBackend::getFixupKindInfo(Kind); 102 103 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 104 "Invalid kind!"); 105 return Infos[Kind - FirstTargetFixupKind]; 106 } 107 108 /// processFixupValue - Target hook to process the literal value of a fixup 109 /// if necessary. 110 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout, 111 const MCFixup &Fixup, const MCFragment *DF, 112 MCValue &Target, uint64_t &Value, 113 bool &IsResolved) { 114 const MCSymbolRefExpr *A = Target.getSymA(); 115 // Some fixups to thumb function symbols need the low bit (thumb bit) 116 // twiddled. 117 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 && 118 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 && 119 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) { 120 if (A) { 121 const MCSymbol &Sym = A->getSymbol().AliasedSymbol(); 122 if (Asm.isThumbFunc(&Sym)) 123 Value |= 1; 124 } 125 } 126 // We must always generate a relocation for BL/BLX instructions if we have 127 // a symbol to reference, as the linker relies on knowing the destination 128 // symbol's thumb-ness to get interworking right. 129 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx || 130 (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl || 131 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx || 132 (unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl || 133 (unsigned)Fixup.getKind() == ARM::fixup_arm_condbl)) 134 IsResolved = false; 135 } 136 137 bool mayNeedRelaxation(const MCInst &Inst) const; 138 139 bool fixupNeedsRelaxation(const MCFixup &Fixup, 140 uint64_t Value, 141 const MCInstFragment *DF, 142 const MCAsmLayout &Layout) const; 143 144 void relaxInstruction(const MCInst &Inst, MCInst &Res) const; 145 146 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const; 147 148 void handleAssemblerFlag(MCAssemblerFlag Flag) { 149 switch (Flag) { 150 default: break; 151 case MCAF_Code16: 152 setIsThumb(true); 153 break; 154 case MCAF_Code32: 155 setIsThumb(false); 156 break; 157 } 158 } 159 160 unsigned getPointerSize() const { return 4; } 161 bool isThumb() const { return isThumbMode; } 162 void setIsThumb(bool it) { isThumbMode = it; } 163 }; 164 } // end anonymous namespace 165 166 static unsigned getRelaxedOpcode(unsigned Op) { 167 switch (Op) { 168 default: return Op; 169 case ARM::tBcc: return ARM::t2Bcc; 170 case ARM::tLDRpciASM: return ARM::t2LDRpci; 171 case ARM::tADR: return ARM::t2ADR; 172 case ARM::tB: return ARM::t2B; 173 } 174 } 175 176 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 177 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode()) 178 return true; 179 return false; 180 } 181 182 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, 183 uint64_t Value, 184 const MCInstFragment *DF, 185 const MCAsmLayout &Layout) const { 186 switch ((unsigned)Fixup.getKind()) { 187 case ARM::fixup_arm_thumb_br: { 188 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the 189 // low bit being an implied zero. There's an implied +4 offset for the 190 // branch, so we adjust the other way here to determine what's 191 // encodable. 192 // 193 // Relax if the value is too big for a (signed) i8. 194 int64_t Offset = int64_t(Value) - 4; 195 return Offset > 2046 || Offset < -2048; 196 } 197 case ARM::fixup_arm_thumb_bcc: { 198 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the 199 // low bit being an implied zero. There's an implied +4 offset for the 200 // branch, so we adjust the other way here to determine what's 201 // encodable. 202 // 203 // Relax if the value is too big for a (signed) i8. 204 int64_t Offset = int64_t(Value) - 4; 205 return Offset > 254 || Offset < -256; 206 } 207 case ARM::fixup_thumb_adr_pcrel_10: 208 case ARM::fixup_arm_thumb_cp: { 209 // If the immediate is negative, greater than 1020, or not a multiple 210 // of four, the wide version of the instruction must be used. 211 int64_t Offset = int64_t(Value) - 4; 212 return Offset > 1020 || Offset < 0 || Offset & 3; 213 } 214 } 215 llvm_unreachable("Unexpected fixup kind in fixupNeedsRelaxation()!"); 216 } 217 218 void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const { 219 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode()); 220 221 // Sanity check w/ diagnostic if we get here w/ a bogus instruction. 222 if (RelaxedOp == Inst.getOpcode()) { 223 SmallString<256> Tmp; 224 raw_svector_ostream OS(Tmp); 225 Inst.dump_pretty(OS); 226 OS << "\n"; 227 report_fatal_error("unexpected instruction to relax: " + OS.str()); 228 } 229 230 // The instructions we're relaxing have (so far) the same operands. 231 // We just need to update to the proper opcode. 232 Res = Inst; 233 Res.setOpcode(RelaxedOp); 234 } 235 236 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 237 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8 238 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP 239 const uint32_t ARMv4_NopEncoding = 0xe1a0000; // using MOV r0,r0 240 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP 241 if (isThumb()) { 242 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding 243 : Thumb1_16bitNopEncoding; 244 uint64_t NumNops = Count / 2; 245 for (uint64_t i = 0; i != NumNops; ++i) 246 OW->Write16(nopEncoding); 247 if (Count & 1) 248 OW->Write8(0); 249 return true; 250 } 251 // ARM mode 252 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding 253 : ARMv4_NopEncoding; 254 uint64_t NumNops = Count / 4; 255 for (uint64_t i = 0; i != NumNops; ++i) 256 OW->Write32(nopEncoding); 257 // FIXME: should this function return false when unable to write exactly 258 // 'Count' bytes with NOP encodings? 259 switch (Count % 4) { 260 default: break; // No leftover bytes to write 261 case 1: OW->Write8(0); break; 262 case 2: OW->Write16(0); break; 263 case 3: OW->Write16(0); OW->Write8(0xa0); break; 264 } 265 266 return true; 267 } 268 269 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { 270 switch (Kind) { 271 default: 272 llvm_unreachable("Unknown fixup kind!"); 273 case FK_Data_1: 274 case FK_Data_2: 275 case FK_Data_4: 276 return Value; 277 case ARM::fixup_arm_movt_hi16: 278 Value >>= 16; 279 // Fallthrough 280 case ARM::fixup_arm_movw_lo16: 281 case ARM::fixup_arm_movt_hi16_pcrel: 282 case ARM::fixup_arm_movw_lo16_pcrel: { 283 unsigned Hi4 = (Value & 0xF000) >> 12; 284 unsigned Lo12 = Value & 0x0FFF; 285 // inst{19-16} = Hi4; 286 // inst{11-0} = Lo12; 287 Value = (Hi4 << 16) | (Lo12); 288 return Value; 289 } 290 case ARM::fixup_t2_movt_hi16: 291 Value >>= 16; 292 // Fallthrough 293 case ARM::fixup_t2_movw_lo16: 294 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like 295 // the other hi16 fixup? 296 case ARM::fixup_t2_movw_lo16_pcrel: { 297 unsigned Hi4 = (Value & 0xF000) >> 12; 298 unsigned i = (Value & 0x800) >> 11; 299 unsigned Mid3 = (Value & 0x700) >> 8; 300 unsigned Lo8 = Value & 0x0FF; 301 // inst{19-16} = Hi4; 302 // inst{26} = i; 303 // inst{14-12} = Mid3; 304 // inst{7-0} = Lo8; 305 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8); 306 uint64_t swapped = (Value & 0xFFFF0000) >> 16; 307 swapped |= (Value & 0x0000FFFF) << 16; 308 return swapped; 309 } 310 case ARM::fixup_arm_ldst_pcrel_12: 311 // ARM PC-relative values are offset by 8. 312 Value -= 4; 313 // FALLTHROUGH 314 case ARM::fixup_t2_ldst_pcrel_12: { 315 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 316 Value -= 4; 317 bool isAdd = true; 318 if ((int64_t)Value < 0) { 319 Value = -Value; 320 isAdd = false; 321 } 322 assert ((Value < 4096) && "Out of range pc-relative fixup value!"); 323 Value |= isAdd << 23; 324 325 // Same addressing mode as fixup_arm_pcrel_10, 326 // but with 16-bit halfwords swapped. 327 if (Kind == ARM::fixup_t2_ldst_pcrel_12) { 328 uint64_t swapped = (Value & 0xFFFF0000) >> 16; 329 swapped |= (Value & 0x0000FFFF) << 16; 330 return swapped; 331 } 332 333 return Value; 334 } 335 case ARM::fixup_thumb_adr_pcrel_10: 336 return ((Value - 4) >> 2) & 0xff; 337 case ARM::fixup_arm_adr_pcrel_12: { 338 // ARM PC-relative values are offset by 8. 339 Value -= 8; 340 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 341 if ((int64_t)Value < 0) { 342 Value = -Value; 343 opc = 2; // 0b0010 344 } 345 assert(ARM_AM::getSOImmVal(Value) != -1 && 346 "Out of range pc-relative fixup value!"); 347 // Encode the immediate and shift the opcode into place. 348 return ARM_AM::getSOImmVal(Value) | (opc << 21); 349 } 350 351 case ARM::fixup_t2_adr_pcrel_12: { 352 Value -= 4; 353 unsigned opc = 0; 354 if ((int64_t)Value < 0) { 355 Value = -Value; 356 opc = 5; 357 } 358 359 uint32_t out = (opc << 21); 360 out |= (Value & 0x800) << 15; 361 out |= (Value & 0x700) << 4; 362 out |= (Value & 0x0FF); 363 364 uint64_t swapped = (out & 0xFFFF0000) >> 16; 365 swapped |= (out & 0x0000FFFF) << 16; 366 return swapped; 367 } 368 369 case ARM::fixup_arm_condbranch: 370 case ARM::fixup_arm_uncondbranch: 371 case ARM::fixup_arm_uncondbl: 372 case ARM::fixup_arm_condbl: 373 case ARM::fixup_arm_blx: 374 // These values don't encode the low two bits since they're always zero. 375 // Offset by 8 just as above. 376 return 0xffffff & ((Value - 8) >> 2); 377 case ARM::fixup_t2_uncondbranch: { 378 Value = Value - 4; 379 Value >>= 1; // Low bit is not encoded. 380 381 uint32_t out = 0; 382 bool I = Value & 0x800000; 383 bool J1 = Value & 0x400000; 384 bool J2 = Value & 0x200000; 385 J1 ^= I; 386 J2 ^= I; 387 388 out |= I << 26; // S bit 389 out |= !J1 << 13; // J1 bit 390 out |= !J2 << 11; // J2 bit 391 out |= (Value & 0x1FF800) << 5; // imm6 field 392 out |= (Value & 0x0007FF); // imm11 field 393 394 uint64_t swapped = (out & 0xFFFF0000) >> 16; 395 swapped |= (out & 0x0000FFFF) << 16; 396 return swapped; 397 } 398 case ARM::fixup_t2_condbranch: { 399 Value = Value - 4; 400 Value >>= 1; // Low bit is not encoded. 401 402 uint64_t out = 0; 403 out |= (Value & 0x80000) << 7; // S bit 404 out |= (Value & 0x40000) >> 7; // J2 bit 405 out |= (Value & 0x20000) >> 4; // J1 bit 406 out |= (Value & 0x1F800) << 5; // imm6 field 407 out |= (Value & 0x007FF); // imm11 field 408 409 uint32_t swapped = (out & 0xFFFF0000) >> 16; 410 swapped |= (out & 0x0000FFFF) << 16; 411 return swapped; 412 } 413 case ARM::fixup_arm_thumb_bl: { 414 // The value doesn't encode the low bit (always zero) and is offset by 415 // four. The value is encoded into disjoint bit positions in the destination 416 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit 417 // 418 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII 419 // 420 // Note that the halfwords are stored high first, low second; so we need 421 // to transpose the fixup value here to map properly. 422 unsigned isNeg = (int64_t(Value - 4) < 0) ? 1 : 0; 423 uint32_t Binary = 0; 424 Value = 0x3fffff & ((Value - 4) >> 1); 425 Binary = (Value & 0x7ff) << 16; // Low imm11 value. 426 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value. 427 Binary |= isNeg << 10; // Sign bit. 428 return Binary; 429 } 430 case ARM::fixup_arm_thumb_blx: { 431 // The value doesn't encode the low two bits (always zero) and is offset by 432 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit 433 // positions in the destination opcode. x = unchanged, I = immediate value 434 // bit, S = sign extension bit, 0 = zero. 435 // 436 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0 437 // 438 // Note that the halfwords are stored high first, low second; so we need 439 // to transpose the fixup value here to map properly. 440 unsigned isNeg = (int64_t(Value-4) < 0) ? 1 : 0; 441 uint32_t Binary = 0; 442 Value = 0xfffff & ((Value - 2) >> 2); 443 Binary = (Value & 0x3ff) << 17; // Low imm10L value. 444 Binary |= (Value & 0xffc00) >> 10; // High imm10H value. 445 Binary |= isNeg << 10; // Sign bit. 446 return Binary; 447 } 448 case ARM::fixup_arm_thumb_cp: 449 // Offset by 4, and don't encode the low two bits. Two bytes of that 450 // 'off by 4' is implicitly handled by the half-word ordering of the 451 // Thumb encoding, so we only need to adjust by 2 here. 452 return ((Value - 2) >> 2) & 0xff; 453 case ARM::fixup_arm_thumb_cb: { 454 // Offset by 4 and don't encode the lower bit, which is always 0. 455 uint32_t Binary = (Value - 4) >> 1; 456 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3); 457 } 458 case ARM::fixup_arm_thumb_br: 459 // Offset by 4 and don't encode the lower bit, which is always 0. 460 return ((Value - 4) >> 1) & 0x7ff; 461 case ARM::fixup_arm_thumb_bcc: 462 // Offset by 4 and don't encode the lower bit, which is always 0. 463 return ((Value - 4) >> 1) & 0xff; 464 case ARM::fixup_arm_pcrel_10_unscaled: { 465 Value = Value - 8; // ARM fixups offset by an additional word and don't 466 // need to adjust for the half-word ordering. 467 bool isAdd = true; 468 if ((int64_t)Value < 0) { 469 Value = -Value; 470 isAdd = false; 471 } 472 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8]. 473 assert ((Value < 256) && "Out of range pc-relative fixup value!"); 474 Value = (Value & 0xf) | ((Value & 0xf0) << 4); 475 return Value | (isAdd << 23); 476 } 477 case ARM::fixup_arm_pcrel_10: 478 Value = Value - 4; // ARM fixups offset by an additional word and don't 479 // need to adjust for the half-word ordering. 480 // Fall through. 481 case ARM::fixup_t2_pcrel_10: { 482 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 483 Value = Value - 4; 484 bool isAdd = true; 485 if ((int64_t)Value < 0) { 486 Value = -Value; 487 isAdd = false; 488 } 489 // These values don't encode the low two bits since they're always zero. 490 Value >>= 2; 491 assert ((Value < 256) && "Out of range pc-relative fixup value!"); 492 Value |= isAdd << 23; 493 494 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords 495 // swapped. 496 if (Kind == ARM::fixup_t2_pcrel_10) { 497 uint32_t swapped = (Value & 0xFFFF0000) >> 16; 498 swapped |= (Value & 0x0000FFFF) << 16; 499 return swapped; 500 } 501 502 return Value; 503 } 504 } 505 } 506 507 namespace { 508 509 // FIXME: This should be in a separate file. 510 // ELF is an ELF of course... 511 class ELFARMAsmBackend : public ARMAsmBackend { 512 public: 513 uint8_t OSABI; 514 ELFARMAsmBackend(const Target &T, const StringRef TT, 515 uint8_t _OSABI) 516 : ARMAsmBackend(T, TT), OSABI(_OSABI) { } 517 518 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 519 uint64_t Value) const; 520 521 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 522 return createARMELFObjectWriter(OS, OSABI); 523 } 524 }; 525 526 // FIXME: Raise this to share code between Darwin and ELF. 527 void ELFARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 528 unsigned DataSize, uint64_t Value) const { 529 unsigned NumBytes = 4; // FIXME: 2 for Thumb 530 Value = adjustFixupValue(Fixup.getKind(), Value); 531 if (!Value) return; // Doesn't change encoding. 532 533 unsigned Offset = Fixup.getOffset(); 534 535 // For each byte of the fragment that the fixup touches, mask in the bits from 536 // the fixup value. The Value has been "split up" into the appropriate 537 // bitfields above. 538 for (unsigned i = 0; i != NumBytes; ++i) 539 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 540 } 541 542 // FIXME: This should be in a separate file. 543 class DarwinARMAsmBackend : public ARMAsmBackend { 544 public: 545 const object::mach::CPUSubtypeARM Subtype; 546 DarwinARMAsmBackend(const Target &T, const StringRef TT, 547 object::mach::CPUSubtypeARM st) 548 : ARMAsmBackend(T, TT), Subtype(st) { } 549 550 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 551 return createARMMachObjectWriter(OS, /*Is64Bit=*/false, 552 object::mach::CTM_ARM, 553 Subtype); 554 } 555 556 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 557 uint64_t Value) const; 558 559 virtual bool doesSectionRequireSymbols(const MCSection &Section) const { 560 return false; 561 } 562 }; 563 564 /// getFixupKindNumBytes - The number of bytes the fixup may change. 565 static unsigned getFixupKindNumBytes(unsigned Kind) { 566 switch (Kind) { 567 default: 568 llvm_unreachable("Unknown fixup kind!"); 569 570 case FK_Data_1: 571 case ARM::fixup_arm_thumb_bcc: 572 case ARM::fixup_arm_thumb_cp: 573 case ARM::fixup_thumb_adr_pcrel_10: 574 return 1; 575 576 case FK_Data_2: 577 case ARM::fixup_arm_thumb_br: 578 case ARM::fixup_arm_thumb_cb: 579 return 2; 580 581 case ARM::fixup_arm_pcrel_10_unscaled: 582 case ARM::fixup_arm_ldst_pcrel_12: 583 case ARM::fixup_arm_pcrel_10: 584 case ARM::fixup_arm_adr_pcrel_12: 585 case ARM::fixup_arm_uncondbl: 586 case ARM::fixup_arm_condbl: 587 case ARM::fixup_arm_blx: 588 case ARM::fixup_arm_condbranch: 589 case ARM::fixup_arm_uncondbranch: 590 return 3; 591 592 case FK_Data_4: 593 case ARM::fixup_t2_ldst_pcrel_12: 594 case ARM::fixup_t2_condbranch: 595 case ARM::fixup_t2_uncondbranch: 596 case ARM::fixup_t2_pcrel_10: 597 case ARM::fixup_t2_adr_pcrel_12: 598 case ARM::fixup_arm_thumb_bl: 599 case ARM::fixup_arm_thumb_blx: 600 case ARM::fixup_arm_movt_hi16: 601 case ARM::fixup_arm_movw_lo16: 602 case ARM::fixup_arm_movt_hi16_pcrel: 603 case ARM::fixup_arm_movw_lo16_pcrel: 604 case ARM::fixup_t2_movt_hi16: 605 case ARM::fixup_t2_movw_lo16: 606 case ARM::fixup_t2_movt_hi16_pcrel: 607 case ARM::fixup_t2_movw_lo16_pcrel: 608 return 4; 609 } 610 } 611 612 void DarwinARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 613 unsigned DataSize, uint64_t Value) const { 614 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 615 Value = adjustFixupValue(Fixup.getKind(), Value); 616 if (!Value) return; // Doesn't change encoding. 617 618 unsigned Offset = Fixup.getOffset(); 619 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!"); 620 621 // For each byte of the fragment that the fixup touches, mask in the 622 // bits from the fixup value. 623 for (unsigned i = 0; i != NumBytes; ++i) 624 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 625 } 626 627 } // end anonymous namespace 628 629 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, StringRef TT) { 630 Triple TheTriple(TT); 631 632 if (TheTriple.isOSDarwin()) { 633 if (TheTriple.getArchName() == "armv4t" || 634 TheTriple.getArchName() == "thumbv4t") 635 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V4T); 636 else if (TheTriple.getArchName() == "armv5e" || 637 TheTriple.getArchName() == "thumbv5e") 638 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V5TEJ); 639 else if (TheTriple.getArchName() == "armv6" || 640 TheTriple.getArchName() == "thumbv6") 641 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V6); 642 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7); 643 } 644 645 if (TheTriple.isOSWindows()) 646 assert(0 && "Windows not supported on ARM"); 647 648 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS()); 649 return new ELFARMAsmBackend(T, TT, OSABI); 650 } 651