1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/ARMMCTargetDesc.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "MCTargetDesc/ARMAsmBackend.h" 13 #include "MCTargetDesc/ARMAsmBackendDarwin.h" 14 #include "MCTargetDesc/ARMAsmBackendELF.h" 15 #include "MCTargetDesc/ARMAsmBackendWinCOFF.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "MCTargetDesc/ARMFixupKinds.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/MC/MCAsmBackend.h" 20 #include "llvm/MC/MCAssembler.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCDirectives.h" 23 #include "llvm/MC/MCELFObjectWriter.h" 24 #include "llvm/MC/MCExpr.h" 25 #include "llvm/MC/MCFixupKindInfo.h" 26 #include "llvm/MC/MCMachObjectWriter.h" 27 #include "llvm/MC/MCObjectWriter.h" 28 #include "llvm/MC/MCRegisterInfo.h" 29 #include "llvm/MC/MCSectionELF.h" 30 #include "llvm/MC/MCSectionMachO.h" 31 #include "llvm/MC/MCSubtargetInfo.h" 32 #include "llvm/MC/MCValue.h" 33 #include "llvm/Support/Debug.h" 34 #include "llvm/Support/ELF.h" 35 #include "llvm/Support/ErrorHandling.h" 36 #include "llvm/Support/Format.h" 37 #include "llvm/Support/MachO.h" 38 #include "llvm/Support/TargetParser.h" 39 #include "llvm/Support/raw_ostream.h" 40 using namespace llvm; 41 42 namespace { 43 class ARMELFObjectWriter : public MCELFObjectTargetWriter { 44 public: 45 ARMELFObjectWriter(uint8_t OSABI) 46 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM, 47 /*HasRelocationAddend*/ false) {} 48 }; 49 50 const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { 51 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = { 52 // This table *must* be in the order that the fixup_* kinds are defined in 53 // ARMFixupKinds.h. 54 // 55 // Name Offset (bits) Size (bits) Flags 56 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 57 {"fixup_t2_ldst_pcrel_12", 0, 32, 58 MCFixupKindInfo::FKF_IsPCRel | 59 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 60 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 61 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 62 {"fixup_t2_pcrel_10", 0, 32, 63 MCFixupKindInfo::FKF_IsPCRel | 64 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 65 {"fixup_thumb_adr_pcrel_10", 0, 8, 66 MCFixupKindInfo::FKF_IsPCRel | 67 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 68 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 69 {"fixup_t2_adr_pcrel_12", 0, 32, 70 MCFixupKindInfo::FKF_IsPCRel | 71 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 72 {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 73 {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 74 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 75 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 76 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 77 {"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 78 {"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 79 {"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 80 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 81 {"fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 82 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 83 {"fixup_arm_thumb_cp", 0, 8, 84 MCFixupKindInfo::FKF_IsPCRel | 85 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 86 {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel}, 87 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 88 // - 19. 89 {"fixup_arm_movt_hi16", 0, 20, 0}, 90 {"fixup_arm_movw_lo16", 0, 20, 0}, 91 {"fixup_t2_movt_hi16", 0, 20, 0}, 92 {"fixup_t2_movw_lo16", 0, 20, 0}, 93 }; 94 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = { 95 // This table *must* be in the order that the fixup_* kinds are defined in 96 // ARMFixupKinds.h. 97 // 98 // Name Offset (bits) Size (bits) Flags 99 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 100 {"fixup_t2_ldst_pcrel_12", 0, 32, 101 MCFixupKindInfo::FKF_IsPCRel | 102 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 103 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 104 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 105 {"fixup_t2_pcrel_10", 0, 32, 106 MCFixupKindInfo::FKF_IsPCRel | 107 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 108 {"fixup_thumb_adr_pcrel_10", 8, 8, 109 MCFixupKindInfo::FKF_IsPCRel | 110 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 111 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 112 {"fixup_t2_adr_pcrel_12", 0, 32, 113 MCFixupKindInfo::FKF_IsPCRel | 114 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 115 {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 116 {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 117 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 118 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 119 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 120 {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 121 {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 122 {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 123 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 124 {"fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 125 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 126 {"fixup_arm_thumb_cp", 8, 8, 127 MCFixupKindInfo::FKF_IsPCRel | 128 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 129 {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel}, 130 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 131 // - 19. 132 {"fixup_arm_movt_hi16", 12, 20, 0}, 133 {"fixup_arm_movw_lo16", 12, 20, 0}, 134 {"fixup_t2_movt_hi16", 12, 20, 0}, 135 {"fixup_t2_movw_lo16", 12, 20, 0}, 136 }; 137 138 if (Kind < FirstTargetFixupKind) 139 return MCAsmBackend::getFixupKindInfo(Kind); 140 141 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 142 "Invalid kind!"); 143 return (IsLittleEndian ? InfosLE : InfosBE)[Kind - FirstTargetFixupKind]; 144 } 145 146 void ARMAsmBackend::handleAssemblerFlag(MCAssemblerFlag Flag) { 147 switch (Flag) { 148 default: 149 break; 150 case MCAF_Code16: 151 setIsThumb(true); 152 break; 153 case MCAF_Code32: 154 setIsThumb(false); 155 break; 156 } 157 } 158 } // end anonymous namespace 159 160 unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op) const { 161 bool HasThumb2 = STI->getFeatureBits()[ARM::FeatureThumb2]; 162 bool HasV8MBaselineOps = STI->getFeatureBits()[ARM::HasV8MBaselineOps]; 163 164 switch (Op) { 165 default: 166 return Op; 167 case ARM::tBcc: 168 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op; 169 case ARM::tLDRpci: 170 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op; 171 case ARM::tADR: 172 return HasThumb2 ? (unsigned)ARM::t2ADR : Op; 173 case ARM::tB: 174 return HasV8MBaselineOps ? (unsigned)ARM::t2B : Op; 175 case ARM::tCBZ: 176 return ARM::tHINT; 177 case ARM::tCBNZ: 178 return ARM::tHINT; 179 } 180 } 181 182 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 183 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode()) 184 return true; 185 return false; 186 } 187 188 const char *ARMAsmBackend::reasonForFixupRelaxation(const MCFixup &Fixup, 189 uint64_t Value) const { 190 switch ((unsigned)Fixup.getKind()) { 191 case ARM::fixup_arm_thumb_br: { 192 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the 193 // low bit being an implied zero. There's an implied +4 offset for the 194 // branch, so we adjust the other way here to determine what's 195 // encodable. 196 // 197 // Relax if the value is too big for a (signed) i8. 198 int64_t Offset = int64_t(Value) - 4; 199 if (Offset > 2046 || Offset < -2048) 200 return "out of range pc-relative fixup value"; 201 break; 202 } 203 case ARM::fixup_arm_thumb_bcc: { 204 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the 205 // low bit being an implied zero. There's an implied +4 offset for the 206 // branch, so we adjust the other way here to determine what's 207 // encodable. 208 // 209 // Relax if the value is too big for a (signed) i8. 210 int64_t Offset = int64_t(Value) - 4; 211 if (Offset > 254 || Offset < -256) 212 return "out of range pc-relative fixup value"; 213 break; 214 } 215 case ARM::fixup_thumb_adr_pcrel_10: 216 case ARM::fixup_arm_thumb_cp: { 217 // If the immediate is negative, greater than 1020, or not a multiple 218 // of four, the wide version of the instruction must be used. 219 int64_t Offset = int64_t(Value) - 4; 220 if (Offset & 3) 221 return "misaligned pc-relative fixup value"; 222 else if (Offset > 1020 || Offset < 0) 223 return "out of range pc-relative fixup value"; 224 break; 225 } 226 case ARM::fixup_arm_thumb_cb: { 227 // If we have a Thumb CBZ or CBNZ instruction and its target is the next 228 // instruction it is is actually out of range for the instruction. 229 // It will be changed to a NOP. 230 int64_t Offset = (Value & ~1); 231 if (Offset == 2) 232 return "will be converted to nop"; 233 break; 234 } 235 default: 236 llvm_unreachable("Unexpected fixup kind in reasonForFixupRelaxation()!"); 237 } 238 return nullptr; 239 } 240 241 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, 242 const MCRelaxableFragment *DF, 243 const MCAsmLayout &Layout) const { 244 return reasonForFixupRelaxation(Fixup, Value); 245 } 246 247 void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const { 248 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode()); 249 250 // Sanity check w/ diagnostic if we get here w/ a bogus instruction. 251 if (RelaxedOp == Inst.getOpcode()) { 252 SmallString<256> Tmp; 253 raw_svector_ostream OS(Tmp); 254 Inst.dump_pretty(OS); 255 OS << "\n"; 256 report_fatal_error("unexpected instruction to relax: " + OS.str()); 257 } 258 259 // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we 260 // have to change the operands too. 261 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) && 262 RelaxedOp == ARM::tHINT) { 263 Res.setOpcode(RelaxedOp); 264 Res.addOperand(MCOperand::createImm(0)); 265 Res.addOperand(MCOperand::createImm(14)); 266 Res.addOperand(MCOperand::createReg(0)); 267 return; 268 } 269 270 // The rest of instructions we're relaxing have the same operands. 271 // We just need to update to the proper opcode. 272 Res = Inst; 273 Res.setOpcode(RelaxedOp); 274 } 275 276 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 277 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8 278 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP 279 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0 280 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP 281 if (isThumb()) { 282 const uint16_t nopEncoding = 283 hasNOP() ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding; 284 uint64_t NumNops = Count / 2; 285 for (uint64_t i = 0; i != NumNops; ++i) 286 OW->write16(nopEncoding); 287 if (Count & 1) 288 OW->write8(0); 289 return true; 290 } 291 // ARM mode 292 const uint32_t nopEncoding = 293 hasNOP() ? ARMv6T2_NopEncoding : ARMv4_NopEncoding; 294 uint64_t NumNops = Count / 4; 295 for (uint64_t i = 0; i != NumNops; ++i) 296 OW->write32(nopEncoding); 297 // FIXME: should this function return false when unable to write exactly 298 // 'Count' bytes with NOP encodings? 299 switch (Count % 4) { 300 default: 301 break; // No leftover bytes to write 302 case 1: 303 OW->write8(0); 304 break; 305 case 2: 306 OW->write16(0); 307 break; 308 case 3: 309 OW->write16(0); 310 OW->write8(0xa0); 311 break; 312 } 313 314 return true; 315 } 316 317 static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) { 318 if (IsLittleEndian) { 319 // Note that the halfwords are stored high first and low second in thumb; 320 // so we need to swap the fixup value here to map properly. 321 uint32_t Swapped = (Value & 0xFFFF0000) >> 16; 322 Swapped |= (Value & 0x0000FFFF) << 16; 323 return Swapped; 324 } else 325 return Value; 326 } 327 328 static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf, 329 bool IsLittleEndian) { 330 uint32_t Value; 331 332 if (IsLittleEndian) { 333 Value = (SecondHalf & 0xFFFF) << 16; 334 Value |= (FirstHalf & 0xFFFF); 335 } else { 336 Value = (SecondHalf & 0xFFFF); 337 Value |= (FirstHalf & 0xFFFF) << 16; 338 } 339 340 return Value; 341 } 342 343 unsigned ARMAsmBackend::adjustFixupValue(const MCFixup &Fixup, uint64_t Value, 344 bool IsPCRel, MCContext *Ctx, 345 bool IsLittleEndian, 346 bool IsResolved) const { 347 unsigned Kind = Fixup.getKind(); 348 switch (Kind) { 349 default: 350 llvm_unreachable("Unknown fixup kind!"); 351 case FK_Data_1: 352 case FK_Data_2: 353 case FK_Data_4: 354 return Value; 355 case FK_SecRel_2: 356 return Value; 357 case FK_SecRel_4: 358 return Value; 359 case ARM::fixup_arm_movt_hi16: 360 if (!IsPCRel) 361 Value >>= 16; 362 // Fallthrough 363 case ARM::fixup_arm_movw_lo16: { 364 unsigned Hi4 = (Value & 0xF000) >> 12; 365 unsigned Lo12 = Value & 0x0FFF; 366 // inst{19-16} = Hi4; 367 // inst{11-0} = Lo12; 368 Value = (Hi4 << 16) | (Lo12); 369 return Value; 370 } 371 case ARM::fixup_t2_movt_hi16: 372 if (!IsPCRel) 373 Value >>= 16; 374 // Fallthrough 375 case ARM::fixup_t2_movw_lo16: { 376 unsigned Hi4 = (Value & 0xF000) >> 12; 377 unsigned i = (Value & 0x800) >> 11; 378 unsigned Mid3 = (Value & 0x700) >> 8; 379 unsigned Lo8 = Value & 0x0FF; 380 // inst{19-16} = Hi4; 381 // inst{26} = i; 382 // inst{14-12} = Mid3; 383 // inst{7-0} = Lo8; 384 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8); 385 return swapHalfWords(Value, IsLittleEndian); 386 } 387 case ARM::fixup_arm_ldst_pcrel_12: 388 // ARM PC-relative values are offset by 8. 389 Value -= 4; 390 // FALLTHROUGH 391 case ARM::fixup_t2_ldst_pcrel_12: { 392 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 393 Value -= 4; 394 bool isAdd = true; 395 if ((int64_t)Value < 0) { 396 Value = -Value; 397 isAdd = false; 398 } 399 if (Ctx && Value >= 4096) { 400 Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 401 return 0; 402 } 403 Value |= isAdd << 23; 404 405 // Same addressing mode as fixup_arm_pcrel_10, 406 // but with 16-bit halfwords swapped. 407 if (Kind == ARM::fixup_t2_ldst_pcrel_12) 408 return swapHalfWords(Value, IsLittleEndian); 409 410 return Value; 411 } 412 case ARM::fixup_arm_adr_pcrel_12: { 413 // ARM PC-relative values are offset by 8. 414 Value -= 8; 415 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 416 if ((int64_t)Value < 0) { 417 Value = -Value; 418 opc = 2; // 0b0010 419 } 420 if (Ctx && ARM_AM::getSOImmVal(Value) == -1) { 421 Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 422 return 0; 423 } 424 // Encode the immediate and shift the opcode into place. 425 return ARM_AM::getSOImmVal(Value) | (opc << 21); 426 } 427 428 case ARM::fixup_t2_adr_pcrel_12: { 429 Value -= 4; 430 unsigned opc = 0; 431 if ((int64_t)Value < 0) { 432 Value = -Value; 433 opc = 5; 434 } 435 436 uint32_t out = (opc << 21); 437 out |= (Value & 0x800) << 15; 438 out |= (Value & 0x700) << 4; 439 out |= (Value & 0x0FF); 440 441 return swapHalfWords(out, IsLittleEndian); 442 } 443 444 case ARM::fixup_arm_condbranch: 445 case ARM::fixup_arm_uncondbranch: 446 case ARM::fixup_arm_uncondbl: 447 case ARM::fixup_arm_condbl: 448 case ARM::fixup_arm_blx: 449 // These values don't encode the low two bits since they're always zero. 450 // Offset by 8 just as above. 451 if (const MCSymbolRefExpr *SRE = 452 dyn_cast<MCSymbolRefExpr>(Fixup.getValue())) 453 if (SRE->getKind() == MCSymbolRefExpr::VK_ARM_TLSCALL) 454 return 0; 455 return 0xffffff & ((Value - 8) >> 2); 456 case ARM::fixup_t2_uncondbranch: { 457 Value = Value - 4; 458 Value >>= 1; // Low bit is not encoded. 459 460 uint32_t out = 0; 461 bool I = Value & 0x800000; 462 bool J1 = Value & 0x400000; 463 bool J2 = Value & 0x200000; 464 J1 ^= I; 465 J2 ^= I; 466 467 out |= I << 26; // S bit 468 out |= !J1 << 13; // J1 bit 469 out |= !J2 << 11; // J2 bit 470 out |= (Value & 0x1FF800) << 5; // imm6 field 471 out |= (Value & 0x0007FF); // imm11 field 472 473 return swapHalfWords(out, IsLittleEndian); 474 } 475 case ARM::fixup_t2_condbranch: { 476 Value = Value - 4; 477 Value >>= 1; // Low bit is not encoded. 478 479 uint64_t out = 0; 480 out |= (Value & 0x80000) << 7; // S bit 481 out |= (Value & 0x40000) >> 7; // J2 bit 482 out |= (Value & 0x20000) >> 4; // J1 bit 483 out |= (Value & 0x1F800) << 5; // imm6 field 484 out |= (Value & 0x007FF); // imm11 field 485 486 return swapHalfWords(out, IsLittleEndian); 487 } 488 case ARM::fixup_arm_thumb_bl: { 489 // The value doesn't encode the low bit (always zero) and is offset by 490 // four. The 32-bit immediate value is encoded as 491 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0) 492 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S). 493 // The value is encoded into disjoint bit positions in the destination 494 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit, 495 // J = either J1 or J2 bit 496 // 497 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII 498 // 499 // Note that the halfwords are stored high first, low second; so we need 500 // to transpose the fixup value here to map properly. 501 uint32_t offset = (Value - 4) >> 1; 502 uint32_t signBit = (offset & 0x800000) >> 23; 503 uint32_t I1Bit = (offset & 0x400000) >> 22; 504 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit; 505 uint32_t I2Bit = (offset & 0x200000) >> 21; 506 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit; 507 uint32_t imm10Bits = (offset & 0x1FF800) >> 11; 508 uint32_t imm11Bits = (offset & 0x000007FF); 509 510 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits); 511 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) | 512 (uint16_t)imm11Bits); 513 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian); 514 } 515 case ARM::fixup_arm_thumb_blx: { 516 // The value doesn't encode the low two bits (always zero) and is offset by 517 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as 518 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00) 519 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S). 520 // The value is encoded into disjoint bit positions in the destination 521 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit, 522 // J = either J1 or J2 bit, 0 = zero. 523 // 524 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0 525 // 526 // Note that the halfwords are stored high first, low second; so we need 527 // to transpose the fixup value here to map properly. 528 uint32_t offset = (Value - 2) >> 2; 529 if (const MCSymbolRefExpr *SRE = 530 dyn_cast<MCSymbolRefExpr>(Fixup.getValue())) 531 if (SRE->getKind() == MCSymbolRefExpr::VK_ARM_TLSCALL) 532 offset = 0; 533 uint32_t signBit = (offset & 0x400000) >> 22; 534 uint32_t I1Bit = (offset & 0x200000) >> 21; 535 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit; 536 uint32_t I2Bit = (offset & 0x100000) >> 20; 537 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit; 538 uint32_t imm10HBits = (offset & 0xFFC00) >> 10; 539 uint32_t imm10LBits = (offset & 0x3FF); 540 541 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits); 542 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) | 543 ((uint16_t)imm10LBits) << 1); 544 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian); 545 } 546 case ARM::fixup_thumb_adr_pcrel_10: 547 case ARM::fixup_arm_thumb_cp: 548 // On CPUs supporting Thumb2, this will be relaxed to an ldr.w, otherwise we 549 // could have an error on our hands. 550 if (Ctx && !STI->getFeatureBits()[ARM::FeatureThumb2] && IsResolved) { 551 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value); 552 if (FixupDiagnostic) { 553 Ctx->reportError(Fixup.getLoc(), FixupDiagnostic); 554 return 0; 555 } 556 } 557 // Offset by 4, and don't encode the low two bits. 558 return ((Value - 4) >> 2) & 0xff; 559 case ARM::fixup_arm_thumb_cb: { 560 // Offset by 4 and don't encode the lower bit, which is always 0. 561 // FIXME: diagnose if no Thumb2 562 uint32_t Binary = (Value - 4) >> 1; 563 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3); 564 } 565 case ARM::fixup_arm_thumb_br: 566 // Offset by 4 and don't encode the lower bit, which is always 0. 567 if (Ctx && !STI->getFeatureBits()[ARM::FeatureThumb2] && 568 !STI->getFeatureBits()[ARM::HasV8MBaselineOps]) { 569 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value); 570 if (FixupDiagnostic) { 571 Ctx->reportError(Fixup.getLoc(), FixupDiagnostic); 572 return 0; 573 } 574 } 575 return ((Value - 4) >> 1) & 0x7ff; 576 case ARM::fixup_arm_thumb_bcc: 577 // Offset by 4 and don't encode the lower bit, which is always 0. 578 if (Ctx && !STI->getFeatureBits()[ARM::FeatureThumb2]) { 579 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value); 580 if (FixupDiagnostic) { 581 Ctx->reportError(Fixup.getLoc(), FixupDiagnostic); 582 return 0; 583 } 584 } 585 return ((Value - 4) >> 1) & 0xff; 586 case ARM::fixup_arm_pcrel_10_unscaled: { 587 Value = Value - 8; // ARM fixups offset by an additional word and don't 588 // need to adjust for the half-word ordering. 589 bool isAdd = true; 590 if ((int64_t)Value < 0) { 591 Value = -Value; 592 isAdd = false; 593 } 594 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8]. 595 if (Ctx && Value >= 256) { 596 Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 597 return 0; 598 } 599 Value = (Value & 0xf) | ((Value & 0xf0) << 4); 600 return Value | (isAdd << 23); 601 } 602 case ARM::fixup_arm_pcrel_10: 603 Value = Value - 4; // ARM fixups offset by an additional word and don't 604 // need to adjust for the half-word ordering. 605 // Fall through. 606 case ARM::fixup_t2_pcrel_10: { 607 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 608 Value = Value - 4; 609 bool isAdd = true; 610 if ((int64_t)Value < 0) { 611 Value = -Value; 612 isAdd = false; 613 } 614 // These values don't encode the low two bits since they're always zero. 615 Value >>= 2; 616 if (Ctx && Value >= 256) { 617 Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 618 return 0; 619 } 620 Value |= isAdd << 23; 621 622 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords 623 // swapped. 624 if (Kind == ARM::fixup_t2_pcrel_10) 625 return swapHalfWords(Value, IsLittleEndian); 626 627 return Value; 628 } 629 } 630 } 631 632 void ARMAsmBackend::processFixupValue(const MCAssembler &Asm, 633 const MCAsmLayout &Layout, 634 const MCFixup &Fixup, 635 const MCFragment *DF, 636 const MCValue &Target, uint64_t &Value, 637 bool &IsResolved) { 638 const MCSymbolRefExpr *A = Target.getSymA(); 639 const MCSymbol *Sym = A ? &A->getSymbol() : nullptr; 640 // Some fixups to thumb function symbols need the low bit (thumb bit) 641 // twiddled. 642 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 && 643 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 && 644 (unsigned)Fixup.getKind() != ARM::fixup_arm_adr_pcrel_12 && 645 (unsigned)Fixup.getKind() != ARM::fixup_thumb_adr_pcrel_10 && 646 (unsigned)Fixup.getKind() != ARM::fixup_t2_adr_pcrel_12 && 647 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) { 648 if (Sym) { 649 if (Asm.isThumbFunc(Sym)) 650 Value |= 1; 651 } 652 } 653 if (IsResolved && (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl) { 654 assert(Sym && "How did we resolve this?"); 655 656 // If the symbol is external the linker will handle it. 657 // FIXME: Should we handle it as an optimization? 658 659 // If the symbol is out of range, produce a relocation and hope the 660 // linker can handle it. GNU AS produces an error in this case. 661 if (Sym->isExternal() || Value >= 0x400004) 662 IsResolved = false; 663 } 664 // We must always generate a relocation for BL/BLX instructions if we have 665 // a symbol to reference, as the linker relies on knowing the destination 666 // symbol's thumb-ness to get interworking right. 667 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx || 668 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx || 669 (unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl || 670 (unsigned)Fixup.getKind() == ARM::fixup_arm_condbl)) 671 IsResolved = false; 672 673 // Try to get the encoded value for the fixup as-if we're mapping it into 674 // the instruction. This allows adjustFixupValue() to issue a diagnostic 675 // if the value aren't invalid. 676 (void)adjustFixupValue(Fixup, Value, false, &Asm.getContext(), 677 IsLittleEndian, IsResolved); 678 } 679 680 /// getFixupKindNumBytes - The number of bytes the fixup may change. 681 static unsigned getFixupKindNumBytes(unsigned Kind) { 682 switch (Kind) { 683 default: 684 llvm_unreachable("Unknown fixup kind!"); 685 686 case FK_Data_1: 687 case ARM::fixup_arm_thumb_bcc: 688 case ARM::fixup_arm_thumb_cp: 689 case ARM::fixup_thumb_adr_pcrel_10: 690 return 1; 691 692 case FK_Data_2: 693 case ARM::fixup_arm_thumb_br: 694 case ARM::fixup_arm_thumb_cb: 695 return 2; 696 697 case ARM::fixup_arm_pcrel_10_unscaled: 698 case ARM::fixup_arm_ldst_pcrel_12: 699 case ARM::fixup_arm_pcrel_10: 700 case ARM::fixup_arm_adr_pcrel_12: 701 case ARM::fixup_arm_uncondbl: 702 case ARM::fixup_arm_condbl: 703 case ARM::fixup_arm_blx: 704 case ARM::fixup_arm_condbranch: 705 case ARM::fixup_arm_uncondbranch: 706 return 3; 707 708 case FK_Data_4: 709 case ARM::fixup_t2_ldst_pcrel_12: 710 case ARM::fixup_t2_condbranch: 711 case ARM::fixup_t2_uncondbranch: 712 case ARM::fixup_t2_pcrel_10: 713 case ARM::fixup_t2_adr_pcrel_12: 714 case ARM::fixup_arm_thumb_bl: 715 case ARM::fixup_arm_thumb_blx: 716 case ARM::fixup_arm_movt_hi16: 717 case ARM::fixup_arm_movw_lo16: 718 case ARM::fixup_t2_movt_hi16: 719 case ARM::fixup_t2_movw_lo16: 720 return 4; 721 722 case FK_SecRel_2: 723 return 2; 724 case FK_SecRel_4: 725 return 4; 726 } 727 } 728 729 /// getFixupKindContainerSizeBytes - The number of bytes of the 730 /// container involved in big endian. 731 static unsigned getFixupKindContainerSizeBytes(unsigned Kind) { 732 switch (Kind) { 733 default: 734 llvm_unreachable("Unknown fixup kind!"); 735 736 case FK_Data_1: 737 return 1; 738 case FK_Data_2: 739 return 2; 740 case FK_Data_4: 741 return 4; 742 743 case ARM::fixup_arm_thumb_bcc: 744 case ARM::fixup_arm_thumb_cp: 745 case ARM::fixup_thumb_adr_pcrel_10: 746 case ARM::fixup_arm_thumb_br: 747 case ARM::fixup_arm_thumb_cb: 748 // Instruction size is 2 bytes. 749 return 2; 750 751 case ARM::fixup_arm_pcrel_10_unscaled: 752 case ARM::fixup_arm_ldst_pcrel_12: 753 case ARM::fixup_arm_pcrel_10: 754 case ARM::fixup_arm_adr_pcrel_12: 755 case ARM::fixup_arm_uncondbl: 756 case ARM::fixup_arm_condbl: 757 case ARM::fixup_arm_blx: 758 case ARM::fixup_arm_condbranch: 759 case ARM::fixup_arm_uncondbranch: 760 case ARM::fixup_t2_ldst_pcrel_12: 761 case ARM::fixup_t2_condbranch: 762 case ARM::fixup_t2_uncondbranch: 763 case ARM::fixup_t2_pcrel_10: 764 case ARM::fixup_t2_adr_pcrel_12: 765 case ARM::fixup_arm_thumb_bl: 766 case ARM::fixup_arm_thumb_blx: 767 case ARM::fixup_arm_movt_hi16: 768 case ARM::fixup_arm_movw_lo16: 769 case ARM::fixup_t2_movt_hi16: 770 case ARM::fixup_t2_movw_lo16: 771 // Instruction size is 4 bytes. 772 return 4; 773 } 774 } 775 776 void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 777 unsigned DataSize, uint64_t Value, 778 bool IsPCRel) const { 779 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 780 Value = 781 adjustFixupValue(Fixup, Value, IsPCRel, nullptr, IsLittleEndian, true); 782 if (!Value) 783 return; // Doesn't change encoding. 784 785 unsigned Offset = Fixup.getOffset(); 786 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!"); 787 788 // Used to point to big endian bytes. 789 unsigned FullSizeBytes; 790 if (!IsLittleEndian) { 791 FullSizeBytes = getFixupKindContainerSizeBytes(Fixup.getKind()); 792 assert((Offset + FullSizeBytes) <= DataSize && "Invalid fixup size!"); 793 assert(NumBytes <= FullSizeBytes && "Invalid fixup size!"); 794 } 795 796 // For each byte of the fragment that the fixup touches, mask in the bits from 797 // the fixup value. The Value has been "split up" into the appropriate 798 // bitfields above. 799 for (unsigned i = 0; i != NumBytes; ++i) { 800 unsigned Idx = IsLittleEndian ? i : (FullSizeBytes - 1 - i); 801 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff); 802 } 803 } 804 805 namespace CU { 806 807 /// \brief Compact unwind encoding values. 808 enum CompactUnwindEncodings { 809 UNWIND_ARM_MODE_MASK = 0x0F000000, 810 UNWIND_ARM_MODE_FRAME = 0x01000000, 811 UNWIND_ARM_MODE_FRAME_D = 0x02000000, 812 UNWIND_ARM_MODE_DWARF = 0x04000000, 813 814 UNWIND_ARM_FRAME_STACK_ADJUST_MASK = 0x00C00000, 815 816 UNWIND_ARM_FRAME_FIRST_PUSH_R4 = 0x00000001, 817 UNWIND_ARM_FRAME_FIRST_PUSH_R5 = 0x00000002, 818 UNWIND_ARM_FRAME_FIRST_PUSH_R6 = 0x00000004, 819 820 UNWIND_ARM_FRAME_SECOND_PUSH_R8 = 0x00000008, 821 UNWIND_ARM_FRAME_SECOND_PUSH_R9 = 0x00000010, 822 UNWIND_ARM_FRAME_SECOND_PUSH_R10 = 0x00000020, 823 UNWIND_ARM_FRAME_SECOND_PUSH_R11 = 0x00000040, 824 UNWIND_ARM_FRAME_SECOND_PUSH_R12 = 0x00000080, 825 826 UNWIND_ARM_FRAME_D_REG_COUNT_MASK = 0x00000F00, 827 828 UNWIND_ARM_DWARF_SECTION_OFFSET = 0x00FFFFFF 829 }; 830 831 } // end CU namespace 832 833 /// Generate compact unwind encoding for the function based on the CFI 834 /// instructions. If the CFI instructions describe a frame that cannot be 835 /// encoded in compact unwind, the method returns UNWIND_ARM_MODE_DWARF which 836 /// tells the runtime to fallback and unwind using dwarf. 837 uint32_t ARMAsmBackendDarwin::generateCompactUnwindEncoding( 838 ArrayRef<MCCFIInstruction> Instrs) const { 839 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "generateCU()\n"); 840 // Only armv7k uses CFI based unwinding. 841 if (Subtype != MachO::CPU_SUBTYPE_ARM_V7K) 842 return 0; 843 // No .cfi directives means no frame. 844 if (Instrs.empty()) 845 return 0; 846 // Start off assuming CFA is at SP+0. 847 int CFARegister = ARM::SP; 848 int CFARegisterOffset = 0; 849 // Mark savable registers as initially unsaved 850 DenseMap<unsigned, int> RegOffsets; 851 int FloatRegCount = 0; 852 // Process each .cfi directive and build up compact unwind info. 853 for (size_t i = 0, e = Instrs.size(); i != e; ++i) { 854 int Reg; 855 const MCCFIInstruction &Inst = Instrs[i]; 856 switch (Inst.getOperation()) { 857 case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa 858 CFARegisterOffset = -Inst.getOffset(); 859 CFARegister = MRI.getLLVMRegNum(Inst.getRegister(), true); 860 break; 861 case MCCFIInstruction::OpDefCfaOffset: // DW_CFA_def_cfa_offset 862 CFARegisterOffset = -Inst.getOffset(); 863 break; 864 case MCCFIInstruction::OpDefCfaRegister: // DW_CFA_def_cfa_register 865 CFARegister = MRI.getLLVMRegNum(Inst.getRegister(), true); 866 break; 867 case MCCFIInstruction::OpOffset: // DW_CFA_offset 868 Reg = MRI.getLLVMRegNum(Inst.getRegister(), true); 869 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 870 RegOffsets[Reg] = Inst.getOffset(); 871 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 872 RegOffsets[Reg] = Inst.getOffset(); 873 ++FloatRegCount; 874 } else { 875 DEBUG_WITH_TYPE("compact-unwind", 876 llvm::dbgs() << ".cfi_offset on unknown register=" 877 << Inst.getRegister() << "\n"); 878 return CU::UNWIND_ARM_MODE_DWARF; 879 } 880 break; 881 case MCCFIInstruction::OpRelOffset: // DW_CFA_advance_loc 882 // Ignore 883 break; 884 default: 885 // Directive not convertable to compact unwind, bail out. 886 DEBUG_WITH_TYPE("compact-unwind", 887 llvm::dbgs() 888 << "CFI directive not compatiable with comact " 889 "unwind encoding, opcode=" << Inst.getOperation() 890 << "\n"); 891 return CU::UNWIND_ARM_MODE_DWARF; 892 break; 893 } 894 } 895 896 // If no frame set up, return no unwind info. 897 if ((CFARegister == ARM::SP) && (CFARegisterOffset == 0)) 898 return 0; 899 900 // Verify standard frame (lr/r7) was used. 901 if (CFARegister != ARM::R7) { 902 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "frame register is " 903 << CFARegister 904 << " instead of r7\n"); 905 return CU::UNWIND_ARM_MODE_DWARF; 906 } 907 int StackAdjust = CFARegisterOffset - 8; 908 if (RegOffsets.lookup(ARM::LR) != (-4 - StackAdjust)) { 909 DEBUG_WITH_TYPE("compact-unwind", 910 llvm::dbgs() 911 << "LR not saved as standard frame, StackAdjust=" 912 << StackAdjust 913 << ", CFARegisterOffset=" << CFARegisterOffset 914 << ", lr save at offset=" << RegOffsets[14] << "\n"); 915 return CU::UNWIND_ARM_MODE_DWARF; 916 } 917 if (RegOffsets.lookup(ARM::R7) != (-8 - StackAdjust)) { 918 DEBUG_WITH_TYPE("compact-unwind", 919 llvm::dbgs() << "r7 not saved as standard frame\n"); 920 return CU::UNWIND_ARM_MODE_DWARF; 921 } 922 uint32_t CompactUnwindEncoding = CU::UNWIND_ARM_MODE_FRAME; 923 924 // If var-args are used, there may be a stack adjust required. 925 switch (StackAdjust) { 926 case 0: 927 break; 928 case 4: 929 CompactUnwindEncoding |= 0x00400000; 930 break; 931 case 8: 932 CompactUnwindEncoding |= 0x00800000; 933 break; 934 case 12: 935 CompactUnwindEncoding |= 0x00C00000; 936 break; 937 default: 938 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() 939 << ".cfi_def_cfa stack adjust (" 940 << StackAdjust << ") out of range\n"); 941 return CU::UNWIND_ARM_MODE_DWARF; 942 } 943 944 // If r6 is saved, it must be right below r7. 945 static struct { 946 unsigned Reg; 947 unsigned Encoding; 948 } GPRCSRegs[] = {{ARM::R6, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R6}, 949 {ARM::R5, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R5}, 950 {ARM::R4, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R4}, 951 {ARM::R12, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R12}, 952 {ARM::R11, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R11}, 953 {ARM::R10, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R10}, 954 {ARM::R9, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R9}, 955 {ARM::R8, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R8}}; 956 957 int CurOffset = -8 - StackAdjust; 958 for (auto CSReg : GPRCSRegs) { 959 auto Offset = RegOffsets.find(CSReg.Reg); 960 if (Offset == RegOffsets.end()) 961 continue; 962 963 int RegOffset = Offset->second; 964 if (RegOffset != CurOffset - 4) { 965 DEBUG_WITH_TYPE("compact-unwind", 966 llvm::dbgs() << MRI.getName(CSReg.Reg) << " saved at " 967 << RegOffset << " but only supported at " 968 << CurOffset << "\n"); 969 return CU::UNWIND_ARM_MODE_DWARF; 970 } 971 CompactUnwindEncoding |= CSReg.Encoding; 972 CurOffset -= 4; 973 } 974 975 // If no floats saved, we are done. 976 if (FloatRegCount == 0) 977 return CompactUnwindEncoding; 978 979 // Switch mode to include D register saving. 980 CompactUnwindEncoding &= ~CU::UNWIND_ARM_MODE_MASK; 981 CompactUnwindEncoding |= CU::UNWIND_ARM_MODE_FRAME_D; 982 983 // FIXME: supporting more than 4 saved D-registers compactly would be trivial, 984 // but needs coordination with the linker and libunwind. 985 if (FloatRegCount > 4) { 986 DEBUG_WITH_TYPE("compact-unwind", 987 llvm::dbgs() << "unsupported number of D registers saved (" 988 << FloatRegCount << ")\n"); 989 return CU::UNWIND_ARM_MODE_DWARF; 990 } 991 992 // Floating point registers must either be saved sequentially, or we defer to 993 // DWARF. No gaps allowed here so check that each saved d-register is 994 // precisely where it should be. 995 static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 }; 996 for (int Idx = FloatRegCount - 1; Idx >= 0; --Idx) { 997 auto Offset = RegOffsets.find(FPRCSRegs[Idx]); 998 if (Offset == RegOffsets.end()) { 999 DEBUG_WITH_TYPE("compact-unwind", 1000 llvm::dbgs() << FloatRegCount << " D-regs saved, but " 1001 << MRI.getName(FPRCSRegs[Idx]) 1002 << " not saved\n"); 1003 return CU::UNWIND_ARM_MODE_DWARF; 1004 } else if (Offset->second != CurOffset - 8) { 1005 DEBUG_WITH_TYPE("compact-unwind", 1006 llvm::dbgs() << FloatRegCount << " D-regs saved, but " 1007 << MRI.getName(FPRCSRegs[Idx]) 1008 << " saved at " << Offset->second 1009 << ", expected at " << CurOffset - 8 1010 << "\n"); 1011 return CU::UNWIND_ARM_MODE_DWARF; 1012 } 1013 CurOffset -= 8; 1014 } 1015 1016 return CompactUnwindEncoding | ((FloatRegCount - 1) << 8); 1017 } 1018 1019 static MachO::CPUSubTypeARM getMachOSubTypeFromArch(StringRef Arch) { 1020 unsigned AK = ARM::parseArch(Arch); 1021 switch (AK) { 1022 default: 1023 return MachO::CPU_SUBTYPE_ARM_V7; 1024 case ARM::AK_ARMV4T: 1025 return MachO::CPU_SUBTYPE_ARM_V4T; 1026 case ARM::AK_ARMV5T: 1027 case ARM::AK_ARMV5TE: 1028 case ARM::AK_ARMV5TEJ: 1029 return MachO::CPU_SUBTYPE_ARM_V5; 1030 case ARM::AK_ARMV6: 1031 case ARM::AK_ARMV6K: 1032 return MachO::CPU_SUBTYPE_ARM_V6; 1033 case ARM::AK_ARMV7A: 1034 return MachO::CPU_SUBTYPE_ARM_V7; 1035 case ARM::AK_ARMV7S: 1036 return MachO::CPU_SUBTYPE_ARM_V7S; 1037 case ARM::AK_ARMV7K: 1038 return MachO::CPU_SUBTYPE_ARM_V7K; 1039 case ARM::AK_ARMV6M: 1040 return MachO::CPU_SUBTYPE_ARM_V6M; 1041 case ARM::AK_ARMV7M: 1042 return MachO::CPU_SUBTYPE_ARM_V7M; 1043 case ARM::AK_ARMV7EM: 1044 return MachO::CPU_SUBTYPE_ARM_V7EM; 1045 } 1046 } 1047 1048 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, 1049 const MCRegisterInfo &MRI, 1050 const Triple &TheTriple, StringRef CPU, 1051 bool isLittle) { 1052 switch (TheTriple.getObjectFormat()) { 1053 default: 1054 llvm_unreachable("unsupported object format"); 1055 case Triple::MachO: { 1056 MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TheTriple.getArchName()); 1057 return new ARMAsmBackendDarwin(T, TheTriple, MRI, CS); 1058 } 1059 case Triple::COFF: 1060 assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported"); 1061 return new ARMAsmBackendWinCOFF(T, TheTriple); 1062 case Triple::ELF: 1063 assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target"); 1064 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); 1065 return new ARMAsmBackendELF(T, TheTriple, OSABI, isLittle); 1066 } 1067 } 1068 1069 MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T, 1070 const MCRegisterInfo &MRI, 1071 const Triple &TT, StringRef CPU) { 1072 return createARMAsmBackend(T, MRI, TT, CPU, true); 1073 } 1074 1075 MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T, 1076 const MCRegisterInfo &MRI, 1077 const Triple &TT, StringRef CPU) { 1078 return createARMAsmBackend(T, MRI, TT, CPU, false); 1079 } 1080 1081 MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T, 1082 const MCRegisterInfo &MRI, 1083 const Triple &TT, StringRef CPU) { 1084 return createARMAsmBackend(T, MRI, TT, CPU, true); 1085 } 1086 1087 MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T, 1088 const MCRegisterInfo &MRI, 1089 const Triple &TT, StringRef CPU) { 1090 return createARMAsmBackend(T, MRI, TT, CPU, false); 1091 } 1092