1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/ARMMCTargetDesc.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMFixupKinds.h" 13 #include "MCTargetDesc/ARMAddressingModes.h" 14 #include "llvm/ADT/Twine.h" 15 #include "llvm/MC/MCAssembler.h" 16 #include "llvm/MC/MCDirectives.h" 17 #include "llvm/MC/MCELFObjectWriter.h" 18 #include "llvm/MC/MCExpr.h" 19 #include "llvm/MC/MCMachObjectWriter.h" 20 #include "llvm/MC/MCObjectWriter.h" 21 #include "llvm/MC/MCSectionELF.h" 22 #include "llvm/MC/MCSectionMachO.h" 23 #include "llvm/MC/MCAsmBackend.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/Object/MachOFormat.h" 26 #include "llvm/Support/ELF.h" 27 #include "llvm/Support/ErrorHandling.h" 28 #include "llvm/Support/raw_ostream.h" 29 using namespace llvm; 30 31 namespace { 32 class ARMELFObjectWriter : public MCELFObjectTargetWriter { 33 public: 34 ARMELFObjectWriter(Triple::OSType OSType) 35 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSType, ELF::EM_ARM, 36 /*HasRelocationAddend*/ false) {} 37 }; 38 39 class ARMAsmBackend : public MCAsmBackend { 40 const MCSubtargetInfo* STI; 41 bool isThumbMode; // Currently emitting Thumb code. 42 public: 43 ARMAsmBackend(const Target &T, const StringRef TT) 44 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")), 45 isThumbMode(TT.startswith("thumb")) {} 46 47 ~ARMAsmBackend() { 48 delete STI; 49 } 50 51 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; } 52 53 bool hasNOP() const { 54 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0; 55 } 56 57 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { 58 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = { 59 // This table *must* be in the order that the fixup_* kinds are defined in 60 // ARMFixupKinds.h. 61 // 62 // Name Offset (bits) Size (bits) Flags 63 { "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 64 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 65 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 66 { "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 67 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 68 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 69 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel | 70 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 71 { "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 72 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 73 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 74 { "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 75 { "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 76 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 77 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 78 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 79 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 80 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 81 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 82 { "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel }, 83 { "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel }, 84 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19. 85 { "fixup_arm_movt_hi16", 0, 20, 0 }, 86 { "fixup_arm_movw_lo16", 0, 20, 0 }, 87 { "fixup_t2_movt_hi16", 0, 20, 0 }, 88 { "fixup_t2_movw_lo16", 0, 20, 0 }, 89 { "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 90 { "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 91 { "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 92 { "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 93 }; 94 95 if (Kind < FirstTargetFixupKind) 96 return MCAsmBackend::getFixupKindInfo(Kind); 97 98 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 99 "Invalid kind!"); 100 return Infos[Kind - FirstTargetFixupKind]; 101 } 102 103 bool MayNeedRelaxation(const MCInst &Inst) const; 104 105 bool fixupNeedsRelaxation(const MCFixup &Fixup, 106 uint64_t Value, 107 const MCInstFragment *DF, 108 const MCAsmLayout &Layout) const; 109 110 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const; 111 112 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const; 113 114 void HandleAssemblerFlag(MCAssemblerFlag Flag) { 115 switch (Flag) { 116 default: break; 117 case MCAF_Code16: 118 setIsThumb(true); 119 break; 120 case MCAF_Code32: 121 setIsThumb(false); 122 break; 123 } 124 } 125 126 unsigned getPointerSize() const { return 4; } 127 bool isThumb() const { return isThumbMode; } 128 void setIsThumb(bool it) { isThumbMode = it; } 129 }; 130 } // end anonymous namespace 131 132 static unsigned getRelaxedOpcode(unsigned Op) { 133 switch (Op) { 134 default: return Op; 135 case ARM::tBcc: return ARM::t2Bcc; 136 } 137 } 138 139 bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const { 140 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode()) 141 return true; 142 return false; 143 } 144 145 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, 146 uint64_t Value, 147 const MCInstFragment *DF, 148 const MCAsmLayout &Layout) const { 149 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the 150 // low bit being an implied zero. There's an implied +4 offset for the 151 // branch, so we adjust the other way here to determine what's 152 // encodable. 153 // 154 // Relax if the value is too big for a (signed) i8. 155 int64_t Offset = int64_t(Value) - 4; 156 return Offset > 254 || Offset < -256; 157 } 158 159 void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const { 160 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode()); 161 162 // Sanity check w/ diagnostic if we get here w/ a bogus instruction. 163 if (RelaxedOp == Inst.getOpcode()) { 164 SmallString<256> Tmp; 165 raw_svector_ostream OS(Tmp); 166 Inst.dump_pretty(OS); 167 OS << "\n"; 168 report_fatal_error("unexpected instruction to relax: " + OS.str()); 169 } 170 171 // The instructions we're relaxing have (so far) the same operands. 172 // We just need to update to the proper opcode. 173 Res = Inst; 174 Res.setOpcode(RelaxedOp); 175 } 176 177 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const { 178 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8 179 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP 180 const uint32_t ARMv4_NopEncoding = 0xe1a0000; // using MOV r0,r0 181 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP 182 if (isThumb()) { 183 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding 184 : Thumb1_16bitNopEncoding; 185 uint64_t NumNops = Count / 2; 186 for (uint64_t i = 0; i != NumNops; ++i) 187 OW->Write16(nopEncoding); 188 if (Count & 1) 189 OW->Write8(0); 190 return true; 191 } 192 // ARM mode 193 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding 194 : ARMv4_NopEncoding; 195 uint64_t NumNops = Count / 4; 196 for (uint64_t i = 0; i != NumNops; ++i) 197 OW->Write32(nopEncoding); 198 // FIXME: should this function return false when unable to write exactly 199 // 'Count' bytes with NOP encodings? 200 switch (Count % 4) { 201 default: break; // No leftover bytes to write 202 case 1: OW->Write8(0); break; 203 case 2: OW->Write16(0); break; 204 case 3: OW->Write16(0); OW->Write8(0xa0); break; 205 } 206 207 return true; 208 } 209 210 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { 211 switch (Kind) { 212 default: 213 llvm_unreachable("Unknown fixup kind!"); 214 case FK_Data_1: 215 case FK_Data_2: 216 case FK_Data_4: 217 return Value; 218 case ARM::fixup_arm_movt_hi16: 219 Value >>= 16; 220 // Fallthrough 221 case ARM::fixup_arm_movw_lo16: 222 case ARM::fixup_arm_movt_hi16_pcrel: 223 case ARM::fixup_arm_movw_lo16_pcrel: { 224 unsigned Hi4 = (Value & 0xF000) >> 12; 225 unsigned Lo12 = Value & 0x0FFF; 226 // inst{19-16} = Hi4; 227 // inst{11-0} = Lo12; 228 Value = (Hi4 << 16) | (Lo12); 229 return Value; 230 } 231 case ARM::fixup_t2_movt_hi16: 232 Value >>= 16; 233 // Fallthrough 234 case ARM::fixup_t2_movw_lo16: 235 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like 236 // the other hi16 fixup? 237 case ARM::fixup_t2_movw_lo16_pcrel: { 238 unsigned Hi4 = (Value & 0xF000) >> 12; 239 unsigned i = (Value & 0x800) >> 11; 240 unsigned Mid3 = (Value & 0x700) >> 8; 241 unsigned Lo8 = Value & 0x0FF; 242 // inst{19-16} = Hi4; 243 // inst{26} = i; 244 // inst{14-12} = Mid3; 245 // inst{7-0} = Lo8; 246 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8); 247 uint64_t swapped = (Value & 0xFFFF0000) >> 16; 248 swapped |= (Value & 0x0000FFFF) << 16; 249 return swapped; 250 } 251 case ARM::fixup_arm_ldst_pcrel_12: 252 // ARM PC-relative values are offset by 8. 253 Value -= 4; 254 // FALLTHROUGH 255 case ARM::fixup_t2_ldst_pcrel_12: { 256 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 257 Value -= 4; 258 bool isAdd = true; 259 if ((int64_t)Value < 0) { 260 Value = -Value; 261 isAdd = false; 262 } 263 assert ((Value < 4096) && "Out of range pc-relative fixup value!"); 264 Value |= isAdd << 23; 265 266 // Same addressing mode as fixup_arm_pcrel_10, 267 // but with 16-bit halfwords swapped. 268 if (Kind == ARM::fixup_t2_ldst_pcrel_12) { 269 uint64_t swapped = (Value & 0xFFFF0000) >> 16; 270 swapped |= (Value & 0x0000FFFF) << 16; 271 return swapped; 272 } 273 274 return Value; 275 } 276 case ARM::fixup_thumb_adr_pcrel_10: 277 return ((Value - 4) >> 2) & 0xff; 278 case ARM::fixup_arm_adr_pcrel_12: { 279 // ARM PC-relative values are offset by 8. 280 Value -= 8; 281 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 282 if ((int64_t)Value < 0) { 283 Value = -Value; 284 opc = 2; // 0b0010 285 } 286 assert(ARM_AM::getSOImmVal(Value) != -1 && 287 "Out of range pc-relative fixup value!"); 288 // Encode the immediate and shift the opcode into place. 289 return ARM_AM::getSOImmVal(Value) | (opc << 21); 290 } 291 292 case ARM::fixup_t2_adr_pcrel_12: { 293 Value -= 4; 294 unsigned opc = 0; 295 if ((int64_t)Value < 0) { 296 Value = -Value; 297 opc = 5; 298 } 299 300 uint32_t out = (opc << 21); 301 out |= (Value & 0x800) << 15; 302 out |= (Value & 0x700) << 4; 303 out |= (Value & 0x0FF); 304 305 uint64_t swapped = (out & 0xFFFF0000) >> 16; 306 swapped |= (out & 0x0000FFFF) << 16; 307 return swapped; 308 } 309 310 case ARM::fixup_arm_condbranch: 311 case ARM::fixup_arm_uncondbranch: 312 // These values don't encode the low two bits since they're always zero. 313 // Offset by 8 just as above. 314 return 0xffffff & ((Value - 8) >> 2); 315 case ARM::fixup_t2_uncondbranch: { 316 Value = Value - 4; 317 Value >>= 1; // Low bit is not encoded. 318 319 uint32_t out = 0; 320 bool I = Value & 0x800000; 321 bool J1 = Value & 0x400000; 322 bool J2 = Value & 0x200000; 323 J1 ^= I; 324 J2 ^= I; 325 326 out |= I << 26; // S bit 327 out |= !J1 << 13; // J1 bit 328 out |= !J2 << 11; // J2 bit 329 out |= (Value & 0x1FF800) << 5; // imm6 field 330 out |= (Value & 0x0007FF); // imm11 field 331 332 uint64_t swapped = (out & 0xFFFF0000) >> 16; 333 swapped |= (out & 0x0000FFFF) << 16; 334 return swapped; 335 } 336 case ARM::fixup_t2_condbranch: { 337 Value = Value - 4; 338 Value >>= 1; // Low bit is not encoded. 339 340 uint64_t out = 0; 341 out |= (Value & 0x80000) << 7; // S bit 342 out |= (Value & 0x40000) >> 7; // J2 bit 343 out |= (Value & 0x20000) >> 4; // J1 bit 344 out |= (Value & 0x1F800) << 5; // imm6 field 345 out |= (Value & 0x007FF); // imm11 field 346 347 uint32_t swapped = (out & 0xFFFF0000) >> 16; 348 swapped |= (out & 0x0000FFFF) << 16; 349 return swapped; 350 } 351 case ARM::fixup_arm_thumb_bl: { 352 // The value doesn't encode the low bit (always zero) and is offset by 353 // four. The value is encoded into disjoint bit positions in the destination 354 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit 355 // 356 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII 357 // 358 // Note that the halfwords are stored high first, low second; so we need 359 // to transpose the fixup value here to map properly. 360 unsigned isNeg = (int64_t(Value - 4) < 0) ? 1 : 0; 361 uint32_t Binary = 0; 362 Value = 0x3fffff & ((Value - 4) >> 1); 363 Binary = (Value & 0x7ff) << 16; // Low imm11 value. 364 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value. 365 Binary |= isNeg << 10; // Sign bit. 366 return Binary; 367 } 368 case ARM::fixup_arm_thumb_blx: { 369 // The value doesn't encode the low two bits (always zero) and is offset by 370 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit 371 // positions in the destination opcode. x = unchanged, I = immediate value 372 // bit, S = sign extension bit, 0 = zero. 373 // 374 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0 375 // 376 // Note that the halfwords are stored high first, low second; so we need 377 // to transpose the fixup value here to map properly. 378 unsigned isNeg = (int64_t(Value-4) < 0) ? 1 : 0; 379 uint32_t Binary = 0; 380 Value = 0xfffff & ((Value - 2) >> 2); 381 Binary = (Value & 0x3ff) << 17; // Low imm10L value. 382 Binary |= (Value & 0xffc00) >> 10; // High imm10H value. 383 Binary |= isNeg << 10; // Sign bit. 384 return Binary; 385 } 386 case ARM::fixup_arm_thumb_cp: 387 // Offset by 4, and don't encode the low two bits. Two bytes of that 388 // 'off by 4' is implicitly handled by the half-word ordering of the 389 // Thumb encoding, so we only need to adjust by 2 here. 390 return ((Value - 2) >> 2) & 0xff; 391 case ARM::fixup_arm_thumb_cb: { 392 // Offset by 4 and don't encode the lower bit, which is always 0. 393 uint32_t Binary = (Value - 4) >> 1; 394 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3); 395 } 396 case ARM::fixup_arm_thumb_br: 397 // Offset by 4 and don't encode the lower bit, which is always 0. 398 return ((Value - 4) >> 1) & 0x7ff; 399 case ARM::fixup_arm_thumb_bcc: 400 // Offset by 4 and don't encode the lower bit, which is always 0. 401 return ((Value - 4) >> 1) & 0xff; 402 case ARM::fixup_arm_pcrel_10: 403 Value = Value - 4; // ARM fixups offset by an additional word and don't 404 // need to adjust for the half-word ordering. 405 // Fall through. 406 case ARM::fixup_t2_pcrel_10: { 407 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 408 Value = Value - 4; 409 bool isAdd = true; 410 if ((int64_t)Value < 0) { 411 Value = -Value; 412 isAdd = false; 413 } 414 // These values don't encode the low two bits since they're always zero. 415 Value >>= 2; 416 assert ((Value < 256) && "Out of range pc-relative fixup value!"); 417 Value |= isAdd << 23; 418 419 // Same addressing mode as fixup_arm_pcrel_10, 420 // but with 16-bit halfwords swapped. 421 if (Kind == ARM::fixup_t2_pcrel_10) { 422 uint32_t swapped = (Value & 0xFFFF0000) >> 16; 423 swapped |= (Value & 0x0000FFFF) << 16; 424 return swapped; 425 } 426 427 return Value; 428 } 429 } 430 } 431 432 namespace { 433 434 // FIXME: This should be in a separate file. 435 // ELF is an ELF of course... 436 class ELFARMAsmBackend : public ARMAsmBackend { 437 public: 438 Triple::OSType OSType; 439 ELFARMAsmBackend(const Target &T, const StringRef TT, 440 Triple::OSType _OSType) 441 : ARMAsmBackend(T, TT), OSType(_OSType) { } 442 443 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 444 uint64_t Value) const; 445 446 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 447 return createELFObjectWriter(new ARMELFObjectWriter(OSType), OS, 448 /*IsLittleEndian*/ true); 449 } 450 }; 451 452 // FIXME: Raise this to share code between Darwin and ELF. 453 void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data, 454 unsigned DataSize, uint64_t Value) const { 455 unsigned NumBytes = 4; // FIXME: 2 for Thumb 456 Value = adjustFixupValue(Fixup.getKind(), Value); 457 if (!Value) return; // Doesn't change encoding. 458 459 unsigned Offset = Fixup.getOffset(); 460 461 // For each byte of the fragment that the fixup touches, mask in the bits from 462 // the fixup value. The Value has been "split up" into the appropriate 463 // bitfields above. 464 for (unsigned i = 0; i != NumBytes; ++i) 465 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 466 } 467 468 // FIXME: This should be in a separate file. 469 class DarwinARMAsmBackend : public ARMAsmBackend { 470 public: 471 const object::mach::CPUSubtypeARM Subtype; 472 DarwinARMAsmBackend(const Target &T, const StringRef TT, 473 object::mach::CPUSubtypeARM st) 474 : ARMAsmBackend(T, TT), Subtype(st) { } 475 476 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 477 return createARMMachObjectWriter(OS, /*Is64Bit=*/false, 478 object::mach::CTM_ARM, 479 Subtype); 480 } 481 482 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 483 uint64_t Value) const; 484 485 virtual bool doesSectionRequireSymbols(const MCSection &Section) const { 486 return false; 487 } 488 }; 489 490 /// getFixupKindNumBytes - The number of bytes the fixup may change. 491 static unsigned getFixupKindNumBytes(unsigned Kind) { 492 switch (Kind) { 493 default: 494 llvm_unreachable("Unknown fixup kind!"); 495 496 case FK_Data_1: 497 case ARM::fixup_arm_thumb_bcc: 498 case ARM::fixup_arm_thumb_cp: 499 case ARM::fixup_thumb_adr_pcrel_10: 500 return 1; 501 502 case FK_Data_2: 503 case ARM::fixup_arm_thumb_br: 504 case ARM::fixup_arm_thumb_cb: 505 return 2; 506 507 case ARM::fixup_arm_ldst_pcrel_12: 508 case ARM::fixup_arm_pcrel_10: 509 case ARM::fixup_arm_adr_pcrel_12: 510 case ARM::fixup_arm_condbranch: 511 case ARM::fixup_arm_uncondbranch: 512 return 3; 513 514 case FK_Data_4: 515 case ARM::fixup_t2_ldst_pcrel_12: 516 case ARM::fixup_t2_condbranch: 517 case ARM::fixup_t2_uncondbranch: 518 case ARM::fixup_t2_pcrel_10: 519 case ARM::fixup_t2_adr_pcrel_12: 520 case ARM::fixup_arm_thumb_bl: 521 case ARM::fixup_arm_thumb_blx: 522 case ARM::fixup_arm_movt_hi16: 523 case ARM::fixup_arm_movw_lo16: 524 case ARM::fixup_arm_movt_hi16_pcrel: 525 case ARM::fixup_arm_movw_lo16_pcrel: 526 case ARM::fixup_t2_movt_hi16: 527 case ARM::fixup_t2_movw_lo16: 528 case ARM::fixup_t2_movt_hi16_pcrel: 529 case ARM::fixup_t2_movw_lo16_pcrel: 530 return 4; 531 } 532 } 533 534 void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data, 535 unsigned DataSize, uint64_t Value) const { 536 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 537 Value = adjustFixupValue(Fixup.getKind(), Value); 538 if (!Value) return; // Doesn't change encoding. 539 540 unsigned Offset = Fixup.getOffset(); 541 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!"); 542 543 // For each byte of the fragment that the fixup touches, mask in the 544 // bits from the fixup value. 545 for (unsigned i = 0; i != NumBytes; ++i) 546 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 547 } 548 549 } // end anonymous namespace 550 551 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, StringRef TT) { 552 Triple TheTriple(TT); 553 554 if (TheTriple.isOSDarwin()) { 555 if (TheTriple.getArchName() == "armv4t" || 556 TheTriple.getArchName() == "thumbv4t") 557 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V4T); 558 else if (TheTriple.getArchName() == "armv5e" || 559 TheTriple.getArchName() == "thumbv5e") 560 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V5TEJ); 561 else if (TheTriple.getArchName() == "armv6" || 562 TheTriple.getArchName() == "thumbv6") 563 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V6); 564 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7); 565 } 566 567 if (TheTriple.isOSWindows()) 568 assert(0 && "Windows not supported on ARM"); 569 570 return new ELFARMAsmBackend(T, TT, Triple(TT).getOS()); 571 } 572