1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/ARMMCTargetDesc.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "MCTargetDesc/ARMBaseInfo.h" 13 #include "MCTargetDesc/ARMFixupKinds.h" 14 #include "llvm/MC/MCAsmBackend.h" 15 #include "llvm/MC/MCAssembler.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCDirectives.h" 18 #include "llvm/MC/MCELFObjectWriter.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCFixupKindInfo.h" 21 #include "llvm/MC/MCMachObjectWriter.h" 22 #include "llvm/MC/MCObjectWriter.h" 23 #include "llvm/MC/MCSectionELF.h" 24 #include "llvm/MC/MCSectionMachO.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/MC/MCValue.h" 27 #include "llvm/Object/MachOFormat.h" 28 #include "llvm/Support/ELF.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/raw_ostream.h" 31 using namespace llvm; 32 33 namespace { 34 class ARMELFObjectWriter : public MCELFObjectTargetWriter { 35 public: 36 ARMELFObjectWriter(uint8_t OSABI) 37 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM, 38 /*HasRelocationAddend*/ false) {} 39 }; 40 41 class ARMAsmBackend : public MCAsmBackend { 42 const MCSubtargetInfo* STI; 43 bool isThumbMode; // Currently emitting Thumb code. 44 public: 45 ARMAsmBackend(const Target &T, const StringRef TT) 46 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")), 47 isThumbMode(TT.startswith("thumb")) {} 48 49 ~ARMAsmBackend() { 50 delete STI; 51 } 52 53 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; } 54 55 bool hasNOP() const { 56 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0; 57 } 58 59 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { 60 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = { 61 // This table *must* be in the order that the fixup_* kinds are defined in 62 // ARMFixupKinds.h. 63 // 64 // Name Offset (bits) Size (bits) Flags 65 { "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 66 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 67 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 68 { "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 69 { "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 70 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 71 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 72 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel | 73 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 74 { "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 75 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 76 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 77 { "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 78 { "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 79 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 80 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 81 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 82 { "fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 83 { "fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 84 { "fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 85 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 86 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 87 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 88 { "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel | 89 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 90 { "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel }, 91 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19. 92 { "fixup_arm_movt_hi16", 0, 20, 0 }, 93 { "fixup_arm_movw_lo16", 0, 20, 0 }, 94 { "fixup_t2_movt_hi16", 0, 20, 0 }, 95 { "fixup_t2_movw_lo16", 0, 20, 0 }, 96 { "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 97 { "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 98 { "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 99 { "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 100 }; 101 102 if (Kind < FirstTargetFixupKind) 103 return MCAsmBackend::getFixupKindInfo(Kind); 104 105 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 106 "Invalid kind!"); 107 return Infos[Kind - FirstTargetFixupKind]; 108 } 109 110 /// processFixupValue - Target hook to process the literal value of a fixup 111 /// if necessary. 112 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout, 113 const MCFixup &Fixup, const MCFragment *DF, 114 MCValue &Target, uint64_t &Value, 115 bool &IsResolved); 116 117 118 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 119 uint64_t Value) const; 120 121 bool mayNeedRelaxation(const MCInst &Inst) const; 122 123 bool fixupNeedsRelaxation(const MCFixup &Fixup, 124 uint64_t Value, 125 const MCRelaxableFragment *DF, 126 const MCAsmLayout &Layout) const; 127 128 void relaxInstruction(const MCInst &Inst, MCInst &Res) const; 129 130 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const; 131 132 void handleAssemblerFlag(MCAssemblerFlag Flag) { 133 switch (Flag) { 134 default: break; 135 case MCAF_Code16: 136 setIsThumb(true); 137 break; 138 case MCAF_Code32: 139 setIsThumb(false); 140 break; 141 } 142 } 143 144 unsigned getPointerSize() const { return 4; } 145 bool isThumb() const { return isThumbMode; } 146 void setIsThumb(bool it) { isThumbMode = it; } 147 }; 148 } // end anonymous namespace 149 150 static unsigned getRelaxedOpcode(unsigned Op) { 151 switch (Op) { 152 default: return Op; 153 case ARM::tBcc: return ARM::t2Bcc; 154 case ARM::tLDRpciASM: return ARM::t2LDRpci; 155 case ARM::tADR: return ARM::t2ADR; 156 case ARM::tB: return ARM::t2B; 157 } 158 } 159 160 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 161 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode()) 162 return true; 163 return false; 164 } 165 166 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, 167 uint64_t Value, 168 const MCRelaxableFragment *DF, 169 const MCAsmLayout &Layout) const { 170 switch ((unsigned)Fixup.getKind()) { 171 case ARM::fixup_arm_thumb_br: { 172 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the 173 // low bit being an implied zero. There's an implied +4 offset for the 174 // branch, so we adjust the other way here to determine what's 175 // encodable. 176 // 177 // Relax if the value is too big for a (signed) i8. 178 int64_t Offset = int64_t(Value) - 4; 179 return Offset > 2046 || Offset < -2048; 180 } 181 case ARM::fixup_arm_thumb_bcc: { 182 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the 183 // low bit being an implied zero. There's an implied +4 offset for the 184 // branch, so we adjust the other way here to determine what's 185 // encodable. 186 // 187 // Relax if the value is too big for a (signed) i8. 188 int64_t Offset = int64_t(Value) - 4; 189 return Offset > 254 || Offset < -256; 190 } 191 case ARM::fixup_thumb_adr_pcrel_10: 192 case ARM::fixup_arm_thumb_cp: { 193 // If the immediate is negative, greater than 1020, or not a multiple 194 // of four, the wide version of the instruction must be used. 195 int64_t Offset = int64_t(Value) - 4; 196 return Offset > 1020 || Offset < 0 || Offset & 3; 197 } 198 } 199 llvm_unreachable("Unexpected fixup kind in fixupNeedsRelaxation()!"); 200 } 201 202 void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const { 203 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode()); 204 205 // Sanity check w/ diagnostic if we get here w/ a bogus instruction. 206 if (RelaxedOp == Inst.getOpcode()) { 207 SmallString<256> Tmp; 208 raw_svector_ostream OS(Tmp); 209 Inst.dump_pretty(OS); 210 OS << "\n"; 211 report_fatal_error("unexpected instruction to relax: " + OS.str()); 212 } 213 214 // The instructions we're relaxing have (so far) the same operands. 215 // We just need to update to the proper opcode. 216 Res = Inst; 217 Res.setOpcode(RelaxedOp); 218 } 219 220 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 221 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8 222 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP 223 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0 224 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP 225 if (isThumb()) { 226 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding 227 : Thumb1_16bitNopEncoding; 228 uint64_t NumNops = Count / 2; 229 for (uint64_t i = 0; i != NumNops; ++i) 230 OW->Write16(nopEncoding); 231 if (Count & 1) 232 OW->Write8(0); 233 return true; 234 } 235 // ARM mode 236 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding 237 : ARMv4_NopEncoding; 238 uint64_t NumNops = Count / 4; 239 for (uint64_t i = 0; i != NumNops; ++i) 240 OW->Write32(nopEncoding); 241 // FIXME: should this function return false when unable to write exactly 242 // 'Count' bytes with NOP encodings? 243 switch (Count % 4) { 244 default: break; // No leftover bytes to write 245 case 1: OW->Write8(0); break; 246 case 2: OW->Write16(0); break; 247 case 3: OW->Write16(0); OW->Write8(0xa0); break; 248 } 249 250 return true; 251 } 252 253 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, 254 MCContext *Ctx = NULL) { 255 unsigned Kind = Fixup.getKind(); 256 switch (Kind) { 257 default: 258 llvm_unreachable("Unknown fixup kind!"); 259 case FK_Data_1: 260 case FK_Data_2: 261 case FK_Data_4: 262 return Value; 263 case ARM::fixup_arm_movt_hi16: 264 Value >>= 16; 265 // Fallthrough 266 case ARM::fixup_arm_movw_lo16: 267 case ARM::fixup_arm_movt_hi16_pcrel: 268 case ARM::fixup_arm_movw_lo16_pcrel: { 269 unsigned Hi4 = (Value & 0xF000) >> 12; 270 unsigned Lo12 = Value & 0x0FFF; 271 // inst{19-16} = Hi4; 272 // inst{11-0} = Lo12; 273 Value = (Hi4 << 16) | (Lo12); 274 return Value; 275 } 276 case ARM::fixup_t2_movt_hi16: 277 Value >>= 16; 278 // Fallthrough 279 case ARM::fixup_t2_movw_lo16: 280 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like 281 // the other hi16 fixup? 282 case ARM::fixup_t2_movw_lo16_pcrel: { 283 unsigned Hi4 = (Value & 0xF000) >> 12; 284 unsigned i = (Value & 0x800) >> 11; 285 unsigned Mid3 = (Value & 0x700) >> 8; 286 unsigned Lo8 = Value & 0x0FF; 287 // inst{19-16} = Hi4; 288 // inst{26} = i; 289 // inst{14-12} = Mid3; 290 // inst{7-0} = Lo8; 291 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8); 292 uint64_t swapped = (Value & 0xFFFF0000) >> 16; 293 swapped |= (Value & 0x0000FFFF) << 16; 294 return swapped; 295 } 296 case ARM::fixup_arm_ldst_pcrel_12: 297 // ARM PC-relative values are offset by 8. 298 Value -= 4; 299 // FALLTHROUGH 300 case ARM::fixup_t2_ldst_pcrel_12: { 301 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 302 Value -= 4; 303 bool isAdd = true; 304 if ((int64_t)Value < 0) { 305 Value = -Value; 306 isAdd = false; 307 } 308 if (Ctx && Value >= 4096) 309 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value"); 310 Value |= isAdd << 23; 311 312 // Same addressing mode as fixup_arm_pcrel_10, 313 // but with 16-bit halfwords swapped. 314 if (Kind == ARM::fixup_t2_ldst_pcrel_12) { 315 uint64_t swapped = (Value & 0xFFFF0000) >> 16; 316 swapped |= (Value & 0x0000FFFF) << 16; 317 return swapped; 318 } 319 320 return Value; 321 } 322 case ARM::fixup_thumb_adr_pcrel_10: 323 return ((Value - 4) >> 2) & 0xff; 324 case ARM::fixup_arm_adr_pcrel_12: { 325 // ARM PC-relative values are offset by 8. 326 Value -= 8; 327 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 328 if ((int64_t)Value < 0) { 329 Value = -Value; 330 opc = 2; // 0b0010 331 } 332 if (Ctx && ARM_AM::getSOImmVal(Value) == -1) 333 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value"); 334 // Encode the immediate and shift the opcode into place. 335 return ARM_AM::getSOImmVal(Value) | (opc << 21); 336 } 337 338 case ARM::fixup_t2_adr_pcrel_12: { 339 Value -= 4; 340 unsigned opc = 0; 341 if ((int64_t)Value < 0) { 342 Value = -Value; 343 opc = 5; 344 } 345 346 uint32_t out = (opc << 21); 347 out |= (Value & 0x800) << 15; 348 out |= (Value & 0x700) << 4; 349 out |= (Value & 0x0FF); 350 351 uint64_t swapped = (out & 0xFFFF0000) >> 16; 352 swapped |= (out & 0x0000FFFF) << 16; 353 return swapped; 354 } 355 356 case ARM::fixup_arm_condbranch: 357 case ARM::fixup_arm_uncondbranch: 358 case ARM::fixup_arm_uncondbl: 359 case ARM::fixup_arm_condbl: 360 case ARM::fixup_arm_blx: 361 // These values don't encode the low two bits since they're always zero. 362 // Offset by 8 just as above. 363 return 0xffffff & ((Value - 8) >> 2); 364 case ARM::fixup_t2_uncondbranch: { 365 Value = Value - 4; 366 Value >>= 1; // Low bit is not encoded. 367 368 uint32_t out = 0; 369 bool I = Value & 0x800000; 370 bool J1 = Value & 0x400000; 371 bool J2 = Value & 0x200000; 372 J1 ^= I; 373 J2 ^= I; 374 375 out |= I << 26; // S bit 376 out |= !J1 << 13; // J1 bit 377 out |= !J2 << 11; // J2 bit 378 out |= (Value & 0x1FF800) << 5; // imm6 field 379 out |= (Value & 0x0007FF); // imm11 field 380 381 uint64_t swapped = (out & 0xFFFF0000) >> 16; 382 swapped |= (out & 0x0000FFFF) << 16; 383 return swapped; 384 } 385 case ARM::fixup_t2_condbranch: { 386 Value = Value - 4; 387 Value >>= 1; // Low bit is not encoded. 388 389 uint64_t out = 0; 390 out |= (Value & 0x80000) << 7; // S bit 391 out |= (Value & 0x40000) >> 7; // J2 bit 392 out |= (Value & 0x20000) >> 4; // J1 bit 393 out |= (Value & 0x1F800) << 5; // imm6 field 394 out |= (Value & 0x007FF); // imm11 field 395 396 uint32_t swapped = (out & 0xFFFF0000) >> 16; 397 swapped |= (out & 0x0000FFFF) << 16; 398 return swapped; 399 } 400 case ARM::fixup_arm_thumb_bl: { 401 // The value doesn't encode the low bit (always zero) and is offset by 402 // four. The 32-bit immediate value is encoded as 403 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0) 404 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S). 405 // The value is encoded into disjoint bit positions in the destination 406 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit, 407 // J = either J1 or J2 bit 408 // 409 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII 410 // 411 // Note that the halfwords are stored high first, low second; so we need 412 // to transpose the fixup value here to map properly. 413 uint32_t offset = (Value - 4) >> 1; 414 uint32_t signBit = (offset & 0x800000) >> 23; 415 uint32_t I1Bit = (offset & 0x400000) >> 22; 416 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit; 417 uint32_t I2Bit = (offset & 0x200000) >> 21; 418 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit; 419 uint32_t imm10Bits = (offset & 0x1FF800) >> 11; 420 uint32_t imm11Bits = (offset & 0x000007FF); 421 422 uint32_t Binary = 0; 423 uint32_t firstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits); 424 uint32_t secondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) | 425 (uint16_t)imm11Bits); 426 Binary |= secondHalf << 16; 427 Binary |= firstHalf; 428 return Binary; 429 430 } 431 case ARM::fixup_arm_thumb_blx: { 432 // The value doesn't encode the low two bits (always zero) and is offset by 433 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as 434 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00) 435 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S). 436 // The value is encoded into disjoint bit positions in the destination 437 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit, 438 // J = either J1 or J2 bit, 0 = zero. 439 // 440 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0 441 // 442 // Note that the halfwords are stored high first, low second; so we need 443 // to transpose the fixup value here to map properly. 444 uint32_t offset = (Value - 2) >> 2; 445 uint32_t signBit = (offset & 0x400000) >> 22; 446 uint32_t I1Bit = (offset & 0x200000) >> 21; 447 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit; 448 uint32_t I2Bit = (offset & 0x100000) >> 20; 449 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit; 450 uint32_t imm10HBits = (offset & 0xFFC00) >> 10; 451 uint32_t imm10LBits = (offset & 0x3FF); 452 453 uint32_t Binary = 0; 454 uint32_t firstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits); 455 uint32_t secondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) | 456 ((uint16_t)imm10LBits) << 1); 457 Binary |= secondHalf << 16; 458 Binary |= firstHalf; 459 return Binary; 460 } 461 case ARM::fixup_arm_thumb_cp: 462 // Offset by 4, and don't encode the low two bits. Two bytes of that 463 // 'off by 4' is implicitly handled by the half-word ordering of the 464 // Thumb encoding, so we only need to adjust by 2 here. 465 return ((Value - 2) >> 2) & 0xff; 466 case ARM::fixup_arm_thumb_cb: { 467 // Offset by 4 and don't encode the lower bit, which is always 0. 468 uint32_t Binary = (Value - 4) >> 1; 469 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3); 470 } 471 case ARM::fixup_arm_thumb_br: 472 // Offset by 4 and don't encode the lower bit, which is always 0. 473 return ((Value - 4) >> 1) & 0x7ff; 474 case ARM::fixup_arm_thumb_bcc: 475 // Offset by 4 and don't encode the lower bit, which is always 0. 476 return ((Value - 4) >> 1) & 0xff; 477 case ARM::fixup_arm_pcrel_10_unscaled: { 478 Value = Value - 8; // ARM fixups offset by an additional word and don't 479 // need to adjust for the half-word ordering. 480 bool isAdd = true; 481 if ((int64_t)Value < 0) { 482 Value = -Value; 483 isAdd = false; 484 } 485 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8]. 486 if (Ctx && Value >= 256) 487 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value"); 488 Value = (Value & 0xf) | ((Value & 0xf0) << 4); 489 return Value | (isAdd << 23); 490 } 491 case ARM::fixup_arm_pcrel_10: 492 Value = Value - 4; // ARM fixups offset by an additional word and don't 493 // need to adjust for the half-word ordering. 494 // Fall through. 495 case ARM::fixup_t2_pcrel_10: { 496 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 497 Value = Value - 4; 498 bool isAdd = true; 499 if ((int64_t)Value < 0) { 500 Value = -Value; 501 isAdd = false; 502 } 503 // These values don't encode the low two bits since they're always zero. 504 Value >>= 2; 505 if (Ctx && Value >= 256) 506 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value"); 507 Value |= isAdd << 23; 508 509 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords 510 // swapped. 511 if (Kind == ARM::fixup_t2_pcrel_10) { 512 uint32_t swapped = (Value & 0xFFFF0000) >> 16; 513 swapped |= (Value & 0x0000FFFF) << 16; 514 return swapped; 515 } 516 517 return Value; 518 } 519 } 520 } 521 522 void ARMAsmBackend::processFixupValue(const MCAssembler &Asm, 523 const MCAsmLayout &Layout, 524 const MCFixup &Fixup, 525 const MCFragment *DF, 526 MCValue &Target, uint64_t &Value, 527 bool &IsResolved) { 528 const MCSymbolRefExpr *A = Target.getSymA(); 529 // Some fixups to thumb function symbols need the low bit (thumb bit) 530 // twiddled. 531 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 && 532 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 && 533 (unsigned)Fixup.getKind() != ARM::fixup_arm_adr_pcrel_12 && 534 (unsigned)Fixup.getKind() != ARM::fixup_thumb_adr_pcrel_10 && 535 (unsigned)Fixup.getKind() != ARM::fixup_t2_adr_pcrel_12 && 536 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) { 537 if (A) { 538 const MCSymbol &Sym = A->getSymbol().AliasedSymbol(); 539 if (Asm.isThumbFunc(&Sym)) 540 Value |= 1; 541 } 542 } 543 // We must always generate a relocation for BL/BLX instructions if we have 544 // a symbol to reference, as the linker relies on knowing the destination 545 // symbol's thumb-ness to get interworking right. 546 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx || 547 (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl || 548 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx || 549 (unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl || 550 (unsigned)Fixup.getKind() == ARM::fixup_arm_condbl)) 551 IsResolved = false; 552 553 // Try to get the encoded value for the fixup as-if we're mapping it into 554 // the instruction. This allows adjustFixupValue() to issue a diagnostic 555 // if the value aren't invalid. 556 (void)adjustFixupValue(Fixup, Value, &Asm.getContext()); 557 } 558 559 /// getFixupKindNumBytes - The number of bytes the fixup may change. 560 static unsigned getFixupKindNumBytes(unsigned Kind) { 561 switch (Kind) { 562 default: 563 llvm_unreachable("Unknown fixup kind!"); 564 565 case FK_Data_1: 566 case ARM::fixup_arm_thumb_bcc: 567 case ARM::fixup_arm_thumb_cp: 568 case ARM::fixup_thumb_adr_pcrel_10: 569 return 1; 570 571 case FK_Data_2: 572 case ARM::fixup_arm_thumb_br: 573 case ARM::fixup_arm_thumb_cb: 574 return 2; 575 576 case ARM::fixup_arm_pcrel_10_unscaled: 577 case ARM::fixup_arm_ldst_pcrel_12: 578 case ARM::fixup_arm_pcrel_10: 579 case ARM::fixup_arm_adr_pcrel_12: 580 case ARM::fixup_arm_uncondbl: 581 case ARM::fixup_arm_condbl: 582 case ARM::fixup_arm_blx: 583 case ARM::fixup_arm_condbranch: 584 case ARM::fixup_arm_uncondbranch: 585 return 3; 586 587 case FK_Data_4: 588 case ARM::fixup_t2_ldst_pcrel_12: 589 case ARM::fixup_t2_condbranch: 590 case ARM::fixup_t2_uncondbranch: 591 case ARM::fixup_t2_pcrel_10: 592 case ARM::fixup_t2_adr_pcrel_12: 593 case ARM::fixup_arm_thumb_bl: 594 case ARM::fixup_arm_thumb_blx: 595 case ARM::fixup_arm_movt_hi16: 596 case ARM::fixup_arm_movw_lo16: 597 case ARM::fixup_arm_movt_hi16_pcrel: 598 case ARM::fixup_arm_movw_lo16_pcrel: 599 case ARM::fixup_t2_movt_hi16: 600 case ARM::fixup_t2_movw_lo16: 601 case ARM::fixup_t2_movt_hi16_pcrel: 602 case ARM::fixup_t2_movw_lo16_pcrel: 603 return 4; 604 } 605 } 606 607 void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 608 unsigned DataSize, uint64_t Value) const { 609 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 610 Value = adjustFixupValue(Fixup, Value); 611 if (!Value) return; // Doesn't change encoding. 612 613 unsigned Offset = Fixup.getOffset(); 614 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!"); 615 616 // For each byte of the fragment that the fixup touches, mask in the bits from 617 // the fixup value. The Value has been "split up" into the appropriate 618 // bitfields above. 619 for (unsigned i = 0; i != NumBytes; ++i) 620 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 621 } 622 623 namespace { 624 625 // FIXME: This should be in a separate file. 626 // ELF is an ELF of course... 627 class ELFARMAsmBackend : public ARMAsmBackend { 628 public: 629 uint8_t OSABI; 630 ELFARMAsmBackend(const Target &T, const StringRef TT, 631 uint8_t _OSABI) 632 : ARMAsmBackend(T, TT), OSABI(_OSABI) { } 633 634 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 635 return createARMELFObjectWriter(OS, OSABI); 636 } 637 }; 638 639 // FIXME: This should be in a separate file. 640 class DarwinARMAsmBackend : public ARMAsmBackend { 641 public: 642 const object::mach::CPUSubtypeARM Subtype; 643 DarwinARMAsmBackend(const Target &T, const StringRef TT, 644 object::mach::CPUSubtypeARM st) 645 : ARMAsmBackend(T, TT), Subtype(st) { 646 HasDataInCodeSupport = true; 647 } 648 649 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 650 return createARMMachObjectWriter(OS, /*Is64Bit=*/false, 651 object::mach::CTM_ARM, 652 Subtype); 653 } 654 655 virtual bool doesSectionRequireSymbols(const MCSection &Section) const { 656 return false; 657 } 658 }; 659 660 } // end anonymous namespace 661 662 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, StringRef TT, StringRef CPU) { 663 Triple TheTriple(TT); 664 665 if (TheTriple.isOSDarwin()) { 666 if (TheTriple.getArchName() == "armv4t" || 667 TheTriple.getArchName() == "thumbv4t") 668 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V4T); 669 else if (TheTriple.getArchName() == "armv5e" || 670 TheTriple.getArchName() == "thumbv5e") 671 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V5TEJ); 672 else if (TheTriple.getArchName() == "armv6" || 673 TheTriple.getArchName() == "thumbv6") 674 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V6); 675 else if (TheTriple.getArchName() == "armv7f" || 676 TheTriple.getArchName() == "thumbv7f") 677 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7F); 678 else if (TheTriple.getArchName() == "armv7k" || 679 TheTriple.getArchName() == "thumbv7k") 680 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7K); 681 else if (TheTriple.getArchName() == "armv7s" || 682 TheTriple.getArchName() == "thumbv7s") 683 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7S); 684 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7); 685 } 686 687 if (TheTriple.isOSWindows()) 688 assert(0 && "Windows not supported on ARM"); 689 690 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS()); 691 return new ELFARMAsmBackend(T, TT, OSABI); 692 } 693