1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/ARMAsmBackend.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "MCTargetDesc/ARMAsmBackendDarwin.h" 13 #include "MCTargetDesc/ARMAsmBackendELF.h" 14 #include "MCTargetDesc/ARMAsmBackendWinCOFF.h" 15 #include "MCTargetDesc/ARMBaseInfo.h" 16 #include "MCTargetDesc/ARMFixupKinds.h" 17 #include "MCTargetDesc/ARMMCTargetDesc.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/BinaryFormat/ELF.h" 20 #include "llvm/BinaryFormat/MachO.h" 21 #include "llvm/MC/MCAsmBackend.h" 22 #include "llvm/MC/MCAssembler.h" 23 #include "llvm/MC/MCContext.h" 24 #include "llvm/MC/MCDirectives.h" 25 #include "llvm/MC/MCELFObjectWriter.h" 26 #include "llvm/MC/MCExpr.h" 27 #include "llvm/MC/MCFixupKindInfo.h" 28 #include "llvm/MC/MCMachObjectWriter.h" 29 #include "llvm/MC/MCObjectWriter.h" 30 #include "llvm/MC/MCRegisterInfo.h" 31 #include "llvm/MC/MCSectionELF.h" 32 #include "llvm/MC/MCSectionMachO.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/MCValue.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/ErrorHandling.h" 37 #include "llvm/Support/Format.h" 38 #include "llvm/Support/TargetParser.h" 39 #include "llvm/Support/raw_ostream.h" 40 using namespace llvm; 41 42 namespace { 43 class ARMELFObjectWriter : public MCELFObjectTargetWriter { 44 public: 45 ARMELFObjectWriter(uint8_t OSABI) 46 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM, 47 /*HasRelocationAddend*/ false) {} 48 }; 49 } // end anonymous namespace 50 51 const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { 52 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = { 53 // This table *must* be in the order that the fixup_* kinds are defined in 54 // ARMFixupKinds.h. 55 // 56 // Name Offset (bits) Size (bits) Flags 57 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 58 {"fixup_t2_ldst_pcrel_12", 0, 32, 59 MCFixupKindInfo::FKF_IsPCRel | 60 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 61 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 62 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 63 {"fixup_t2_pcrel_10", 0, 32, 64 MCFixupKindInfo::FKF_IsPCRel | 65 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 66 {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 67 {"fixup_t2_pcrel_9", 0, 32, 68 MCFixupKindInfo::FKF_IsPCRel | 69 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 70 {"fixup_thumb_adr_pcrel_10", 0, 8, 71 MCFixupKindInfo::FKF_IsPCRel | 72 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 73 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 74 {"fixup_t2_adr_pcrel_12", 0, 32, 75 MCFixupKindInfo::FKF_IsPCRel | 76 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 77 {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 78 {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 79 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 80 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 81 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 82 {"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 83 {"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 84 {"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 85 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 86 {"fixup_arm_thumb_blx", 0, 32, 87 MCFixupKindInfo::FKF_IsPCRel | 88 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 89 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 90 {"fixup_arm_thumb_cp", 0, 8, 91 MCFixupKindInfo::FKF_IsPCRel | 92 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 93 {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel}, 94 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 95 // - 19. 96 {"fixup_arm_movt_hi16", 0, 20, 0}, 97 {"fixup_arm_movw_lo16", 0, 20, 0}, 98 {"fixup_t2_movt_hi16", 0, 20, 0}, 99 {"fixup_t2_movw_lo16", 0, 20, 0}, 100 {"fixup_arm_mod_imm", 0, 12, 0}, 101 {"fixup_t2_so_imm", 0, 26, 0}, 102 }; 103 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = { 104 // This table *must* be in the order that the fixup_* kinds are defined in 105 // ARMFixupKinds.h. 106 // 107 // Name Offset (bits) Size (bits) Flags 108 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 109 {"fixup_t2_ldst_pcrel_12", 0, 32, 110 MCFixupKindInfo::FKF_IsPCRel | 111 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 112 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 113 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 114 {"fixup_t2_pcrel_10", 0, 32, 115 MCFixupKindInfo::FKF_IsPCRel | 116 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 117 {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 118 {"fixup_t2_pcrel_9", 0, 32, 119 MCFixupKindInfo::FKF_IsPCRel | 120 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 121 {"fixup_thumb_adr_pcrel_10", 8, 8, 122 MCFixupKindInfo::FKF_IsPCRel | 123 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 124 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 125 {"fixup_t2_adr_pcrel_12", 0, 32, 126 MCFixupKindInfo::FKF_IsPCRel | 127 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 128 {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 129 {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 130 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 131 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 132 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 133 {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 134 {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 135 {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 136 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 137 {"fixup_arm_thumb_blx", 0, 32, 138 MCFixupKindInfo::FKF_IsPCRel | 139 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 140 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 141 {"fixup_arm_thumb_cp", 8, 8, 142 MCFixupKindInfo::FKF_IsPCRel | 143 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 144 {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel}, 145 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 146 // - 19. 147 {"fixup_arm_movt_hi16", 12, 20, 0}, 148 {"fixup_arm_movw_lo16", 12, 20, 0}, 149 {"fixup_t2_movt_hi16", 12, 20, 0}, 150 {"fixup_t2_movw_lo16", 12, 20, 0}, 151 {"fixup_arm_mod_imm", 20, 12, 0}, 152 {"fixup_t2_so_imm", 26, 6, 0}, 153 }; 154 155 if (Kind < FirstTargetFixupKind) 156 return MCAsmBackend::getFixupKindInfo(Kind); 157 158 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 159 "Invalid kind!"); 160 return (IsLittleEndian ? InfosLE : InfosBE)[Kind - FirstTargetFixupKind]; 161 } 162 163 void ARMAsmBackend::handleAssemblerFlag(MCAssemblerFlag Flag) { 164 switch (Flag) { 165 default: 166 break; 167 case MCAF_Code16: 168 setIsThumb(true); 169 break; 170 case MCAF_Code32: 171 setIsThumb(false); 172 break; 173 } 174 } 175 176 unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op) const { 177 bool HasThumb2 = STI->getFeatureBits()[ARM::FeatureThumb2]; 178 bool HasV8MBaselineOps = STI->getFeatureBits()[ARM::HasV8MBaselineOps]; 179 180 switch (Op) { 181 default: 182 return Op; 183 case ARM::tBcc: 184 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op; 185 case ARM::tLDRpci: 186 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op; 187 case ARM::tADR: 188 return HasThumb2 ? (unsigned)ARM::t2ADR : Op; 189 case ARM::tB: 190 return HasV8MBaselineOps ? (unsigned)ARM::t2B : Op; 191 case ARM::tCBZ: 192 return ARM::tHINT; 193 case ARM::tCBNZ: 194 return ARM::tHINT; 195 } 196 } 197 198 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 199 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode()) 200 return true; 201 return false; 202 } 203 204 const char *ARMAsmBackend::reasonForFixupRelaxation(const MCFixup &Fixup, 205 uint64_t Value) const { 206 switch ((unsigned)Fixup.getKind()) { 207 case ARM::fixup_arm_thumb_br: { 208 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the 209 // low bit being an implied zero. There's an implied +4 offset for the 210 // branch, so we adjust the other way here to determine what's 211 // encodable. 212 // 213 // Relax if the value is too big for a (signed) i8. 214 int64_t Offset = int64_t(Value) - 4; 215 if (Offset > 2046 || Offset < -2048) 216 return "out of range pc-relative fixup value"; 217 break; 218 } 219 case ARM::fixup_arm_thumb_bcc: { 220 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the 221 // low bit being an implied zero. There's an implied +4 offset for the 222 // branch, so we adjust the other way here to determine what's 223 // encodable. 224 // 225 // Relax if the value is too big for a (signed) i8. 226 int64_t Offset = int64_t(Value) - 4; 227 if (Offset > 254 || Offset < -256) 228 return "out of range pc-relative fixup value"; 229 break; 230 } 231 case ARM::fixup_thumb_adr_pcrel_10: 232 case ARM::fixup_arm_thumb_cp: { 233 // If the immediate is negative, greater than 1020, or not a multiple 234 // of four, the wide version of the instruction must be used. 235 int64_t Offset = int64_t(Value) - 4; 236 if (Offset & 3) 237 return "misaligned pc-relative fixup value"; 238 else if (Offset > 1020 || Offset < 0) 239 return "out of range pc-relative fixup value"; 240 break; 241 } 242 case ARM::fixup_arm_thumb_cb: { 243 // If we have a Thumb CBZ or CBNZ instruction and its target is the next 244 // instruction it is is actually out of range for the instruction. 245 // It will be changed to a NOP. 246 int64_t Offset = (Value & ~1); 247 if (Offset == 2) 248 return "will be converted to nop"; 249 break; 250 } 251 default: 252 llvm_unreachable("Unexpected fixup kind in reasonForFixupRelaxation()!"); 253 } 254 return nullptr; 255 } 256 257 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, 258 const MCRelaxableFragment *DF, 259 const MCAsmLayout &Layout) const { 260 return reasonForFixupRelaxation(Fixup, Value); 261 } 262 263 void ARMAsmBackend::relaxInstruction(const MCInst &Inst, 264 const MCSubtargetInfo &STI, 265 MCInst &Res) const { 266 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode()); 267 268 // Sanity check w/ diagnostic if we get here w/ a bogus instruction. 269 if (RelaxedOp == Inst.getOpcode()) { 270 SmallString<256> Tmp; 271 raw_svector_ostream OS(Tmp); 272 Inst.dump_pretty(OS); 273 OS << "\n"; 274 report_fatal_error("unexpected instruction to relax: " + OS.str()); 275 } 276 277 // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we 278 // have to change the operands too. 279 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) && 280 RelaxedOp == ARM::tHINT) { 281 Res.setOpcode(RelaxedOp); 282 Res.addOperand(MCOperand::createImm(0)); 283 Res.addOperand(MCOperand::createImm(14)); 284 Res.addOperand(MCOperand::createReg(0)); 285 return; 286 } 287 288 // The rest of instructions we're relaxing have the same operands. 289 // We just need to update to the proper opcode. 290 Res = Inst; 291 Res.setOpcode(RelaxedOp); 292 } 293 294 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 295 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8 296 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP 297 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0 298 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP 299 if (isThumb()) { 300 const uint16_t nopEncoding = 301 hasNOP() ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding; 302 uint64_t NumNops = Count / 2; 303 for (uint64_t i = 0; i != NumNops; ++i) 304 OW->write16(nopEncoding); 305 if (Count & 1) 306 OW->write8(0); 307 return true; 308 } 309 // ARM mode 310 const uint32_t nopEncoding = 311 hasNOP() ? ARMv6T2_NopEncoding : ARMv4_NopEncoding; 312 uint64_t NumNops = Count / 4; 313 for (uint64_t i = 0; i != NumNops; ++i) 314 OW->write32(nopEncoding); 315 // FIXME: should this function return false when unable to write exactly 316 // 'Count' bytes with NOP encodings? 317 switch (Count % 4) { 318 default: 319 break; // No leftover bytes to write 320 case 1: 321 OW->write8(0); 322 break; 323 case 2: 324 OW->write16(0); 325 break; 326 case 3: 327 OW->write16(0); 328 OW->write8(0xa0); 329 break; 330 } 331 332 return true; 333 } 334 335 static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) { 336 if (IsLittleEndian) { 337 // Note that the halfwords are stored high first and low second in thumb; 338 // so we need to swap the fixup value here to map properly. 339 uint32_t Swapped = (Value & 0xFFFF0000) >> 16; 340 Swapped |= (Value & 0x0000FFFF) << 16; 341 return Swapped; 342 } else 343 return Value; 344 } 345 346 static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf, 347 bool IsLittleEndian) { 348 uint32_t Value; 349 350 if (IsLittleEndian) { 351 Value = (SecondHalf & 0xFFFF) << 16; 352 Value |= (FirstHalf & 0xFFFF); 353 } else { 354 Value = (SecondHalf & 0xFFFF); 355 Value |= (FirstHalf & 0xFFFF) << 16; 356 } 357 358 return Value; 359 } 360 361 unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm, 362 const MCFixup &Fixup, 363 const MCValue &Target, uint64_t Value, 364 bool IsPCRel, MCContext &Ctx, 365 bool IsLittleEndian, 366 bool IsResolved) const { 367 unsigned Kind = Fixup.getKind(); 368 369 // MachO tries to make .o files that look vaguely pre-linked, so for MOVW/MOVT 370 // and .word relocations they put the Thumb bit into the addend if possible. 371 // Other relocation types don't want this bit though (branches couldn't encode 372 // it if it *was* present, and no other relocations exist) and it can 373 // interfere with checking valid expressions. 374 if (const MCSymbolRefExpr *A = Target.getSymA()) { 375 if (A->hasSubsectionsViaSymbols() && Asm.isThumbFunc(&A->getSymbol()) && 376 (Kind == FK_Data_4 || Kind == ARM::fixup_arm_movw_lo16 || 377 Kind == ARM::fixup_arm_movt_hi16 || Kind == ARM::fixup_t2_movw_lo16 || 378 Kind == ARM::fixup_t2_movt_hi16)) 379 Value |= 1; 380 } 381 382 switch (Kind) { 383 default: 384 Ctx.reportError(Fixup.getLoc(), "bad relocation fixup type"); 385 return 0; 386 case FK_Data_1: 387 case FK_Data_2: 388 case FK_Data_4: 389 return Value; 390 case FK_SecRel_2: 391 return Value; 392 case FK_SecRel_4: 393 return Value; 394 case ARM::fixup_arm_movt_hi16: 395 if (!IsPCRel) 396 Value >>= 16; 397 LLVM_FALLTHROUGH; 398 case ARM::fixup_arm_movw_lo16: { 399 unsigned Hi4 = (Value & 0xF000) >> 12; 400 unsigned Lo12 = Value & 0x0FFF; 401 // inst{19-16} = Hi4; 402 // inst{11-0} = Lo12; 403 Value = (Hi4 << 16) | (Lo12); 404 return Value; 405 } 406 case ARM::fixup_t2_movt_hi16: 407 if (!IsPCRel) 408 Value >>= 16; 409 LLVM_FALLTHROUGH; 410 case ARM::fixup_t2_movw_lo16: { 411 unsigned Hi4 = (Value & 0xF000) >> 12; 412 unsigned i = (Value & 0x800) >> 11; 413 unsigned Mid3 = (Value & 0x700) >> 8; 414 unsigned Lo8 = Value & 0x0FF; 415 // inst{19-16} = Hi4; 416 // inst{26} = i; 417 // inst{14-12} = Mid3; 418 // inst{7-0} = Lo8; 419 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8); 420 return swapHalfWords(Value, IsLittleEndian); 421 } 422 case ARM::fixup_arm_ldst_pcrel_12: 423 // ARM PC-relative values are offset by 8. 424 Value -= 4; 425 LLVM_FALLTHROUGH; 426 case ARM::fixup_t2_ldst_pcrel_12: { 427 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 428 Value -= 4; 429 bool isAdd = true; 430 if ((int64_t)Value < 0) { 431 Value = -Value; 432 isAdd = false; 433 } 434 if (Value >= 4096) { 435 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 436 return 0; 437 } 438 Value |= isAdd << 23; 439 440 // Same addressing mode as fixup_arm_pcrel_10, 441 // but with 16-bit halfwords swapped. 442 if (Kind == ARM::fixup_t2_ldst_pcrel_12) 443 return swapHalfWords(Value, IsLittleEndian); 444 445 return Value; 446 } 447 case ARM::fixup_arm_adr_pcrel_12: { 448 // ARM PC-relative values are offset by 8. 449 Value -= 8; 450 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 451 if ((int64_t)Value < 0) { 452 Value = -Value; 453 opc = 2; // 0b0010 454 } 455 if (ARM_AM::getSOImmVal(Value) == -1) { 456 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 457 return 0; 458 } 459 // Encode the immediate and shift the opcode into place. 460 return ARM_AM::getSOImmVal(Value) | (opc << 21); 461 } 462 463 case ARM::fixup_t2_adr_pcrel_12: { 464 Value -= 4; 465 unsigned opc = 0; 466 if ((int64_t)Value < 0) { 467 Value = -Value; 468 opc = 5; 469 } 470 471 uint32_t out = (opc << 21); 472 out |= (Value & 0x800) << 15; 473 out |= (Value & 0x700) << 4; 474 out |= (Value & 0x0FF); 475 476 return swapHalfWords(out, IsLittleEndian); 477 } 478 479 case ARM::fixup_arm_condbranch: 480 case ARM::fixup_arm_uncondbranch: 481 case ARM::fixup_arm_uncondbl: 482 case ARM::fixup_arm_condbl: 483 case ARM::fixup_arm_blx: 484 // These values don't encode the low two bits since they're always zero. 485 // Offset by 8 just as above. 486 if (const MCSymbolRefExpr *SRE = 487 dyn_cast<MCSymbolRefExpr>(Fixup.getValue())) 488 if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL) 489 return 0; 490 return 0xffffff & ((Value - 8) >> 2); 491 case ARM::fixup_t2_uncondbranch: { 492 Value = Value - 4; 493 Value >>= 1; // Low bit is not encoded. 494 495 uint32_t out = 0; 496 bool I = Value & 0x800000; 497 bool J1 = Value & 0x400000; 498 bool J2 = Value & 0x200000; 499 J1 ^= I; 500 J2 ^= I; 501 502 out |= I << 26; // S bit 503 out |= !J1 << 13; // J1 bit 504 out |= !J2 << 11; // J2 bit 505 out |= (Value & 0x1FF800) << 5; // imm6 field 506 out |= (Value & 0x0007FF); // imm11 field 507 508 return swapHalfWords(out, IsLittleEndian); 509 } 510 case ARM::fixup_t2_condbranch: { 511 Value = Value - 4; 512 Value >>= 1; // Low bit is not encoded. 513 514 uint64_t out = 0; 515 out |= (Value & 0x80000) << 7; // S bit 516 out |= (Value & 0x40000) >> 7; // J2 bit 517 out |= (Value & 0x20000) >> 4; // J1 bit 518 out |= (Value & 0x1F800) << 5; // imm6 field 519 out |= (Value & 0x007FF); // imm11 field 520 521 return swapHalfWords(out, IsLittleEndian); 522 } 523 case ARM::fixup_arm_thumb_bl: { 524 // FIXME: We get both thumb1 and thumb2 in here, so we can only check for 525 // the less strict thumb2 value. 526 if (!isInt<26>(Value - 4)) { 527 Ctx.reportError(Fixup.getLoc(), "Relocation out of range"); 528 return 0; 529 } 530 531 // The value doesn't encode the low bit (always zero) and is offset by 532 // four. The 32-bit immediate value is encoded as 533 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0) 534 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S). 535 // The value is encoded into disjoint bit positions in the destination 536 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit, 537 // J = either J1 or J2 bit 538 // 539 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII 540 // 541 // Note that the halfwords are stored high first, low second; so we need 542 // to transpose the fixup value here to map properly. 543 uint32_t offset = (Value - 4) >> 1; 544 uint32_t signBit = (offset & 0x800000) >> 23; 545 uint32_t I1Bit = (offset & 0x400000) >> 22; 546 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit; 547 uint32_t I2Bit = (offset & 0x200000) >> 21; 548 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit; 549 uint32_t imm10Bits = (offset & 0x1FF800) >> 11; 550 uint32_t imm11Bits = (offset & 0x000007FF); 551 552 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits); 553 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) | 554 (uint16_t)imm11Bits); 555 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian); 556 } 557 case ARM::fixup_arm_thumb_blx: { 558 // The value doesn't encode the low two bits (always zero) and is offset by 559 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as 560 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00) 561 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S). 562 // The value is encoded into disjoint bit positions in the destination 563 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit, 564 // J = either J1 or J2 bit, 0 = zero. 565 // 566 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0 567 // 568 // Note that the halfwords are stored high first, low second; so we need 569 // to transpose the fixup value here to map properly. 570 if (Value % 4 != 0) { 571 Ctx.reportError(Fixup.getLoc(), "misaligned ARM call destination"); 572 return 0; 573 } 574 575 uint32_t offset = (Value - 4) >> 2; 576 if (const MCSymbolRefExpr *SRE = 577 dyn_cast<MCSymbolRefExpr>(Fixup.getValue())) 578 if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL) 579 offset = 0; 580 uint32_t signBit = (offset & 0x400000) >> 22; 581 uint32_t I1Bit = (offset & 0x200000) >> 21; 582 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit; 583 uint32_t I2Bit = (offset & 0x100000) >> 20; 584 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit; 585 uint32_t imm10HBits = (offset & 0xFFC00) >> 10; 586 uint32_t imm10LBits = (offset & 0x3FF); 587 588 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits); 589 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) | 590 ((uint16_t)imm10LBits) << 1); 591 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian); 592 } 593 case ARM::fixup_thumb_adr_pcrel_10: 594 case ARM::fixup_arm_thumb_cp: 595 // On CPUs supporting Thumb2, this will be relaxed to an ldr.w, otherwise we 596 // could have an error on our hands. 597 if (!STI->getFeatureBits()[ARM::FeatureThumb2] && IsResolved) { 598 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value); 599 if (FixupDiagnostic) { 600 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic); 601 return 0; 602 } 603 } 604 // Offset by 4, and don't encode the low two bits. 605 return ((Value - 4) >> 2) & 0xff; 606 case ARM::fixup_arm_thumb_cb: { 607 // CB instructions can only branch to offsets in [4, 126] in multiples of 2 608 // so ensure that the raw value LSB is zero and it lies in [2, 130]. 609 // An offset of 2 will be relaxed to a NOP. 610 if ((int64_t)Value < 2 || Value > 0x82 || Value & 1) { 611 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 612 return 0; 613 } 614 // Offset by 4 and don't encode the lower bit, which is always 0. 615 // FIXME: diagnose if no Thumb2 616 uint32_t Binary = (Value - 4) >> 1; 617 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3); 618 } 619 case ARM::fixup_arm_thumb_br: 620 // Offset by 4 and don't encode the lower bit, which is always 0. 621 if (!STI->getFeatureBits()[ARM::FeatureThumb2] && 622 !STI->getFeatureBits()[ARM::HasV8MBaselineOps]) { 623 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value); 624 if (FixupDiagnostic) { 625 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic); 626 return 0; 627 } 628 } 629 return ((Value - 4) >> 1) & 0x7ff; 630 case ARM::fixup_arm_thumb_bcc: 631 // Offset by 4 and don't encode the lower bit, which is always 0. 632 if (!STI->getFeatureBits()[ARM::FeatureThumb2]) { 633 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value); 634 if (FixupDiagnostic) { 635 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic); 636 return 0; 637 } 638 } 639 return ((Value - 4) >> 1) & 0xff; 640 case ARM::fixup_arm_pcrel_10_unscaled: { 641 Value = Value - 8; // ARM fixups offset by an additional word and don't 642 // need to adjust for the half-word ordering. 643 bool isAdd = true; 644 if ((int64_t)Value < 0) { 645 Value = -Value; 646 isAdd = false; 647 } 648 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8]. 649 if (Value >= 256) { 650 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 651 return 0; 652 } 653 Value = (Value & 0xf) | ((Value & 0xf0) << 4); 654 return Value | (isAdd << 23); 655 } 656 case ARM::fixup_arm_pcrel_10: 657 Value = Value - 4; // ARM fixups offset by an additional word and don't 658 // need to adjust for the half-word ordering. 659 LLVM_FALLTHROUGH; 660 case ARM::fixup_t2_pcrel_10: { 661 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 662 Value = Value - 4; 663 bool isAdd = true; 664 if ((int64_t)Value < 0) { 665 Value = -Value; 666 isAdd = false; 667 } 668 // These values don't encode the low two bits since they're always zero. 669 Value >>= 2; 670 if (Value >= 256) { 671 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 672 return 0; 673 } 674 Value |= isAdd << 23; 675 676 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords 677 // swapped. 678 if (Kind == ARM::fixup_t2_pcrel_10) 679 return swapHalfWords(Value, IsLittleEndian); 680 681 return Value; 682 } 683 case ARM::fixup_arm_pcrel_9: 684 Value = Value - 4; // ARM fixups offset by an additional word and don't 685 // need to adjust for the half-word ordering. 686 LLVM_FALLTHROUGH; 687 case ARM::fixup_t2_pcrel_9: { 688 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 689 Value = Value - 4; 690 bool isAdd = true; 691 if ((int64_t)Value < 0) { 692 Value = -Value; 693 isAdd = false; 694 } 695 // These values don't encode the low bit since it's always zero. 696 if (Value & 1) { 697 Ctx.reportError(Fixup.getLoc(), "invalid value for this fixup"); 698 return 0; 699 } 700 Value >>= 1; 701 if (Value >= 256) { 702 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 703 return 0; 704 } 705 Value |= isAdd << 23; 706 707 // Same addressing mode as fixup_arm_pcrel_9, but with 16-bit halfwords 708 // swapped. 709 if (Kind == ARM::fixup_t2_pcrel_9) 710 return swapHalfWords(Value, IsLittleEndian); 711 712 return Value; 713 } 714 case ARM::fixup_arm_mod_imm: 715 Value = ARM_AM::getSOImmVal(Value); 716 if (Value >> 12) { 717 Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value"); 718 return 0; 719 } 720 return Value; 721 case ARM::fixup_t2_so_imm: { 722 Value = ARM_AM::getT2SOImmVal(Value); 723 if ((int64_t)Value < 0) { 724 Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value"); 725 return 0; 726 } 727 // Value will contain a 12-bit value broken up into a 4-bit shift in bits 728 // 11:8 and the 8-bit immediate in 0:7. The instruction has the immediate 729 // in 0:7. The 4-bit shift is split up into i:imm3 where i is placed at bit 730 // 10 of the upper half-word and imm3 is placed at 14:12 of the lower 731 // half-word. 732 uint64_t EncValue = 0; 733 EncValue |= (Value & 0x800) << 15; 734 EncValue |= (Value & 0x700) << 4; 735 EncValue |= (Value & 0xff); 736 return swapHalfWords(EncValue, IsLittleEndian); 737 } 738 } 739 } 740 741 bool ARMAsmBackend::shouldForceRelocation(const MCAssembler &Asm, 742 const MCFixup &Fixup, 743 const MCValue &Target) { 744 const MCSymbolRefExpr *A = Target.getSymA(); 745 const MCSymbol *Sym = A ? &A->getSymbol() : nullptr; 746 const unsigned FixupKind = Fixup.getKind() ; 747 if ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl) { 748 assert(Sym && "How did we resolve this?"); 749 750 // If the symbol is external the linker will handle it. 751 // FIXME: Should we handle it as an optimization? 752 753 // If the symbol is out of range, produce a relocation and hope the 754 // linker can handle it. GNU AS produces an error in this case. 755 if (Sym->isExternal()) 756 return true; 757 } 758 // Create relocations for unconditional branches to function symbols with 759 // different execution mode in ELF binaries. 760 if (Sym && Sym->isELF()) { 761 unsigned Type = dyn_cast<MCSymbolELF>(Sym)->getType(); 762 if ((Type == ELF::STT_FUNC || Type == ELF::STT_GNU_IFUNC)) { 763 if (Asm.isThumbFunc(Sym) && (FixupKind == ARM::fixup_arm_uncondbranch)) 764 return true; 765 if (!Asm.isThumbFunc(Sym) && (FixupKind == ARM::fixup_arm_thumb_br || 766 FixupKind == ARM::fixup_arm_thumb_bl || 767 FixupKind == ARM::fixup_t2_condbranch || 768 FixupKind == ARM::fixup_t2_uncondbranch)) 769 return true; 770 } 771 } 772 // We must always generate a relocation for BL/BLX instructions if we have 773 // a symbol to reference, as the linker relies on knowing the destination 774 // symbol's thumb-ness to get interworking right. 775 if (A && (FixupKind == ARM::fixup_arm_thumb_blx || 776 FixupKind == ARM::fixup_arm_blx || 777 FixupKind == ARM::fixup_arm_uncondbl || 778 FixupKind == ARM::fixup_arm_condbl)) 779 return true; 780 return false; 781 } 782 783 /// getFixupKindNumBytes - The number of bytes the fixup may change. 784 static unsigned getFixupKindNumBytes(unsigned Kind) { 785 switch (Kind) { 786 default: 787 llvm_unreachable("Unknown fixup kind!"); 788 789 case FK_Data_1: 790 case ARM::fixup_arm_thumb_bcc: 791 case ARM::fixup_arm_thumb_cp: 792 case ARM::fixup_thumb_adr_pcrel_10: 793 return 1; 794 795 case FK_Data_2: 796 case ARM::fixup_arm_thumb_br: 797 case ARM::fixup_arm_thumb_cb: 798 case ARM::fixup_arm_mod_imm: 799 return 2; 800 801 case ARM::fixup_arm_pcrel_10_unscaled: 802 case ARM::fixup_arm_ldst_pcrel_12: 803 case ARM::fixup_arm_pcrel_10: 804 case ARM::fixup_arm_pcrel_9: 805 case ARM::fixup_arm_adr_pcrel_12: 806 case ARM::fixup_arm_uncondbl: 807 case ARM::fixup_arm_condbl: 808 case ARM::fixup_arm_blx: 809 case ARM::fixup_arm_condbranch: 810 case ARM::fixup_arm_uncondbranch: 811 return 3; 812 813 case FK_Data_4: 814 case ARM::fixup_t2_ldst_pcrel_12: 815 case ARM::fixup_t2_condbranch: 816 case ARM::fixup_t2_uncondbranch: 817 case ARM::fixup_t2_pcrel_10: 818 case ARM::fixup_t2_pcrel_9: 819 case ARM::fixup_t2_adr_pcrel_12: 820 case ARM::fixup_arm_thumb_bl: 821 case ARM::fixup_arm_thumb_blx: 822 case ARM::fixup_arm_movt_hi16: 823 case ARM::fixup_arm_movw_lo16: 824 case ARM::fixup_t2_movt_hi16: 825 case ARM::fixup_t2_movw_lo16: 826 case ARM::fixup_t2_so_imm: 827 return 4; 828 829 case FK_SecRel_2: 830 return 2; 831 case FK_SecRel_4: 832 return 4; 833 } 834 } 835 836 /// getFixupKindContainerSizeBytes - The number of bytes of the 837 /// container involved in big endian. 838 static unsigned getFixupKindContainerSizeBytes(unsigned Kind) { 839 switch (Kind) { 840 default: 841 llvm_unreachable("Unknown fixup kind!"); 842 843 case FK_Data_1: 844 return 1; 845 case FK_Data_2: 846 return 2; 847 case FK_Data_4: 848 return 4; 849 850 case ARM::fixup_arm_thumb_bcc: 851 case ARM::fixup_arm_thumb_cp: 852 case ARM::fixup_thumb_adr_pcrel_10: 853 case ARM::fixup_arm_thumb_br: 854 case ARM::fixup_arm_thumb_cb: 855 // Instruction size is 2 bytes. 856 return 2; 857 858 case ARM::fixup_arm_pcrel_10_unscaled: 859 case ARM::fixup_arm_ldst_pcrel_12: 860 case ARM::fixup_arm_pcrel_10: 861 case ARM::fixup_arm_adr_pcrel_12: 862 case ARM::fixup_arm_uncondbl: 863 case ARM::fixup_arm_condbl: 864 case ARM::fixup_arm_blx: 865 case ARM::fixup_arm_condbranch: 866 case ARM::fixup_arm_uncondbranch: 867 case ARM::fixup_t2_ldst_pcrel_12: 868 case ARM::fixup_t2_condbranch: 869 case ARM::fixup_t2_uncondbranch: 870 case ARM::fixup_t2_pcrel_10: 871 case ARM::fixup_t2_adr_pcrel_12: 872 case ARM::fixup_arm_thumb_bl: 873 case ARM::fixup_arm_thumb_blx: 874 case ARM::fixup_arm_movt_hi16: 875 case ARM::fixup_arm_movw_lo16: 876 case ARM::fixup_t2_movt_hi16: 877 case ARM::fixup_t2_movw_lo16: 878 case ARM::fixup_arm_mod_imm: 879 case ARM::fixup_t2_so_imm: 880 // Instruction size is 4 bytes. 881 return 4; 882 } 883 } 884 885 void ARMAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 886 const MCValue &Target, 887 MutableArrayRef<char> Data, uint64_t Value, 888 bool IsPCRel) const { 889 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 890 MCContext &Ctx = Asm.getContext(); 891 Value = adjustFixupValue(Asm, Fixup, Target, Value, IsPCRel, Ctx, 892 IsLittleEndian, true); 893 if (!Value) 894 return; // Doesn't change encoding. 895 896 unsigned Offset = Fixup.getOffset(); 897 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!"); 898 899 // Used to point to big endian bytes. 900 unsigned FullSizeBytes; 901 if (!IsLittleEndian) { 902 FullSizeBytes = getFixupKindContainerSizeBytes(Fixup.getKind()); 903 assert((Offset + FullSizeBytes) <= Data.size() && "Invalid fixup size!"); 904 assert(NumBytes <= FullSizeBytes && "Invalid fixup size!"); 905 } 906 907 // For each byte of the fragment that the fixup touches, mask in the bits from 908 // the fixup value. The Value has been "split up" into the appropriate 909 // bitfields above. 910 for (unsigned i = 0; i != NumBytes; ++i) { 911 unsigned Idx = IsLittleEndian ? i : (FullSizeBytes - 1 - i); 912 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff); 913 } 914 } 915 916 namespace CU { 917 918 /// \brief Compact unwind encoding values. 919 enum CompactUnwindEncodings { 920 UNWIND_ARM_MODE_MASK = 0x0F000000, 921 UNWIND_ARM_MODE_FRAME = 0x01000000, 922 UNWIND_ARM_MODE_FRAME_D = 0x02000000, 923 UNWIND_ARM_MODE_DWARF = 0x04000000, 924 925 UNWIND_ARM_FRAME_STACK_ADJUST_MASK = 0x00C00000, 926 927 UNWIND_ARM_FRAME_FIRST_PUSH_R4 = 0x00000001, 928 UNWIND_ARM_FRAME_FIRST_PUSH_R5 = 0x00000002, 929 UNWIND_ARM_FRAME_FIRST_PUSH_R6 = 0x00000004, 930 931 UNWIND_ARM_FRAME_SECOND_PUSH_R8 = 0x00000008, 932 UNWIND_ARM_FRAME_SECOND_PUSH_R9 = 0x00000010, 933 UNWIND_ARM_FRAME_SECOND_PUSH_R10 = 0x00000020, 934 UNWIND_ARM_FRAME_SECOND_PUSH_R11 = 0x00000040, 935 UNWIND_ARM_FRAME_SECOND_PUSH_R12 = 0x00000080, 936 937 UNWIND_ARM_FRAME_D_REG_COUNT_MASK = 0x00000F00, 938 939 UNWIND_ARM_DWARF_SECTION_OFFSET = 0x00FFFFFF 940 }; 941 942 } // end CU namespace 943 944 /// Generate compact unwind encoding for the function based on the CFI 945 /// instructions. If the CFI instructions describe a frame that cannot be 946 /// encoded in compact unwind, the method returns UNWIND_ARM_MODE_DWARF which 947 /// tells the runtime to fallback and unwind using dwarf. 948 uint32_t ARMAsmBackendDarwin::generateCompactUnwindEncoding( 949 ArrayRef<MCCFIInstruction> Instrs) const { 950 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "generateCU()\n"); 951 // Only armv7k uses CFI based unwinding. 952 if (Subtype != MachO::CPU_SUBTYPE_ARM_V7K) 953 return 0; 954 // No .cfi directives means no frame. 955 if (Instrs.empty()) 956 return 0; 957 // Start off assuming CFA is at SP+0. 958 int CFARegister = ARM::SP; 959 int CFARegisterOffset = 0; 960 // Mark savable registers as initially unsaved 961 DenseMap<unsigned, int> RegOffsets; 962 int FloatRegCount = 0; 963 // Process each .cfi directive and build up compact unwind info. 964 for (size_t i = 0, e = Instrs.size(); i != e; ++i) { 965 int Reg; 966 const MCCFIInstruction &Inst = Instrs[i]; 967 switch (Inst.getOperation()) { 968 case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa 969 CFARegisterOffset = -Inst.getOffset(); 970 CFARegister = MRI.getLLVMRegNum(Inst.getRegister(), true); 971 break; 972 case MCCFIInstruction::OpDefCfaOffset: // DW_CFA_def_cfa_offset 973 CFARegisterOffset = -Inst.getOffset(); 974 break; 975 case MCCFIInstruction::OpDefCfaRegister: // DW_CFA_def_cfa_register 976 CFARegister = MRI.getLLVMRegNum(Inst.getRegister(), true); 977 break; 978 case MCCFIInstruction::OpOffset: // DW_CFA_offset 979 Reg = MRI.getLLVMRegNum(Inst.getRegister(), true); 980 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 981 RegOffsets[Reg] = Inst.getOffset(); 982 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 983 RegOffsets[Reg] = Inst.getOffset(); 984 ++FloatRegCount; 985 } else { 986 DEBUG_WITH_TYPE("compact-unwind", 987 llvm::dbgs() << ".cfi_offset on unknown register=" 988 << Inst.getRegister() << "\n"); 989 return CU::UNWIND_ARM_MODE_DWARF; 990 } 991 break; 992 case MCCFIInstruction::OpRelOffset: // DW_CFA_advance_loc 993 // Ignore 994 break; 995 default: 996 // Directive not convertable to compact unwind, bail out. 997 DEBUG_WITH_TYPE("compact-unwind", 998 llvm::dbgs() 999 << "CFI directive not compatiable with comact " 1000 "unwind encoding, opcode=" << Inst.getOperation() 1001 << "\n"); 1002 return CU::UNWIND_ARM_MODE_DWARF; 1003 break; 1004 } 1005 } 1006 1007 // If no frame set up, return no unwind info. 1008 if ((CFARegister == ARM::SP) && (CFARegisterOffset == 0)) 1009 return 0; 1010 1011 // Verify standard frame (lr/r7) was used. 1012 if (CFARegister != ARM::R7) { 1013 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "frame register is " 1014 << CFARegister 1015 << " instead of r7\n"); 1016 return CU::UNWIND_ARM_MODE_DWARF; 1017 } 1018 int StackAdjust = CFARegisterOffset - 8; 1019 if (RegOffsets.lookup(ARM::LR) != (-4 - StackAdjust)) { 1020 DEBUG_WITH_TYPE("compact-unwind", 1021 llvm::dbgs() 1022 << "LR not saved as standard frame, StackAdjust=" 1023 << StackAdjust 1024 << ", CFARegisterOffset=" << CFARegisterOffset 1025 << ", lr save at offset=" << RegOffsets[14] << "\n"); 1026 return CU::UNWIND_ARM_MODE_DWARF; 1027 } 1028 if (RegOffsets.lookup(ARM::R7) != (-8 - StackAdjust)) { 1029 DEBUG_WITH_TYPE("compact-unwind", 1030 llvm::dbgs() << "r7 not saved as standard frame\n"); 1031 return CU::UNWIND_ARM_MODE_DWARF; 1032 } 1033 uint32_t CompactUnwindEncoding = CU::UNWIND_ARM_MODE_FRAME; 1034 1035 // If var-args are used, there may be a stack adjust required. 1036 switch (StackAdjust) { 1037 case 0: 1038 break; 1039 case 4: 1040 CompactUnwindEncoding |= 0x00400000; 1041 break; 1042 case 8: 1043 CompactUnwindEncoding |= 0x00800000; 1044 break; 1045 case 12: 1046 CompactUnwindEncoding |= 0x00C00000; 1047 break; 1048 default: 1049 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() 1050 << ".cfi_def_cfa stack adjust (" 1051 << StackAdjust << ") out of range\n"); 1052 return CU::UNWIND_ARM_MODE_DWARF; 1053 } 1054 1055 // If r6 is saved, it must be right below r7. 1056 static struct { 1057 unsigned Reg; 1058 unsigned Encoding; 1059 } GPRCSRegs[] = {{ARM::R6, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R6}, 1060 {ARM::R5, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R5}, 1061 {ARM::R4, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R4}, 1062 {ARM::R12, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R12}, 1063 {ARM::R11, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R11}, 1064 {ARM::R10, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R10}, 1065 {ARM::R9, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R9}, 1066 {ARM::R8, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R8}}; 1067 1068 int CurOffset = -8 - StackAdjust; 1069 for (auto CSReg : GPRCSRegs) { 1070 auto Offset = RegOffsets.find(CSReg.Reg); 1071 if (Offset == RegOffsets.end()) 1072 continue; 1073 1074 int RegOffset = Offset->second; 1075 if (RegOffset != CurOffset - 4) { 1076 DEBUG_WITH_TYPE("compact-unwind", 1077 llvm::dbgs() << MRI.getName(CSReg.Reg) << " saved at " 1078 << RegOffset << " but only supported at " 1079 << CurOffset << "\n"); 1080 return CU::UNWIND_ARM_MODE_DWARF; 1081 } 1082 CompactUnwindEncoding |= CSReg.Encoding; 1083 CurOffset -= 4; 1084 } 1085 1086 // If no floats saved, we are done. 1087 if (FloatRegCount == 0) 1088 return CompactUnwindEncoding; 1089 1090 // Switch mode to include D register saving. 1091 CompactUnwindEncoding &= ~CU::UNWIND_ARM_MODE_MASK; 1092 CompactUnwindEncoding |= CU::UNWIND_ARM_MODE_FRAME_D; 1093 1094 // FIXME: supporting more than 4 saved D-registers compactly would be trivial, 1095 // but needs coordination with the linker and libunwind. 1096 if (FloatRegCount > 4) { 1097 DEBUG_WITH_TYPE("compact-unwind", 1098 llvm::dbgs() << "unsupported number of D registers saved (" 1099 << FloatRegCount << ")\n"); 1100 return CU::UNWIND_ARM_MODE_DWARF; 1101 } 1102 1103 // Floating point registers must either be saved sequentially, or we defer to 1104 // DWARF. No gaps allowed here so check that each saved d-register is 1105 // precisely where it should be. 1106 static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 }; 1107 for (int Idx = FloatRegCount - 1; Idx >= 0; --Idx) { 1108 auto Offset = RegOffsets.find(FPRCSRegs[Idx]); 1109 if (Offset == RegOffsets.end()) { 1110 DEBUG_WITH_TYPE("compact-unwind", 1111 llvm::dbgs() << FloatRegCount << " D-regs saved, but " 1112 << MRI.getName(FPRCSRegs[Idx]) 1113 << " not saved\n"); 1114 return CU::UNWIND_ARM_MODE_DWARF; 1115 } else if (Offset->second != CurOffset - 8) { 1116 DEBUG_WITH_TYPE("compact-unwind", 1117 llvm::dbgs() << FloatRegCount << " D-regs saved, but " 1118 << MRI.getName(FPRCSRegs[Idx]) 1119 << " saved at " << Offset->second 1120 << ", expected at " << CurOffset - 8 1121 << "\n"); 1122 return CU::UNWIND_ARM_MODE_DWARF; 1123 } 1124 CurOffset -= 8; 1125 } 1126 1127 return CompactUnwindEncoding | ((FloatRegCount - 1) << 8); 1128 } 1129 1130 static MachO::CPUSubTypeARM getMachOSubTypeFromArch(StringRef Arch) { 1131 unsigned AK = ARM::parseArch(Arch); 1132 switch (AK) { 1133 default: 1134 return MachO::CPU_SUBTYPE_ARM_V7; 1135 case ARM::AK_ARMV4T: 1136 return MachO::CPU_SUBTYPE_ARM_V4T; 1137 case ARM::AK_ARMV5T: 1138 case ARM::AK_ARMV5TE: 1139 case ARM::AK_ARMV5TEJ: 1140 return MachO::CPU_SUBTYPE_ARM_V5; 1141 case ARM::AK_ARMV6: 1142 case ARM::AK_ARMV6K: 1143 return MachO::CPU_SUBTYPE_ARM_V6; 1144 case ARM::AK_ARMV7A: 1145 return MachO::CPU_SUBTYPE_ARM_V7; 1146 case ARM::AK_ARMV7S: 1147 return MachO::CPU_SUBTYPE_ARM_V7S; 1148 case ARM::AK_ARMV7K: 1149 return MachO::CPU_SUBTYPE_ARM_V7K; 1150 case ARM::AK_ARMV6M: 1151 return MachO::CPU_SUBTYPE_ARM_V6M; 1152 case ARM::AK_ARMV7M: 1153 return MachO::CPU_SUBTYPE_ARM_V7M; 1154 case ARM::AK_ARMV7EM: 1155 return MachO::CPU_SUBTYPE_ARM_V7EM; 1156 } 1157 } 1158 1159 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, 1160 const MCRegisterInfo &MRI, 1161 const Triple &TheTriple, StringRef CPU, 1162 const MCTargetOptions &Options, 1163 bool isLittle) { 1164 switch (TheTriple.getObjectFormat()) { 1165 default: 1166 llvm_unreachable("unsupported object format"); 1167 case Triple::MachO: { 1168 MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TheTriple.getArchName()); 1169 return new ARMAsmBackendDarwin(T, TheTriple, MRI, CS); 1170 } 1171 case Triple::COFF: 1172 assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported"); 1173 return new ARMAsmBackendWinCOFF(T, TheTriple); 1174 case Triple::ELF: 1175 assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target"); 1176 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); 1177 return new ARMAsmBackendELF(T, TheTriple, OSABI, isLittle); 1178 } 1179 } 1180 1181 MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T, 1182 const MCRegisterInfo &MRI, 1183 const Triple &TT, StringRef CPU, 1184 const MCTargetOptions &Options) { 1185 return createARMAsmBackend(T, MRI, TT, CPU, Options, true); 1186 } 1187 1188 MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T, 1189 const MCRegisterInfo &MRI, 1190 const Triple &TT, StringRef CPU, 1191 const MCTargetOptions &Options) { 1192 return createARMAsmBackend(T, MRI, TT, CPU, Options, false); 1193 } 1194 1195 MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T, 1196 const MCRegisterInfo &MRI, 1197 const Triple &TT, StringRef CPU, 1198 const MCTargetOptions &Options) { 1199 return createARMAsmBackend(T, MRI, TT, CPU, Options, true); 1200 } 1201 1202 MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T, 1203 const MCRegisterInfo &MRI, 1204 const Triple &TT, StringRef CPU, 1205 const MCTargetOptions &Options) { 1206 return createARMAsmBackend(T, MRI, TT, CPU, Options, false); 1207 } 1208