1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "llvm/MC/MCDisassembler.h" 13 #include "MCTargetDesc/ARMAddressingModes.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCInstrDesc.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/LEB128.h" 25 #include "llvm/Support/MemoryObject.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 #include <vector> 29 30 using namespace llvm; 31 32 typedef MCDisassembler::DecodeStatus DecodeStatus; 33 34 namespace { 35 // Handles the condition code status of instructions in IT blocks 36 class ITStatus 37 { 38 public: 39 // Returns the condition code for instruction in IT block 40 unsigned getITCC() { 41 unsigned CC = ARMCC::AL; 42 if (instrInITBlock()) 43 CC = ITStates.back(); 44 return CC; 45 } 46 47 // Advances the IT block state to the next T or E 48 void advanceITState() { 49 ITStates.pop_back(); 50 } 51 52 // Returns true if the current instruction is in an IT block 53 bool instrInITBlock() { 54 return !ITStates.empty(); 55 } 56 57 // Returns true if current instruction is the last instruction in an IT block 58 bool instrLastInITBlock() { 59 return ITStates.size() == 1; 60 } 61 62 // Called when decoding an IT instruction. Sets the IT state for the following 63 // instructions that for the IT block. Firstcond and Mask correspond to the 64 // fields in the IT instruction encoding. 65 void setITState(char Firstcond, char Mask) { 66 // (3 - the number of trailing zeros) is the number of then / else. 67 unsigned CondBit0 = Firstcond & 1; 68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 70 assert(NumTZ <= 3 && "Invalid IT mask!"); 71 // push condition codes onto the stack the correct order for the pops 72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 73 bool T = ((Mask >> Pos) & 1) == CondBit0; 74 if (T) 75 ITStates.push_back(CCBits); 76 else 77 ITStates.push_back(CCBits ^ 1); 78 } 79 ITStates.push_back(CCBits); 80 } 81 82 private: 83 std::vector<unsigned char> ITStates; 84 }; 85 } 86 87 namespace { 88 /// ARMDisassembler - ARM disassembler for all ARM platforms. 89 class ARMDisassembler : public MCDisassembler { 90 public: 91 /// Constructor - Initializes the disassembler. 92 /// 93 ARMDisassembler(const MCSubtargetInfo &STI) : 94 MCDisassembler(STI) { 95 } 96 97 ~ARMDisassembler() { 98 } 99 100 /// getInstruction - See MCDisassembler. 101 DecodeStatus getInstruction(MCInst &instr, 102 uint64_t &size, 103 const MemoryObject ®ion, 104 uint64_t address, 105 raw_ostream &vStream, 106 raw_ostream &cStream) const; 107 }; 108 109 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 110 class ThumbDisassembler : public MCDisassembler { 111 public: 112 /// Constructor - Initializes the disassembler. 113 /// 114 ThumbDisassembler(const MCSubtargetInfo &STI) : 115 MCDisassembler(STI) { 116 } 117 118 ~ThumbDisassembler() { 119 } 120 121 /// getInstruction - See MCDisassembler. 122 DecodeStatus getInstruction(MCInst &instr, 123 uint64_t &size, 124 const MemoryObject ®ion, 125 uint64_t address, 126 raw_ostream &vStream, 127 raw_ostream &cStream) const; 128 129 private: 130 mutable ITStatus ITBlock; 131 DecodeStatus AddThumbPredicate(MCInst&) const; 132 void UpdateThumbVFPPredicate(MCInst&) const; 133 }; 134 } 135 136 static bool Check(DecodeStatus &Out, DecodeStatus In) { 137 switch (In) { 138 case MCDisassembler::Success: 139 // Out stays the same. 140 return true; 141 case MCDisassembler::SoftFail: 142 Out = In; 143 return true; 144 case MCDisassembler::Fail: 145 Out = In; 146 return false; 147 } 148 llvm_unreachable("Invalid DecodeStatus!"); 149 } 150 151 152 // Forward declare these because the autogenerated code will reference them. 153 // Definitions are further down. 154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 157 unsigned RegNo, uint64_t Address, 158 const void *Decoder); 159 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 160 unsigned RegNo, uint64_t Address, 161 const void *Decoder); 162 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 185 unsigned RegNo, uint64_t Address, 186 const void *Decoder); 187 188 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 201 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 206 unsigned Insn, 207 uint64_t Address, 208 const void *Decoder); 209 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 218 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 219 unsigned Insn, 220 uint64_t Adddress, 221 const void *Decoder); 222 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 327 const void *Decoder); 328 329 330 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 349 uint64_t Address, const void *Decoder); 350 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 351 uint64_t Address, const void* Decoder); 352 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 353 uint64_t Address, const void* Decoder); 354 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 355 uint64_t Address, const void* Decoder); 356 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 357 uint64_t Address, const void* Decoder); 358 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 381 uint64_t Address, const void *Decoder); 382 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 383 uint64_t Address, const void *Decoder); 384 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 389 uint64_t Address, const void *Decoder); 390 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 391 uint64_t Address, const void *Decoder); 392 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 393 uint64_t Address, const void *Decoder); 394 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 395 uint64_t Address, const void *Decoder); 396 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 397 uint64_t Address, const void *Decoder); 398 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 399 uint64_t Address, const void *Decoder); 400 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 401 uint64_t Address, const void *Decoder); 402 403 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 404 uint64_t Address, const void *Decoder); 405 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 406 uint64_t Address, const void *Decoder); 407 #include "ARMGenDisassemblerTables.inc" 408 409 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 410 return new ARMDisassembler(STI); 411 } 412 413 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 414 return new ThumbDisassembler(STI); 415 } 416 417 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 418 const MemoryObject &Region, 419 uint64_t Address, 420 raw_ostream &os, 421 raw_ostream &cs) const { 422 CommentStream = &cs; 423 424 uint8_t bytes[4]; 425 426 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 427 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 428 429 // We want to read exactly 4 bytes of data. 430 if (Region.readBytes(Address, 4, bytes) == -1) { 431 Size = 0; 432 return MCDisassembler::Fail; 433 } 434 435 // Encoded as a small-endian 32-bit word in the stream. 436 uint32_t insn = (bytes[3] << 24) | 437 (bytes[2] << 16) | 438 (bytes[1] << 8) | 439 (bytes[0] << 0); 440 441 // Calling the auto-generated decoder function. 442 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 443 Address, this, STI); 444 if (result != MCDisassembler::Fail) { 445 Size = 4; 446 return result; 447 } 448 449 // VFP and NEON instructions, similarly, are shared between ARM 450 // and Thumb modes. 451 MI.clear(); 452 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 453 if (result != MCDisassembler::Fail) { 454 Size = 4; 455 return result; 456 } 457 458 MI.clear(); 459 result = decodeInstruction(DecoderTableVFPV832, MI, insn, Address, this, STI); 460 if (result != MCDisassembler::Fail) { 461 Size = 4; 462 return result; 463 } 464 465 MI.clear(); 466 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 467 this, STI); 468 if (result != MCDisassembler::Fail) { 469 Size = 4; 470 // Add a fake predicate operand, because we share these instruction 471 // definitions with Thumb2 where these instructions are predicable. 472 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 473 return MCDisassembler::Fail; 474 return result; 475 } 476 477 MI.clear(); 478 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 479 this, STI); 480 if (result != MCDisassembler::Fail) { 481 Size = 4; 482 // Add a fake predicate operand, because we share these instruction 483 // definitions with Thumb2 where these instructions are predicable. 484 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 485 return MCDisassembler::Fail; 486 return result; 487 } 488 489 MI.clear(); 490 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 491 this, STI); 492 if (result != MCDisassembler::Fail) { 493 Size = 4; 494 // Add a fake predicate operand, because we share these instruction 495 // definitions with Thumb2 where these instructions are predicable. 496 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 497 return MCDisassembler::Fail; 498 return result; 499 } 500 501 MI.clear(); 502 503 Size = 0; 504 return MCDisassembler::Fail; 505 } 506 507 namespace llvm { 508 extern const MCInstrDesc ARMInsts[]; 509 } 510 511 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 512 /// immediate Value in the MCInst. The immediate Value has had any PC 513 /// adjustment made by the caller. If the instruction is a branch instruction 514 /// then isBranch is true, else false. If the getOpInfo() function was set as 515 /// part of the setupForSymbolicDisassembly() call then that function is called 516 /// to get any symbolic information at the Address for this instruction. If 517 /// that returns non-zero then the symbolic information it returns is used to 518 /// create an MCExpr and that is added as an operand to the MCInst. If 519 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 520 /// Value is done and if a symbol is found an MCExpr is created with that, else 521 /// an MCExpr with Value is created. This function returns true if it adds an 522 /// operand to the MCInst and false otherwise. 523 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 524 bool isBranch, uint64_t InstSize, 525 MCInst &MI, const void *Decoder) { 526 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 527 // FIXME: Does it make sense for value to be negative? 528 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 529 /* Offset */ 0, InstSize); 530 } 531 532 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 533 /// referenced by a load instruction with the base register that is the Pc. 534 /// These can often be values in a literal pool near the Address of the 535 /// instruction. The Address of the instruction and its immediate Value are 536 /// used as a possible literal pool entry. The SymbolLookUp call back will 537 /// return the name of a symbol referenced by the literal pool's entry if 538 /// the referenced address is that of a symbol. Or it will return a pointer to 539 /// a literal 'C' string if the referenced address of the literal pool's entry 540 /// is an address into a section with 'C' string literals. 541 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 542 const void *Decoder) { 543 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 544 Dis->tryAddingPcLoadReferenceComment(Value, Address); 545 } 546 547 // Thumb1 instructions don't have explicit S bits. Rather, they 548 // implicitly set CPSR. Since it's not represented in the encoding, the 549 // auto-generated decoder won't inject the CPSR operand. We need to fix 550 // that as a post-pass. 551 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 552 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 553 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 554 MCInst::iterator I = MI.begin(); 555 for (unsigned i = 0; i < NumOps; ++i, ++I) { 556 if (I == MI.end()) break; 557 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 558 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 559 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 560 return; 561 } 562 } 563 564 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 565 } 566 567 // Most Thumb instructions don't have explicit predicates in the 568 // encoding, but rather get their predicates from IT context. We need 569 // to fix up the predicate operands using this context information as a 570 // post-pass. 571 MCDisassembler::DecodeStatus 572 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 573 MCDisassembler::DecodeStatus S = Success; 574 575 // A few instructions actually have predicates encoded in them. Don't 576 // try to overwrite it if we're seeing one of those. 577 switch (MI.getOpcode()) { 578 case ARM::tBcc: 579 case ARM::t2Bcc: 580 case ARM::tCBZ: 581 case ARM::tCBNZ: 582 case ARM::tCPS: 583 case ARM::t2CPS3p: 584 case ARM::t2CPS2p: 585 case ARM::t2CPS1p: 586 case ARM::tMOVSr: 587 case ARM::tSETEND: 588 // Some instructions (mostly conditional branches) are not 589 // allowed in IT blocks. 590 if (ITBlock.instrInITBlock()) 591 S = SoftFail; 592 else 593 return Success; 594 break; 595 case ARM::tB: 596 case ARM::t2B: 597 case ARM::t2TBB: 598 case ARM::t2TBH: 599 // Some instructions (mostly unconditional branches) can 600 // only appears at the end of, or outside of, an IT. 601 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 602 S = SoftFail; 603 break; 604 default: 605 break; 606 } 607 608 // If we're in an IT block, base the predicate on that. Otherwise, 609 // assume a predicate of AL. 610 unsigned CC; 611 CC = ITBlock.getITCC(); 612 if (CC == 0xF) 613 CC = ARMCC::AL; 614 if (ITBlock.instrInITBlock()) 615 ITBlock.advanceITState(); 616 617 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 618 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 619 MCInst::iterator I = MI.begin(); 620 for (unsigned i = 0; i < NumOps; ++i, ++I) { 621 if (I == MI.end()) break; 622 if (OpInfo[i].isPredicate()) { 623 I = MI.insert(I, MCOperand::CreateImm(CC)); 624 ++I; 625 if (CC == ARMCC::AL) 626 MI.insert(I, MCOperand::CreateReg(0)); 627 else 628 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 629 return S; 630 } 631 } 632 633 I = MI.insert(I, MCOperand::CreateImm(CC)); 634 ++I; 635 if (CC == ARMCC::AL) 636 MI.insert(I, MCOperand::CreateReg(0)); 637 else 638 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 639 640 return S; 641 } 642 643 // Thumb VFP instructions are a special case. Because we share their 644 // encodings between ARM and Thumb modes, and they are predicable in ARM 645 // mode, the auto-generated decoder will give them an (incorrect) 646 // predicate operand. We need to rewrite these operands based on the IT 647 // context as a post-pass. 648 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 649 unsigned CC; 650 CC = ITBlock.getITCC(); 651 if (ITBlock.instrInITBlock()) 652 ITBlock.advanceITState(); 653 654 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 655 MCInst::iterator I = MI.begin(); 656 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 657 for (unsigned i = 0; i < NumOps; ++i, ++I) { 658 if (OpInfo[i].isPredicate() ) { 659 I->setImm(CC); 660 ++I; 661 if (CC == ARMCC::AL) 662 I->setReg(0); 663 else 664 I->setReg(ARM::CPSR); 665 return; 666 } 667 } 668 } 669 670 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 671 const MemoryObject &Region, 672 uint64_t Address, 673 raw_ostream &os, 674 raw_ostream &cs) const { 675 CommentStream = &cs; 676 677 uint8_t bytes[4]; 678 679 assert((STI.getFeatureBits() & ARM::ModeThumb) && 680 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 681 682 // We want to read exactly 2 bytes of data. 683 if (Region.readBytes(Address, 2, bytes) == -1) { 684 Size = 0; 685 return MCDisassembler::Fail; 686 } 687 688 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 689 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 690 Address, this, STI); 691 if (result != MCDisassembler::Fail) { 692 Size = 2; 693 Check(result, AddThumbPredicate(MI)); 694 return result; 695 } 696 697 MI.clear(); 698 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 699 Address, this, STI); 700 if (result) { 701 Size = 2; 702 bool InITBlock = ITBlock.instrInITBlock(); 703 Check(result, AddThumbPredicate(MI)); 704 AddThumb1SBit(MI, InITBlock); 705 return result; 706 } 707 708 MI.clear(); 709 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 710 Address, this, STI); 711 if (result != MCDisassembler::Fail) { 712 Size = 2; 713 714 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 715 // the Thumb predicate. 716 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 717 result = MCDisassembler::SoftFail; 718 719 Check(result, AddThumbPredicate(MI)); 720 721 // If we find an IT instruction, we need to parse its condition 722 // code and mask operands so that we can apply them correctly 723 // to the subsequent instructions. 724 if (MI.getOpcode() == ARM::t2IT) { 725 726 unsigned Firstcond = MI.getOperand(0).getImm(); 727 unsigned Mask = MI.getOperand(1).getImm(); 728 ITBlock.setITState(Firstcond, Mask); 729 } 730 731 return result; 732 } 733 734 // We want to read exactly 4 bytes of data. 735 if (Region.readBytes(Address, 4, bytes) == -1) { 736 Size = 0; 737 return MCDisassembler::Fail; 738 } 739 740 uint32_t insn32 = (bytes[3] << 8) | 741 (bytes[2] << 0) | 742 (bytes[1] << 24) | 743 (bytes[0] << 16); 744 MI.clear(); 745 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 746 this, STI); 747 if (result != MCDisassembler::Fail) { 748 Size = 4; 749 bool InITBlock = ITBlock.instrInITBlock(); 750 Check(result, AddThumbPredicate(MI)); 751 AddThumb1SBit(MI, InITBlock); 752 return result; 753 } 754 755 MI.clear(); 756 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 757 this, STI); 758 if (result != MCDisassembler::Fail) { 759 Size = 4; 760 Check(result, AddThumbPredicate(MI)); 761 return result; 762 } 763 764 if (fieldFromInstruction(insn32, 28, 4) == 0xE) { 765 MI.clear(); 766 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 767 if (result != MCDisassembler::Fail) { 768 Size = 4; 769 UpdateThumbVFPPredicate(MI); 770 return result; 771 } 772 } 773 774 MI.clear(); 775 result = decodeInstruction(DecoderTableVFPV832, MI, insn32, Address, this, STI); 776 if (result != MCDisassembler::Fail) { 777 Size = 4; 778 return result; 779 } 780 781 if (fieldFromInstruction(insn32, 28, 4) == 0xE) { 782 MI.clear(); 783 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 784 this, STI); 785 if (result != MCDisassembler::Fail) { 786 Size = 4; 787 Check(result, AddThumbPredicate(MI)); 788 return result; 789 } 790 } 791 792 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 793 MI.clear(); 794 uint32_t NEONLdStInsn = insn32; 795 NEONLdStInsn &= 0xF0FFFFFF; 796 NEONLdStInsn |= 0x04000000; 797 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 798 Address, this, STI); 799 if (result != MCDisassembler::Fail) { 800 Size = 4; 801 Check(result, AddThumbPredicate(MI)); 802 return result; 803 } 804 } 805 806 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 807 MI.clear(); 808 uint32_t NEONDataInsn = insn32; 809 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 810 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 811 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 812 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 813 Address, this, STI); 814 if (result != MCDisassembler::Fail) { 815 Size = 4; 816 Check(result, AddThumbPredicate(MI)); 817 return result; 818 } 819 } 820 821 Size = 0; 822 return MCDisassembler::Fail; 823 } 824 825 826 extern "C" void LLVMInitializeARMDisassembler() { 827 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 828 createARMDisassembler); 829 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 830 createThumbDisassembler); 831 } 832 833 static const uint16_t GPRDecoderTable[] = { 834 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 835 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 836 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 837 ARM::R12, ARM::SP, ARM::LR, ARM::PC 838 }; 839 840 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 841 uint64_t Address, const void *Decoder) { 842 if (RegNo > 15) 843 return MCDisassembler::Fail; 844 845 unsigned Register = GPRDecoderTable[RegNo]; 846 Inst.addOperand(MCOperand::CreateReg(Register)); 847 return MCDisassembler::Success; 848 } 849 850 static DecodeStatus 851 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 852 uint64_t Address, const void *Decoder) { 853 DecodeStatus S = MCDisassembler::Success; 854 855 if (RegNo == 15) 856 S = MCDisassembler::SoftFail; 857 858 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 859 860 return S; 861 } 862 863 static DecodeStatus 864 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 865 uint64_t Address, const void *Decoder) { 866 DecodeStatus S = MCDisassembler::Success; 867 868 if (RegNo == 15) 869 { 870 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); 871 return MCDisassembler::Success; 872 } 873 874 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 875 return S; 876 } 877 878 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 879 uint64_t Address, const void *Decoder) { 880 if (RegNo > 7) 881 return MCDisassembler::Fail; 882 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 883 } 884 885 static const uint16_t GPRPairDecoderTable[] = { 886 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 887 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 888 }; 889 890 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 891 uint64_t Address, const void *Decoder) { 892 DecodeStatus S = MCDisassembler::Success; 893 894 if (RegNo > 13) 895 return MCDisassembler::Fail; 896 897 if ((RegNo & 1) || RegNo == 0xe) 898 S = MCDisassembler::SoftFail; 899 900 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 901 Inst.addOperand(MCOperand::CreateReg(RegisterPair)); 902 return S; 903 } 904 905 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 906 uint64_t Address, const void *Decoder) { 907 unsigned Register = 0; 908 switch (RegNo) { 909 case 0: 910 Register = ARM::R0; 911 break; 912 case 1: 913 Register = ARM::R1; 914 break; 915 case 2: 916 Register = ARM::R2; 917 break; 918 case 3: 919 Register = ARM::R3; 920 break; 921 case 9: 922 Register = ARM::R9; 923 break; 924 case 12: 925 Register = ARM::R12; 926 break; 927 default: 928 return MCDisassembler::Fail; 929 } 930 931 Inst.addOperand(MCOperand::CreateReg(Register)); 932 return MCDisassembler::Success; 933 } 934 935 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 936 uint64_t Address, const void *Decoder) { 937 DecodeStatus S = MCDisassembler::Success; 938 if (RegNo == 13 || RegNo == 15) 939 S = MCDisassembler::SoftFail; 940 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 941 return S; 942 } 943 944 static const uint16_t SPRDecoderTable[] = { 945 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 946 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 947 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 948 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 949 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 950 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 951 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 952 ARM::S28, ARM::S29, ARM::S30, ARM::S31 953 }; 954 955 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 956 uint64_t Address, const void *Decoder) { 957 if (RegNo > 31) 958 return MCDisassembler::Fail; 959 960 unsigned Register = SPRDecoderTable[RegNo]; 961 Inst.addOperand(MCOperand::CreateReg(Register)); 962 return MCDisassembler::Success; 963 } 964 965 static const uint16_t DPRDecoderTable[] = { 966 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 967 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 968 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 969 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 970 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 971 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 972 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 973 ARM::D28, ARM::D29, ARM::D30, ARM::D31 974 }; 975 976 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 977 uint64_t Address, const void *Decoder) { 978 if (RegNo > 31) 979 return MCDisassembler::Fail; 980 981 unsigned Register = DPRDecoderTable[RegNo]; 982 Inst.addOperand(MCOperand::CreateReg(Register)); 983 return MCDisassembler::Success; 984 } 985 986 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 987 uint64_t Address, const void *Decoder) { 988 if (RegNo > 7) 989 return MCDisassembler::Fail; 990 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 991 } 992 993 static DecodeStatus 994 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 995 uint64_t Address, const void *Decoder) { 996 if (RegNo > 15) 997 return MCDisassembler::Fail; 998 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 999 } 1000 1001 static const uint16_t QPRDecoderTable[] = { 1002 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1003 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1004 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1005 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1006 }; 1007 1008 1009 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1010 uint64_t Address, const void *Decoder) { 1011 if (RegNo > 31 || (RegNo & 1) != 0) 1012 return MCDisassembler::Fail; 1013 RegNo >>= 1; 1014 1015 unsigned Register = QPRDecoderTable[RegNo]; 1016 Inst.addOperand(MCOperand::CreateReg(Register)); 1017 return MCDisassembler::Success; 1018 } 1019 1020 static const uint16_t DPairDecoderTable[] = { 1021 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1022 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1023 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1024 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1025 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1026 ARM::Q15 1027 }; 1028 1029 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1030 uint64_t Address, const void *Decoder) { 1031 if (RegNo > 30) 1032 return MCDisassembler::Fail; 1033 1034 unsigned Register = DPairDecoderTable[RegNo]; 1035 Inst.addOperand(MCOperand::CreateReg(Register)); 1036 return MCDisassembler::Success; 1037 } 1038 1039 static const uint16_t DPairSpacedDecoderTable[] = { 1040 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1041 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1042 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1043 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1044 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1045 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1046 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1047 ARM::D28_D30, ARM::D29_D31 1048 }; 1049 1050 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1051 unsigned RegNo, 1052 uint64_t Address, 1053 const void *Decoder) { 1054 if (RegNo > 29) 1055 return MCDisassembler::Fail; 1056 1057 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1058 Inst.addOperand(MCOperand::CreateReg(Register)); 1059 return MCDisassembler::Success; 1060 } 1061 1062 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1063 uint64_t Address, const void *Decoder) { 1064 if (Val == 0xF) return MCDisassembler::Fail; 1065 // AL predicate is not allowed on Thumb1 branches. 1066 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1067 return MCDisassembler::Fail; 1068 Inst.addOperand(MCOperand::CreateImm(Val)); 1069 if (Val == ARMCC::AL) { 1070 Inst.addOperand(MCOperand::CreateReg(0)); 1071 } else 1072 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1073 return MCDisassembler::Success; 1074 } 1075 1076 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1077 uint64_t Address, const void *Decoder) { 1078 if (Val) 1079 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1080 else 1081 Inst.addOperand(MCOperand::CreateReg(0)); 1082 return MCDisassembler::Success; 1083 } 1084 1085 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1086 uint64_t Address, const void *Decoder) { 1087 uint32_t imm = Val & 0xFF; 1088 uint32_t rot = (Val & 0xF00) >> 7; 1089 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1090 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1091 return MCDisassembler::Success; 1092 } 1093 1094 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1095 uint64_t Address, const void *Decoder) { 1096 DecodeStatus S = MCDisassembler::Success; 1097 1098 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1099 unsigned type = fieldFromInstruction(Val, 5, 2); 1100 unsigned imm = fieldFromInstruction(Val, 7, 5); 1101 1102 // Register-immediate 1103 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1104 return MCDisassembler::Fail; 1105 1106 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1107 switch (type) { 1108 case 0: 1109 Shift = ARM_AM::lsl; 1110 break; 1111 case 1: 1112 Shift = ARM_AM::lsr; 1113 break; 1114 case 2: 1115 Shift = ARM_AM::asr; 1116 break; 1117 case 3: 1118 Shift = ARM_AM::ror; 1119 break; 1120 } 1121 1122 if (Shift == ARM_AM::ror && imm == 0) 1123 Shift = ARM_AM::rrx; 1124 1125 unsigned Op = Shift | (imm << 3); 1126 Inst.addOperand(MCOperand::CreateImm(Op)); 1127 1128 return S; 1129 } 1130 1131 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1132 uint64_t Address, const void *Decoder) { 1133 DecodeStatus S = MCDisassembler::Success; 1134 1135 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1136 unsigned type = fieldFromInstruction(Val, 5, 2); 1137 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1138 1139 // Register-register 1140 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1141 return MCDisassembler::Fail; 1142 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1143 return MCDisassembler::Fail; 1144 1145 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1146 switch (type) { 1147 case 0: 1148 Shift = ARM_AM::lsl; 1149 break; 1150 case 1: 1151 Shift = ARM_AM::lsr; 1152 break; 1153 case 2: 1154 Shift = ARM_AM::asr; 1155 break; 1156 case 3: 1157 Shift = ARM_AM::ror; 1158 break; 1159 } 1160 1161 Inst.addOperand(MCOperand::CreateImm(Shift)); 1162 1163 return S; 1164 } 1165 1166 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1167 uint64_t Address, const void *Decoder) { 1168 DecodeStatus S = MCDisassembler::Success; 1169 1170 bool writebackLoad = false; 1171 unsigned writebackReg = 0; 1172 switch (Inst.getOpcode()) { 1173 default: 1174 break; 1175 case ARM::LDMIA_UPD: 1176 case ARM::LDMDB_UPD: 1177 case ARM::LDMIB_UPD: 1178 case ARM::LDMDA_UPD: 1179 case ARM::t2LDMIA_UPD: 1180 case ARM::t2LDMDB_UPD: 1181 writebackLoad = true; 1182 writebackReg = Inst.getOperand(0).getReg(); 1183 break; 1184 } 1185 1186 // Empty register lists are not allowed. 1187 if (Val == 0) return MCDisassembler::Fail; 1188 for (unsigned i = 0; i < 16; ++i) { 1189 if (Val & (1 << i)) { 1190 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1191 return MCDisassembler::Fail; 1192 // Writeback not allowed if Rn is in the target list. 1193 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1194 Check(S, MCDisassembler::SoftFail); 1195 } 1196 } 1197 1198 return S; 1199 } 1200 1201 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1202 uint64_t Address, const void *Decoder) { 1203 DecodeStatus S = MCDisassembler::Success; 1204 1205 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1206 unsigned regs = fieldFromInstruction(Val, 0, 8); 1207 1208 // In case of unpredictable encoding, tweak the operands. 1209 if (regs == 0 || (Vd + regs) > 32) { 1210 regs = Vd + regs > 32 ? 32 - Vd : regs; 1211 regs = std::max( 1u, regs); 1212 S = MCDisassembler::SoftFail; 1213 } 1214 1215 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1216 return MCDisassembler::Fail; 1217 for (unsigned i = 0; i < (regs - 1); ++i) { 1218 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1219 return MCDisassembler::Fail; 1220 } 1221 1222 return S; 1223 } 1224 1225 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1226 uint64_t Address, const void *Decoder) { 1227 DecodeStatus S = MCDisassembler::Success; 1228 1229 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1230 unsigned regs = fieldFromInstruction(Val, 1, 7); 1231 1232 // In case of unpredictable encoding, tweak the operands. 1233 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1234 regs = Vd + regs > 32 ? 32 - Vd : regs; 1235 regs = std::max( 1u, regs); 1236 regs = std::min(16u, regs); 1237 S = MCDisassembler::SoftFail; 1238 } 1239 1240 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1241 return MCDisassembler::Fail; 1242 for (unsigned i = 0; i < (regs - 1); ++i) { 1243 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1244 return MCDisassembler::Fail; 1245 } 1246 1247 return S; 1248 } 1249 1250 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1251 uint64_t Address, const void *Decoder) { 1252 // This operand encodes a mask of contiguous zeros between a specified MSB 1253 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1254 // the mask of all bits LSB-and-lower, and then xor them to create 1255 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1256 // create the final mask. 1257 unsigned msb = fieldFromInstruction(Val, 5, 5); 1258 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1259 1260 DecodeStatus S = MCDisassembler::Success; 1261 if (lsb > msb) { 1262 Check(S, MCDisassembler::SoftFail); 1263 // The check above will cause the warning for the "potentially undefined 1264 // instruction encoding" but we can't build a bad MCOperand value here 1265 // with a lsb > msb or else printing the MCInst will cause a crash. 1266 lsb = msb; 1267 } 1268 1269 uint32_t msb_mask = 0xFFFFFFFF; 1270 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1271 uint32_t lsb_mask = (1U << lsb) - 1; 1272 1273 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1274 return S; 1275 } 1276 1277 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1278 uint64_t Address, const void *Decoder) { 1279 DecodeStatus S = MCDisassembler::Success; 1280 1281 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1282 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1283 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1284 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1285 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1286 unsigned U = fieldFromInstruction(Insn, 23, 1); 1287 1288 switch (Inst.getOpcode()) { 1289 case ARM::LDC_OFFSET: 1290 case ARM::LDC_PRE: 1291 case ARM::LDC_POST: 1292 case ARM::LDC_OPTION: 1293 case ARM::LDCL_OFFSET: 1294 case ARM::LDCL_PRE: 1295 case ARM::LDCL_POST: 1296 case ARM::LDCL_OPTION: 1297 case ARM::STC_OFFSET: 1298 case ARM::STC_PRE: 1299 case ARM::STC_POST: 1300 case ARM::STC_OPTION: 1301 case ARM::STCL_OFFSET: 1302 case ARM::STCL_PRE: 1303 case ARM::STCL_POST: 1304 case ARM::STCL_OPTION: 1305 case ARM::t2LDC_OFFSET: 1306 case ARM::t2LDC_PRE: 1307 case ARM::t2LDC_POST: 1308 case ARM::t2LDC_OPTION: 1309 case ARM::t2LDCL_OFFSET: 1310 case ARM::t2LDCL_PRE: 1311 case ARM::t2LDCL_POST: 1312 case ARM::t2LDCL_OPTION: 1313 case ARM::t2STC_OFFSET: 1314 case ARM::t2STC_PRE: 1315 case ARM::t2STC_POST: 1316 case ARM::t2STC_OPTION: 1317 case ARM::t2STCL_OFFSET: 1318 case ARM::t2STCL_PRE: 1319 case ARM::t2STCL_POST: 1320 case ARM::t2STCL_OPTION: 1321 if (coproc == 0xA || coproc == 0xB) 1322 return MCDisassembler::Fail; 1323 break; 1324 default: 1325 break; 1326 } 1327 1328 Inst.addOperand(MCOperand::CreateImm(coproc)); 1329 Inst.addOperand(MCOperand::CreateImm(CRd)); 1330 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1331 return MCDisassembler::Fail; 1332 1333 switch (Inst.getOpcode()) { 1334 case ARM::t2LDC2_OFFSET: 1335 case ARM::t2LDC2L_OFFSET: 1336 case ARM::t2LDC2_PRE: 1337 case ARM::t2LDC2L_PRE: 1338 case ARM::t2STC2_OFFSET: 1339 case ARM::t2STC2L_OFFSET: 1340 case ARM::t2STC2_PRE: 1341 case ARM::t2STC2L_PRE: 1342 case ARM::LDC2_OFFSET: 1343 case ARM::LDC2L_OFFSET: 1344 case ARM::LDC2_PRE: 1345 case ARM::LDC2L_PRE: 1346 case ARM::STC2_OFFSET: 1347 case ARM::STC2L_OFFSET: 1348 case ARM::STC2_PRE: 1349 case ARM::STC2L_PRE: 1350 case ARM::t2LDC_OFFSET: 1351 case ARM::t2LDCL_OFFSET: 1352 case ARM::t2LDC_PRE: 1353 case ARM::t2LDCL_PRE: 1354 case ARM::t2STC_OFFSET: 1355 case ARM::t2STCL_OFFSET: 1356 case ARM::t2STC_PRE: 1357 case ARM::t2STCL_PRE: 1358 case ARM::LDC_OFFSET: 1359 case ARM::LDCL_OFFSET: 1360 case ARM::LDC_PRE: 1361 case ARM::LDCL_PRE: 1362 case ARM::STC_OFFSET: 1363 case ARM::STCL_OFFSET: 1364 case ARM::STC_PRE: 1365 case ARM::STCL_PRE: 1366 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1367 Inst.addOperand(MCOperand::CreateImm(imm)); 1368 break; 1369 case ARM::t2LDC2_POST: 1370 case ARM::t2LDC2L_POST: 1371 case ARM::t2STC2_POST: 1372 case ARM::t2STC2L_POST: 1373 case ARM::LDC2_POST: 1374 case ARM::LDC2L_POST: 1375 case ARM::STC2_POST: 1376 case ARM::STC2L_POST: 1377 case ARM::t2LDC_POST: 1378 case ARM::t2LDCL_POST: 1379 case ARM::t2STC_POST: 1380 case ARM::t2STCL_POST: 1381 case ARM::LDC_POST: 1382 case ARM::LDCL_POST: 1383 case ARM::STC_POST: 1384 case ARM::STCL_POST: 1385 imm |= U << 8; 1386 // fall through. 1387 default: 1388 // The 'option' variant doesn't encode 'U' in the immediate since 1389 // the immediate is unsigned [0,255]. 1390 Inst.addOperand(MCOperand::CreateImm(imm)); 1391 break; 1392 } 1393 1394 switch (Inst.getOpcode()) { 1395 case ARM::LDC_OFFSET: 1396 case ARM::LDC_PRE: 1397 case ARM::LDC_POST: 1398 case ARM::LDC_OPTION: 1399 case ARM::LDCL_OFFSET: 1400 case ARM::LDCL_PRE: 1401 case ARM::LDCL_POST: 1402 case ARM::LDCL_OPTION: 1403 case ARM::STC_OFFSET: 1404 case ARM::STC_PRE: 1405 case ARM::STC_POST: 1406 case ARM::STC_OPTION: 1407 case ARM::STCL_OFFSET: 1408 case ARM::STCL_PRE: 1409 case ARM::STCL_POST: 1410 case ARM::STCL_OPTION: 1411 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1412 return MCDisassembler::Fail; 1413 break; 1414 default: 1415 break; 1416 } 1417 1418 return S; 1419 } 1420 1421 static DecodeStatus 1422 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1423 uint64_t Address, const void *Decoder) { 1424 DecodeStatus S = MCDisassembler::Success; 1425 1426 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1427 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1428 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1429 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1430 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1431 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1432 unsigned P = fieldFromInstruction(Insn, 24, 1); 1433 unsigned W = fieldFromInstruction(Insn, 21, 1); 1434 1435 // On stores, the writeback operand precedes Rt. 1436 switch (Inst.getOpcode()) { 1437 case ARM::STR_POST_IMM: 1438 case ARM::STR_POST_REG: 1439 case ARM::STRB_POST_IMM: 1440 case ARM::STRB_POST_REG: 1441 case ARM::STRT_POST_REG: 1442 case ARM::STRT_POST_IMM: 1443 case ARM::STRBT_POST_REG: 1444 case ARM::STRBT_POST_IMM: 1445 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1446 return MCDisassembler::Fail; 1447 break; 1448 default: 1449 break; 1450 } 1451 1452 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1453 return MCDisassembler::Fail; 1454 1455 // On loads, the writeback operand comes after Rt. 1456 switch (Inst.getOpcode()) { 1457 case ARM::LDR_POST_IMM: 1458 case ARM::LDR_POST_REG: 1459 case ARM::LDRB_POST_IMM: 1460 case ARM::LDRB_POST_REG: 1461 case ARM::LDRBT_POST_REG: 1462 case ARM::LDRBT_POST_IMM: 1463 case ARM::LDRT_POST_REG: 1464 case ARM::LDRT_POST_IMM: 1465 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1466 return MCDisassembler::Fail; 1467 break; 1468 default: 1469 break; 1470 } 1471 1472 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1473 return MCDisassembler::Fail; 1474 1475 ARM_AM::AddrOpc Op = ARM_AM::add; 1476 if (!fieldFromInstruction(Insn, 23, 1)) 1477 Op = ARM_AM::sub; 1478 1479 bool writeback = (P == 0) || (W == 1); 1480 unsigned idx_mode = 0; 1481 if (P && writeback) 1482 idx_mode = ARMII::IndexModePre; 1483 else if (!P && writeback) 1484 idx_mode = ARMII::IndexModePost; 1485 1486 if (writeback && (Rn == 15 || Rn == Rt)) 1487 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1488 1489 if (reg) { 1490 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1491 return MCDisassembler::Fail; 1492 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1493 switch( fieldFromInstruction(Insn, 5, 2)) { 1494 case 0: 1495 Opc = ARM_AM::lsl; 1496 break; 1497 case 1: 1498 Opc = ARM_AM::lsr; 1499 break; 1500 case 2: 1501 Opc = ARM_AM::asr; 1502 break; 1503 case 3: 1504 Opc = ARM_AM::ror; 1505 break; 1506 default: 1507 return MCDisassembler::Fail; 1508 } 1509 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1510 if (Opc == ARM_AM::ror && amt == 0) 1511 Opc = ARM_AM::rrx; 1512 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1513 1514 Inst.addOperand(MCOperand::CreateImm(imm)); 1515 } else { 1516 Inst.addOperand(MCOperand::CreateReg(0)); 1517 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1518 Inst.addOperand(MCOperand::CreateImm(tmp)); 1519 } 1520 1521 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1522 return MCDisassembler::Fail; 1523 1524 return S; 1525 } 1526 1527 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1528 uint64_t Address, const void *Decoder) { 1529 DecodeStatus S = MCDisassembler::Success; 1530 1531 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1532 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1533 unsigned type = fieldFromInstruction(Val, 5, 2); 1534 unsigned imm = fieldFromInstruction(Val, 7, 5); 1535 unsigned U = fieldFromInstruction(Val, 12, 1); 1536 1537 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1538 switch (type) { 1539 case 0: 1540 ShOp = ARM_AM::lsl; 1541 break; 1542 case 1: 1543 ShOp = ARM_AM::lsr; 1544 break; 1545 case 2: 1546 ShOp = ARM_AM::asr; 1547 break; 1548 case 3: 1549 ShOp = ARM_AM::ror; 1550 break; 1551 } 1552 1553 if (ShOp == ARM_AM::ror && imm == 0) 1554 ShOp = ARM_AM::rrx; 1555 1556 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1557 return MCDisassembler::Fail; 1558 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1559 return MCDisassembler::Fail; 1560 unsigned shift; 1561 if (U) 1562 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1563 else 1564 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1565 Inst.addOperand(MCOperand::CreateImm(shift)); 1566 1567 return S; 1568 } 1569 1570 static DecodeStatus 1571 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1572 uint64_t Address, const void *Decoder) { 1573 DecodeStatus S = MCDisassembler::Success; 1574 1575 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1576 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1577 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1578 unsigned type = fieldFromInstruction(Insn, 22, 1); 1579 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1580 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1581 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1582 unsigned W = fieldFromInstruction(Insn, 21, 1); 1583 unsigned P = fieldFromInstruction(Insn, 24, 1); 1584 unsigned Rt2 = Rt + 1; 1585 1586 bool writeback = (W == 1) | (P == 0); 1587 1588 // For {LD,ST}RD, Rt must be even, else undefined. 1589 switch (Inst.getOpcode()) { 1590 case ARM::STRD: 1591 case ARM::STRD_PRE: 1592 case ARM::STRD_POST: 1593 case ARM::LDRD: 1594 case ARM::LDRD_PRE: 1595 case ARM::LDRD_POST: 1596 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1597 break; 1598 default: 1599 break; 1600 } 1601 switch (Inst.getOpcode()) { 1602 case ARM::STRD: 1603 case ARM::STRD_PRE: 1604 case ARM::STRD_POST: 1605 if (P == 0 && W == 1) 1606 S = MCDisassembler::SoftFail; 1607 1608 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1609 S = MCDisassembler::SoftFail; 1610 if (type && Rm == 15) 1611 S = MCDisassembler::SoftFail; 1612 if (Rt2 == 15) 1613 S = MCDisassembler::SoftFail; 1614 if (!type && fieldFromInstruction(Insn, 8, 4)) 1615 S = MCDisassembler::SoftFail; 1616 break; 1617 case ARM::STRH: 1618 case ARM::STRH_PRE: 1619 case ARM::STRH_POST: 1620 if (Rt == 15) 1621 S = MCDisassembler::SoftFail; 1622 if (writeback && (Rn == 15 || Rn == Rt)) 1623 S = MCDisassembler::SoftFail; 1624 if (!type && Rm == 15) 1625 S = MCDisassembler::SoftFail; 1626 break; 1627 case ARM::LDRD: 1628 case ARM::LDRD_PRE: 1629 case ARM::LDRD_POST: 1630 if (type && Rn == 15){ 1631 if (Rt2 == 15) 1632 S = MCDisassembler::SoftFail; 1633 break; 1634 } 1635 if (P == 0 && W == 1) 1636 S = MCDisassembler::SoftFail; 1637 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1638 S = MCDisassembler::SoftFail; 1639 if (!type && writeback && Rn == 15) 1640 S = MCDisassembler::SoftFail; 1641 if (writeback && (Rn == Rt || Rn == Rt2)) 1642 S = MCDisassembler::SoftFail; 1643 break; 1644 case ARM::LDRH: 1645 case ARM::LDRH_PRE: 1646 case ARM::LDRH_POST: 1647 if (type && Rn == 15){ 1648 if (Rt == 15) 1649 S = MCDisassembler::SoftFail; 1650 break; 1651 } 1652 if (Rt == 15) 1653 S = MCDisassembler::SoftFail; 1654 if (!type && Rm == 15) 1655 S = MCDisassembler::SoftFail; 1656 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1657 S = MCDisassembler::SoftFail; 1658 break; 1659 case ARM::LDRSH: 1660 case ARM::LDRSH_PRE: 1661 case ARM::LDRSH_POST: 1662 case ARM::LDRSB: 1663 case ARM::LDRSB_PRE: 1664 case ARM::LDRSB_POST: 1665 if (type && Rn == 15){ 1666 if (Rt == 15) 1667 S = MCDisassembler::SoftFail; 1668 break; 1669 } 1670 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1671 S = MCDisassembler::SoftFail; 1672 if (!type && (Rt == 15 || Rm == 15)) 1673 S = MCDisassembler::SoftFail; 1674 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1675 S = MCDisassembler::SoftFail; 1676 break; 1677 default: 1678 break; 1679 } 1680 1681 if (writeback) { // Writeback 1682 if (P) 1683 U |= ARMII::IndexModePre << 9; 1684 else 1685 U |= ARMII::IndexModePost << 9; 1686 1687 // On stores, the writeback operand precedes Rt. 1688 switch (Inst.getOpcode()) { 1689 case ARM::STRD: 1690 case ARM::STRD_PRE: 1691 case ARM::STRD_POST: 1692 case ARM::STRH: 1693 case ARM::STRH_PRE: 1694 case ARM::STRH_POST: 1695 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1696 return MCDisassembler::Fail; 1697 break; 1698 default: 1699 break; 1700 } 1701 } 1702 1703 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1704 return MCDisassembler::Fail; 1705 switch (Inst.getOpcode()) { 1706 case ARM::STRD: 1707 case ARM::STRD_PRE: 1708 case ARM::STRD_POST: 1709 case ARM::LDRD: 1710 case ARM::LDRD_PRE: 1711 case ARM::LDRD_POST: 1712 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1713 return MCDisassembler::Fail; 1714 break; 1715 default: 1716 break; 1717 } 1718 1719 if (writeback) { 1720 // On loads, the writeback operand comes after Rt. 1721 switch (Inst.getOpcode()) { 1722 case ARM::LDRD: 1723 case ARM::LDRD_PRE: 1724 case ARM::LDRD_POST: 1725 case ARM::LDRH: 1726 case ARM::LDRH_PRE: 1727 case ARM::LDRH_POST: 1728 case ARM::LDRSH: 1729 case ARM::LDRSH_PRE: 1730 case ARM::LDRSH_POST: 1731 case ARM::LDRSB: 1732 case ARM::LDRSB_PRE: 1733 case ARM::LDRSB_POST: 1734 case ARM::LDRHTr: 1735 case ARM::LDRSBTr: 1736 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1737 return MCDisassembler::Fail; 1738 break; 1739 default: 1740 break; 1741 } 1742 } 1743 1744 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1745 return MCDisassembler::Fail; 1746 1747 if (type) { 1748 Inst.addOperand(MCOperand::CreateReg(0)); 1749 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1750 } else { 1751 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1752 return MCDisassembler::Fail; 1753 Inst.addOperand(MCOperand::CreateImm(U)); 1754 } 1755 1756 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1757 return MCDisassembler::Fail; 1758 1759 return S; 1760 } 1761 1762 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1763 uint64_t Address, const void *Decoder) { 1764 DecodeStatus S = MCDisassembler::Success; 1765 1766 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1767 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1768 1769 switch (mode) { 1770 case 0: 1771 mode = ARM_AM::da; 1772 break; 1773 case 1: 1774 mode = ARM_AM::ia; 1775 break; 1776 case 2: 1777 mode = ARM_AM::db; 1778 break; 1779 case 3: 1780 mode = ARM_AM::ib; 1781 break; 1782 } 1783 1784 Inst.addOperand(MCOperand::CreateImm(mode)); 1785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1786 return MCDisassembler::Fail; 1787 1788 return S; 1789 } 1790 1791 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1792 uint64_t Address, const void *Decoder) { 1793 DecodeStatus S = MCDisassembler::Success; 1794 1795 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1796 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1797 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1798 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1799 1800 if (pred == 0xF) 1801 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1802 1803 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1804 return MCDisassembler::Fail; 1805 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1806 return MCDisassembler::Fail; 1807 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1808 return MCDisassembler::Fail; 1809 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1810 return MCDisassembler::Fail; 1811 return S; 1812 } 1813 1814 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1815 unsigned Insn, 1816 uint64_t Address, const void *Decoder) { 1817 DecodeStatus S = MCDisassembler::Success; 1818 1819 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1820 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1821 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1822 1823 if (pred == 0xF) { 1824 // Ambiguous with RFE and SRS 1825 switch (Inst.getOpcode()) { 1826 case ARM::LDMDA: 1827 Inst.setOpcode(ARM::RFEDA); 1828 break; 1829 case ARM::LDMDA_UPD: 1830 Inst.setOpcode(ARM::RFEDA_UPD); 1831 break; 1832 case ARM::LDMDB: 1833 Inst.setOpcode(ARM::RFEDB); 1834 break; 1835 case ARM::LDMDB_UPD: 1836 Inst.setOpcode(ARM::RFEDB_UPD); 1837 break; 1838 case ARM::LDMIA: 1839 Inst.setOpcode(ARM::RFEIA); 1840 break; 1841 case ARM::LDMIA_UPD: 1842 Inst.setOpcode(ARM::RFEIA_UPD); 1843 break; 1844 case ARM::LDMIB: 1845 Inst.setOpcode(ARM::RFEIB); 1846 break; 1847 case ARM::LDMIB_UPD: 1848 Inst.setOpcode(ARM::RFEIB_UPD); 1849 break; 1850 case ARM::STMDA: 1851 Inst.setOpcode(ARM::SRSDA); 1852 break; 1853 case ARM::STMDA_UPD: 1854 Inst.setOpcode(ARM::SRSDA_UPD); 1855 break; 1856 case ARM::STMDB: 1857 Inst.setOpcode(ARM::SRSDB); 1858 break; 1859 case ARM::STMDB_UPD: 1860 Inst.setOpcode(ARM::SRSDB_UPD); 1861 break; 1862 case ARM::STMIA: 1863 Inst.setOpcode(ARM::SRSIA); 1864 break; 1865 case ARM::STMIA_UPD: 1866 Inst.setOpcode(ARM::SRSIA_UPD); 1867 break; 1868 case ARM::STMIB: 1869 Inst.setOpcode(ARM::SRSIB); 1870 break; 1871 case ARM::STMIB_UPD: 1872 Inst.setOpcode(ARM::SRSIB_UPD); 1873 break; 1874 default: 1875 return MCDisassembler::Fail; 1876 } 1877 1878 // For stores (which become SRS's, the only operand is the mode. 1879 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1880 // Check SRS encoding constraints 1881 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1882 fieldFromInstruction(Insn, 20, 1) == 0)) 1883 return MCDisassembler::Fail; 1884 1885 Inst.addOperand( 1886 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1887 return S; 1888 } 1889 1890 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1891 } 1892 1893 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1894 return MCDisassembler::Fail; 1895 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1896 return MCDisassembler::Fail; // Tied 1897 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1898 return MCDisassembler::Fail; 1899 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1900 return MCDisassembler::Fail; 1901 1902 return S; 1903 } 1904 1905 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1906 uint64_t Address, const void *Decoder) { 1907 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1908 unsigned M = fieldFromInstruction(Insn, 17, 1); 1909 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1910 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1911 1912 DecodeStatus S = MCDisassembler::Success; 1913 1914 // This decoder is called from multiple location that do not check 1915 // the full encoding is valid before they do. 1916 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1917 fieldFromInstruction(Insn, 16, 1) != 0 || 1918 fieldFromInstruction(Insn, 20, 8) != 0x10) 1919 return MCDisassembler::Fail; 1920 1921 // imod == '01' --> UNPREDICTABLE 1922 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1923 // return failure here. The '01' imod value is unprintable, so there's 1924 // nothing useful we could do even if we returned UNPREDICTABLE. 1925 1926 if (imod == 1) return MCDisassembler::Fail; 1927 1928 if (imod && M) { 1929 Inst.setOpcode(ARM::CPS3p); 1930 Inst.addOperand(MCOperand::CreateImm(imod)); 1931 Inst.addOperand(MCOperand::CreateImm(iflags)); 1932 Inst.addOperand(MCOperand::CreateImm(mode)); 1933 } else if (imod && !M) { 1934 Inst.setOpcode(ARM::CPS2p); 1935 Inst.addOperand(MCOperand::CreateImm(imod)); 1936 Inst.addOperand(MCOperand::CreateImm(iflags)); 1937 if (mode) S = MCDisassembler::SoftFail; 1938 } else if (!imod && M) { 1939 Inst.setOpcode(ARM::CPS1p); 1940 Inst.addOperand(MCOperand::CreateImm(mode)); 1941 if (iflags) S = MCDisassembler::SoftFail; 1942 } else { 1943 // imod == '00' && M == '0' --> UNPREDICTABLE 1944 Inst.setOpcode(ARM::CPS1p); 1945 Inst.addOperand(MCOperand::CreateImm(mode)); 1946 S = MCDisassembler::SoftFail; 1947 } 1948 1949 return S; 1950 } 1951 1952 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1953 uint64_t Address, const void *Decoder) { 1954 unsigned imod = fieldFromInstruction(Insn, 9, 2); 1955 unsigned M = fieldFromInstruction(Insn, 8, 1); 1956 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 1957 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1958 1959 DecodeStatus S = MCDisassembler::Success; 1960 1961 // imod == '01' --> UNPREDICTABLE 1962 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1963 // return failure here. The '01' imod value is unprintable, so there's 1964 // nothing useful we could do even if we returned UNPREDICTABLE. 1965 1966 if (imod == 1) return MCDisassembler::Fail; 1967 1968 if (imod && M) { 1969 Inst.setOpcode(ARM::t2CPS3p); 1970 Inst.addOperand(MCOperand::CreateImm(imod)); 1971 Inst.addOperand(MCOperand::CreateImm(iflags)); 1972 Inst.addOperand(MCOperand::CreateImm(mode)); 1973 } else if (imod && !M) { 1974 Inst.setOpcode(ARM::t2CPS2p); 1975 Inst.addOperand(MCOperand::CreateImm(imod)); 1976 Inst.addOperand(MCOperand::CreateImm(iflags)); 1977 if (mode) S = MCDisassembler::SoftFail; 1978 } else if (!imod && M) { 1979 Inst.setOpcode(ARM::t2CPS1p); 1980 Inst.addOperand(MCOperand::CreateImm(mode)); 1981 if (iflags) S = MCDisassembler::SoftFail; 1982 } else { 1983 // imod == '00' && M == '0' --> this is a HINT instruction 1984 int imm = fieldFromInstruction(Insn, 0, 8); 1985 // HINT are defined only for immediate in [0..4] 1986 if(imm > 4) return MCDisassembler::Fail; 1987 Inst.setOpcode(ARM::t2HINT); 1988 Inst.addOperand(MCOperand::CreateImm(imm)); 1989 } 1990 1991 return S; 1992 } 1993 1994 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 1995 uint64_t Address, const void *Decoder) { 1996 DecodeStatus S = MCDisassembler::Success; 1997 1998 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 1999 unsigned imm = 0; 2000 2001 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2002 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2003 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2004 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2005 2006 if (Inst.getOpcode() == ARM::t2MOVTi16) 2007 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2008 return MCDisassembler::Fail; 2009 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2010 return MCDisassembler::Fail; 2011 2012 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2013 Inst.addOperand(MCOperand::CreateImm(imm)); 2014 2015 return S; 2016 } 2017 2018 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2019 uint64_t Address, const void *Decoder) { 2020 DecodeStatus S = MCDisassembler::Success; 2021 2022 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2023 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2024 unsigned imm = 0; 2025 2026 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2027 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2028 2029 if (Inst.getOpcode() == ARM::MOVTi16) 2030 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2031 return MCDisassembler::Fail; 2032 2033 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2034 return MCDisassembler::Fail; 2035 2036 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2037 Inst.addOperand(MCOperand::CreateImm(imm)); 2038 2039 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2040 return MCDisassembler::Fail; 2041 2042 return S; 2043 } 2044 2045 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2046 uint64_t Address, const void *Decoder) { 2047 DecodeStatus S = MCDisassembler::Success; 2048 2049 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2050 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2051 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2052 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2053 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2054 2055 if (pred == 0xF) 2056 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2057 2058 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2059 return MCDisassembler::Fail; 2060 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2061 return MCDisassembler::Fail; 2062 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2063 return MCDisassembler::Fail; 2064 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2065 return MCDisassembler::Fail; 2066 2067 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2068 return MCDisassembler::Fail; 2069 2070 return S; 2071 } 2072 2073 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2074 uint64_t Address, const void *Decoder) { 2075 DecodeStatus S = MCDisassembler::Success; 2076 2077 unsigned add = fieldFromInstruction(Val, 12, 1); 2078 unsigned imm = fieldFromInstruction(Val, 0, 12); 2079 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2080 2081 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2082 return MCDisassembler::Fail; 2083 2084 if (!add) imm *= -1; 2085 if (imm == 0 && !add) imm = INT32_MIN; 2086 Inst.addOperand(MCOperand::CreateImm(imm)); 2087 if (Rn == 15) 2088 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2089 2090 return S; 2091 } 2092 2093 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2094 uint64_t Address, const void *Decoder) { 2095 DecodeStatus S = MCDisassembler::Success; 2096 2097 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2098 unsigned U = fieldFromInstruction(Val, 8, 1); 2099 unsigned imm = fieldFromInstruction(Val, 0, 8); 2100 2101 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2102 return MCDisassembler::Fail; 2103 2104 if (U) 2105 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2106 else 2107 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2108 2109 return S; 2110 } 2111 2112 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2113 uint64_t Address, const void *Decoder) { 2114 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2115 } 2116 2117 static DecodeStatus 2118 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2119 uint64_t Address, const void *Decoder) { 2120 DecodeStatus Status = MCDisassembler::Success; 2121 2122 // Note the J1 and J2 values are from the encoded instruction. So here 2123 // change them to I1 and I2 values via as documented: 2124 // I1 = NOT(J1 EOR S); 2125 // I2 = NOT(J2 EOR S); 2126 // and build the imm32 with one trailing zero as documented: 2127 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2128 unsigned S = fieldFromInstruction(Insn, 26, 1); 2129 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2130 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2131 unsigned I1 = !(J1 ^ S); 2132 unsigned I2 = !(J2 ^ S); 2133 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2134 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2135 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2136 int imm32 = SignExtend32<25>(tmp << 1); 2137 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2138 true, 4, Inst, Decoder)) 2139 Inst.addOperand(MCOperand::CreateImm(imm32)); 2140 2141 return Status; 2142 } 2143 2144 static DecodeStatus 2145 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2146 uint64_t Address, const void *Decoder) { 2147 DecodeStatus S = MCDisassembler::Success; 2148 2149 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2150 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2151 2152 if (pred == 0xF) { 2153 Inst.setOpcode(ARM::BLXi); 2154 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2155 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2156 true, 4, Inst, Decoder)) 2157 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2158 return S; 2159 } 2160 2161 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2162 true, 4, Inst, Decoder)) 2163 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2164 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2165 return MCDisassembler::Fail; 2166 2167 return S; 2168 } 2169 2170 2171 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2172 uint64_t Address, const void *Decoder) { 2173 DecodeStatus S = MCDisassembler::Success; 2174 2175 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2176 unsigned align = fieldFromInstruction(Val, 4, 2); 2177 2178 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2179 return MCDisassembler::Fail; 2180 if (!align) 2181 Inst.addOperand(MCOperand::CreateImm(0)); 2182 else 2183 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2184 2185 return S; 2186 } 2187 2188 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2189 uint64_t Address, const void *Decoder) { 2190 DecodeStatus S = MCDisassembler::Success; 2191 2192 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2193 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2194 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2195 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2196 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2197 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2198 2199 // First output register 2200 switch (Inst.getOpcode()) { 2201 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2202 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2203 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2204 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2205 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2206 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2207 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2208 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2209 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2210 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2211 return MCDisassembler::Fail; 2212 break; 2213 case ARM::VLD2b16: 2214 case ARM::VLD2b32: 2215 case ARM::VLD2b8: 2216 case ARM::VLD2b16wb_fixed: 2217 case ARM::VLD2b16wb_register: 2218 case ARM::VLD2b32wb_fixed: 2219 case ARM::VLD2b32wb_register: 2220 case ARM::VLD2b8wb_fixed: 2221 case ARM::VLD2b8wb_register: 2222 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2223 return MCDisassembler::Fail; 2224 break; 2225 default: 2226 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2227 return MCDisassembler::Fail; 2228 } 2229 2230 // Second output register 2231 switch (Inst.getOpcode()) { 2232 case ARM::VLD3d8: 2233 case ARM::VLD3d16: 2234 case ARM::VLD3d32: 2235 case ARM::VLD3d8_UPD: 2236 case ARM::VLD3d16_UPD: 2237 case ARM::VLD3d32_UPD: 2238 case ARM::VLD4d8: 2239 case ARM::VLD4d16: 2240 case ARM::VLD4d32: 2241 case ARM::VLD4d8_UPD: 2242 case ARM::VLD4d16_UPD: 2243 case ARM::VLD4d32_UPD: 2244 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2245 return MCDisassembler::Fail; 2246 break; 2247 case ARM::VLD3q8: 2248 case ARM::VLD3q16: 2249 case ARM::VLD3q32: 2250 case ARM::VLD3q8_UPD: 2251 case ARM::VLD3q16_UPD: 2252 case ARM::VLD3q32_UPD: 2253 case ARM::VLD4q8: 2254 case ARM::VLD4q16: 2255 case ARM::VLD4q32: 2256 case ARM::VLD4q8_UPD: 2257 case ARM::VLD4q16_UPD: 2258 case ARM::VLD4q32_UPD: 2259 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2260 return MCDisassembler::Fail; 2261 default: 2262 break; 2263 } 2264 2265 // Third output register 2266 switch(Inst.getOpcode()) { 2267 case ARM::VLD3d8: 2268 case ARM::VLD3d16: 2269 case ARM::VLD3d32: 2270 case ARM::VLD3d8_UPD: 2271 case ARM::VLD3d16_UPD: 2272 case ARM::VLD3d32_UPD: 2273 case ARM::VLD4d8: 2274 case ARM::VLD4d16: 2275 case ARM::VLD4d32: 2276 case ARM::VLD4d8_UPD: 2277 case ARM::VLD4d16_UPD: 2278 case ARM::VLD4d32_UPD: 2279 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2280 return MCDisassembler::Fail; 2281 break; 2282 case ARM::VLD3q8: 2283 case ARM::VLD3q16: 2284 case ARM::VLD3q32: 2285 case ARM::VLD3q8_UPD: 2286 case ARM::VLD3q16_UPD: 2287 case ARM::VLD3q32_UPD: 2288 case ARM::VLD4q8: 2289 case ARM::VLD4q16: 2290 case ARM::VLD4q32: 2291 case ARM::VLD4q8_UPD: 2292 case ARM::VLD4q16_UPD: 2293 case ARM::VLD4q32_UPD: 2294 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2295 return MCDisassembler::Fail; 2296 break; 2297 default: 2298 break; 2299 } 2300 2301 // Fourth output register 2302 switch (Inst.getOpcode()) { 2303 case ARM::VLD4d8: 2304 case ARM::VLD4d16: 2305 case ARM::VLD4d32: 2306 case ARM::VLD4d8_UPD: 2307 case ARM::VLD4d16_UPD: 2308 case ARM::VLD4d32_UPD: 2309 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2310 return MCDisassembler::Fail; 2311 break; 2312 case ARM::VLD4q8: 2313 case ARM::VLD4q16: 2314 case ARM::VLD4q32: 2315 case ARM::VLD4q8_UPD: 2316 case ARM::VLD4q16_UPD: 2317 case ARM::VLD4q32_UPD: 2318 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2319 return MCDisassembler::Fail; 2320 break; 2321 default: 2322 break; 2323 } 2324 2325 // Writeback operand 2326 switch (Inst.getOpcode()) { 2327 case ARM::VLD1d8wb_fixed: 2328 case ARM::VLD1d16wb_fixed: 2329 case ARM::VLD1d32wb_fixed: 2330 case ARM::VLD1d64wb_fixed: 2331 case ARM::VLD1d8wb_register: 2332 case ARM::VLD1d16wb_register: 2333 case ARM::VLD1d32wb_register: 2334 case ARM::VLD1d64wb_register: 2335 case ARM::VLD1q8wb_fixed: 2336 case ARM::VLD1q16wb_fixed: 2337 case ARM::VLD1q32wb_fixed: 2338 case ARM::VLD1q64wb_fixed: 2339 case ARM::VLD1q8wb_register: 2340 case ARM::VLD1q16wb_register: 2341 case ARM::VLD1q32wb_register: 2342 case ARM::VLD1q64wb_register: 2343 case ARM::VLD1d8Twb_fixed: 2344 case ARM::VLD1d8Twb_register: 2345 case ARM::VLD1d16Twb_fixed: 2346 case ARM::VLD1d16Twb_register: 2347 case ARM::VLD1d32Twb_fixed: 2348 case ARM::VLD1d32Twb_register: 2349 case ARM::VLD1d64Twb_fixed: 2350 case ARM::VLD1d64Twb_register: 2351 case ARM::VLD1d8Qwb_fixed: 2352 case ARM::VLD1d8Qwb_register: 2353 case ARM::VLD1d16Qwb_fixed: 2354 case ARM::VLD1d16Qwb_register: 2355 case ARM::VLD1d32Qwb_fixed: 2356 case ARM::VLD1d32Qwb_register: 2357 case ARM::VLD1d64Qwb_fixed: 2358 case ARM::VLD1d64Qwb_register: 2359 case ARM::VLD2d8wb_fixed: 2360 case ARM::VLD2d16wb_fixed: 2361 case ARM::VLD2d32wb_fixed: 2362 case ARM::VLD2q8wb_fixed: 2363 case ARM::VLD2q16wb_fixed: 2364 case ARM::VLD2q32wb_fixed: 2365 case ARM::VLD2d8wb_register: 2366 case ARM::VLD2d16wb_register: 2367 case ARM::VLD2d32wb_register: 2368 case ARM::VLD2q8wb_register: 2369 case ARM::VLD2q16wb_register: 2370 case ARM::VLD2q32wb_register: 2371 case ARM::VLD2b8wb_fixed: 2372 case ARM::VLD2b16wb_fixed: 2373 case ARM::VLD2b32wb_fixed: 2374 case ARM::VLD2b8wb_register: 2375 case ARM::VLD2b16wb_register: 2376 case ARM::VLD2b32wb_register: 2377 Inst.addOperand(MCOperand::CreateImm(0)); 2378 break; 2379 case ARM::VLD3d8_UPD: 2380 case ARM::VLD3d16_UPD: 2381 case ARM::VLD3d32_UPD: 2382 case ARM::VLD3q8_UPD: 2383 case ARM::VLD3q16_UPD: 2384 case ARM::VLD3q32_UPD: 2385 case ARM::VLD4d8_UPD: 2386 case ARM::VLD4d16_UPD: 2387 case ARM::VLD4d32_UPD: 2388 case ARM::VLD4q8_UPD: 2389 case ARM::VLD4q16_UPD: 2390 case ARM::VLD4q32_UPD: 2391 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2392 return MCDisassembler::Fail; 2393 break; 2394 default: 2395 break; 2396 } 2397 2398 // AddrMode6 Base (register+alignment) 2399 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2400 return MCDisassembler::Fail; 2401 2402 // AddrMode6 Offset (register) 2403 switch (Inst.getOpcode()) { 2404 default: 2405 // The below have been updated to have explicit am6offset split 2406 // between fixed and register offset. For those instructions not 2407 // yet updated, we need to add an additional reg0 operand for the 2408 // fixed variant. 2409 // 2410 // The fixed offset encodes as Rm == 0xd, so we check for that. 2411 if (Rm == 0xd) { 2412 Inst.addOperand(MCOperand::CreateReg(0)); 2413 break; 2414 } 2415 // Fall through to handle the register offset variant. 2416 case ARM::VLD1d8wb_fixed: 2417 case ARM::VLD1d16wb_fixed: 2418 case ARM::VLD1d32wb_fixed: 2419 case ARM::VLD1d64wb_fixed: 2420 case ARM::VLD1d8Twb_fixed: 2421 case ARM::VLD1d16Twb_fixed: 2422 case ARM::VLD1d32Twb_fixed: 2423 case ARM::VLD1d64Twb_fixed: 2424 case ARM::VLD1d8Qwb_fixed: 2425 case ARM::VLD1d16Qwb_fixed: 2426 case ARM::VLD1d32Qwb_fixed: 2427 case ARM::VLD1d64Qwb_fixed: 2428 case ARM::VLD1d8wb_register: 2429 case ARM::VLD1d16wb_register: 2430 case ARM::VLD1d32wb_register: 2431 case ARM::VLD1d64wb_register: 2432 case ARM::VLD1q8wb_fixed: 2433 case ARM::VLD1q16wb_fixed: 2434 case ARM::VLD1q32wb_fixed: 2435 case ARM::VLD1q64wb_fixed: 2436 case ARM::VLD1q8wb_register: 2437 case ARM::VLD1q16wb_register: 2438 case ARM::VLD1q32wb_register: 2439 case ARM::VLD1q64wb_register: 2440 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2441 // variant encodes Rm == 0xf. Anything else is a register offset post- 2442 // increment and we need to add the register operand to the instruction. 2443 if (Rm != 0xD && Rm != 0xF && 2444 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2445 return MCDisassembler::Fail; 2446 break; 2447 case ARM::VLD2d8wb_fixed: 2448 case ARM::VLD2d16wb_fixed: 2449 case ARM::VLD2d32wb_fixed: 2450 case ARM::VLD2b8wb_fixed: 2451 case ARM::VLD2b16wb_fixed: 2452 case ARM::VLD2b32wb_fixed: 2453 case ARM::VLD2q8wb_fixed: 2454 case ARM::VLD2q16wb_fixed: 2455 case ARM::VLD2q32wb_fixed: 2456 break; 2457 } 2458 2459 return S; 2460 } 2461 2462 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2463 uint64_t Address, const void *Decoder) { 2464 unsigned type = fieldFromInstruction(Insn, 8, 4); 2465 unsigned align = fieldFromInstruction(Insn, 4, 2); 2466 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2467 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2468 if (type == 10 && align == 3) return MCDisassembler::Fail; 2469 2470 unsigned load = fieldFromInstruction(Insn, 21, 1); 2471 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2472 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2473 } 2474 2475 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2476 uint64_t Address, const void *Decoder) { 2477 unsigned size = fieldFromInstruction(Insn, 6, 2); 2478 if (size == 3) return MCDisassembler::Fail; 2479 2480 unsigned type = fieldFromInstruction(Insn, 8, 4); 2481 unsigned align = fieldFromInstruction(Insn, 4, 2); 2482 if (type == 8 && align == 3) return MCDisassembler::Fail; 2483 if (type == 9 && align == 3) return MCDisassembler::Fail; 2484 2485 unsigned load = fieldFromInstruction(Insn, 21, 1); 2486 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2487 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2488 } 2489 2490 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2491 uint64_t Address, const void *Decoder) { 2492 unsigned size = fieldFromInstruction(Insn, 6, 2); 2493 if (size == 3) return MCDisassembler::Fail; 2494 2495 unsigned align = fieldFromInstruction(Insn, 4, 2); 2496 if (align & 2) return MCDisassembler::Fail; 2497 2498 unsigned load = fieldFromInstruction(Insn, 21, 1); 2499 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2500 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2501 } 2502 2503 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2504 uint64_t Address, const void *Decoder) { 2505 unsigned size = fieldFromInstruction(Insn, 6, 2); 2506 if (size == 3) return MCDisassembler::Fail; 2507 2508 unsigned load = fieldFromInstruction(Insn, 21, 1); 2509 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2510 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2511 } 2512 2513 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2514 uint64_t Address, const void *Decoder) { 2515 DecodeStatus S = MCDisassembler::Success; 2516 2517 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2518 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2519 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2520 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2521 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2522 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2523 2524 // Writeback Operand 2525 switch (Inst.getOpcode()) { 2526 case ARM::VST1d8wb_fixed: 2527 case ARM::VST1d16wb_fixed: 2528 case ARM::VST1d32wb_fixed: 2529 case ARM::VST1d64wb_fixed: 2530 case ARM::VST1d8wb_register: 2531 case ARM::VST1d16wb_register: 2532 case ARM::VST1d32wb_register: 2533 case ARM::VST1d64wb_register: 2534 case ARM::VST1q8wb_fixed: 2535 case ARM::VST1q16wb_fixed: 2536 case ARM::VST1q32wb_fixed: 2537 case ARM::VST1q64wb_fixed: 2538 case ARM::VST1q8wb_register: 2539 case ARM::VST1q16wb_register: 2540 case ARM::VST1q32wb_register: 2541 case ARM::VST1q64wb_register: 2542 case ARM::VST1d8Twb_fixed: 2543 case ARM::VST1d16Twb_fixed: 2544 case ARM::VST1d32Twb_fixed: 2545 case ARM::VST1d64Twb_fixed: 2546 case ARM::VST1d8Twb_register: 2547 case ARM::VST1d16Twb_register: 2548 case ARM::VST1d32Twb_register: 2549 case ARM::VST1d64Twb_register: 2550 case ARM::VST1d8Qwb_fixed: 2551 case ARM::VST1d16Qwb_fixed: 2552 case ARM::VST1d32Qwb_fixed: 2553 case ARM::VST1d64Qwb_fixed: 2554 case ARM::VST1d8Qwb_register: 2555 case ARM::VST1d16Qwb_register: 2556 case ARM::VST1d32Qwb_register: 2557 case ARM::VST1d64Qwb_register: 2558 case ARM::VST2d8wb_fixed: 2559 case ARM::VST2d16wb_fixed: 2560 case ARM::VST2d32wb_fixed: 2561 case ARM::VST2d8wb_register: 2562 case ARM::VST2d16wb_register: 2563 case ARM::VST2d32wb_register: 2564 case ARM::VST2q8wb_fixed: 2565 case ARM::VST2q16wb_fixed: 2566 case ARM::VST2q32wb_fixed: 2567 case ARM::VST2q8wb_register: 2568 case ARM::VST2q16wb_register: 2569 case ARM::VST2q32wb_register: 2570 case ARM::VST2b8wb_fixed: 2571 case ARM::VST2b16wb_fixed: 2572 case ARM::VST2b32wb_fixed: 2573 case ARM::VST2b8wb_register: 2574 case ARM::VST2b16wb_register: 2575 case ARM::VST2b32wb_register: 2576 if (Rm == 0xF) 2577 return MCDisassembler::Fail; 2578 Inst.addOperand(MCOperand::CreateImm(0)); 2579 break; 2580 case ARM::VST3d8_UPD: 2581 case ARM::VST3d16_UPD: 2582 case ARM::VST3d32_UPD: 2583 case ARM::VST3q8_UPD: 2584 case ARM::VST3q16_UPD: 2585 case ARM::VST3q32_UPD: 2586 case ARM::VST4d8_UPD: 2587 case ARM::VST4d16_UPD: 2588 case ARM::VST4d32_UPD: 2589 case ARM::VST4q8_UPD: 2590 case ARM::VST4q16_UPD: 2591 case ARM::VST4q32_UPD: 2592 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2593 return MCDisassembler::Fail; 2594 break; 2595 default: 2596 break; 2597 } 2598 2599 // AddrMode6 Base (register+alignment) 2600 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2601 return MCDisassembler::Fail; 2602 2603 // AddrMode6 Offset (register) 2604 switch (Inst.getOpcode()) { 2605 default: 2606 if (Rm == 0xD) 2607 Inst.addOperand(MCOperand::CreateReg(0)); 2608 else if (Rm != 0xF) { 2609 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2610 return MCDisassembler::Fail; 2611 } 2612 break; 2613 case ARM::VST1d8wb_fixed: 2614 case ARM::VST1d16wb_fixed: 2615 case ARM::VST1d32wb_fixed: 2616 case ARM::VST1d64wb_fixed: 2617 case ARM::VST1q8wb_fixed: 2618 case ARM::VST1q16wb_fixed: 2619 case ARM::VST1q32wb_fixed: 2620 case ARM::VST1q64wb_fixed: 2621 case ARM::VST1d8Twb_fixed: 2622 case ARM::VST1d16Twb_fixed: 2623 case ARM::VST1d32Twb_fixed: 2624 case ARM::VST1d64Twb_fixed: 2625 case ARM::VST1d8Qwb_fixed: 2626 case ARM::VST1d16Qwb_fixed: 2627 case ARM::VST1d32Qwb_fixed: 2628 case ARM::VST1d64Qwb_fixed: 2629 case ARM::VST2d8wb_fixed: 2630 case ARM::VST2d16wb_fixed: 2631 case ARM::VST2d32wb_fixed: 2632 case ARM::VST2q8wb_fixed: 2633 case ARM::VST2q16wb_fixed: 2634 case ARM::VST2q32wb_fixed: 2635 case ARM::VST2b8wb_fixed: 2636 case ARM::VST2b16wb_fixed: 2637 case ARM::VST2b32wb_fixed: 2638 break; 2639 } 2640 2641 2642 // First input register 2643 switch (Inst.getOpcode()) { 2644 case ARM::VST1q16: 2645 case ARM::VST1q32: 2646 case ARM::VST1q64: 2647 case ARM::VST1q8: 2648 case ARM::VST1q16wb_fixed: 2649 case ARM::VST1q16wb_register: 2650 case ARM::VST1q32wb_fixed: 2651 case ARM::VST1q32wb_register: 2652 case ARM::VST1q64wb_fixed: 2653 case ARM::VST1q64wb_register: 2654 case ARM::VST1q8wb_fixed: 2655 case ARM::VST1q8wb_register: 2656 case ARM::VST2d16: 2657 case ARM::VST2d32: 2658 case ARM::VST2d8: 2659 case ARM::VST2d16wb_fixed: 2660 case ARM::VST2d16wb_register: 2661 case ARM::VST2d32wb_fixed: 2662 case ARM::VST2d32wb_register: 2663 case ARM::VST2d8wb_fixed: 2664 case ARM::VST2d8wb_register: 2665 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2666 return MCDisassembler::Fail; 2667 break; 2668 case ARM::VST2b16: 2669 case ARM::VST2b32: 2670 case ARM::VST2b8: 2671 case ARM::VST2b16wb_fixed: 2672 case ARM::VST2b16wb_register: 2673 case ARM::VST2b32wb_fixed: 2674 case ARM::VST2b32wb_register: 2675 case ARM::VST2b8wb_fixed: 2676 case ARM::VST2b8wb_register: 2677 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2678 return MCDisassembler::Fail; 2679 break; 2680 default: 2681 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2682 return MCDisassembler::Fail; 2683 } 2684 2685 // Second input register 2686 switch (Inst.getOpcode()) { 2687 case ARM::VST3d8: 2688 case ARM::VST3d16: 2689 case ARM::VST3d32: 2690 case ARM::VST3d8_UPD: 2691 case ARM::VST3d16_UPD: 2692 case ARM::VST3d32_UPD: 2693 case ARM::VST4d8: 2694 case ARM::VST4d16: 2695 case ARM::VST4d32: 2696 case ARM::VST4d8_UPD: 2697 case ARM::VST4d16_UPD: 2698 case ARM::VST4d32_UPD: 2699 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2700 return MCDisassembler::Fail; 2701 break; 2702 case ARM::VST3q8: 2703 case ARM::VST3q16: 2704 case ARM::VST3q32: 2705 case ARM::VST3q8_UPD: 2706 case ARM::VST3q16_UPD: 2707 case ARM::VST3q32_UPD: 2708 case ARM::VST4q8: 2709 case ARM::VST4q16: 2710 case ARM::VST4q32: 2711 case ARM::VST4q8_UPD: 2712 case ARM::VST4q16_UPD: 2713 case ARM::VST4q32_UPD: 2714 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2715 return MCDisassembler::Fail; 2716 break; 2717 default: 2718 break; 2719 } 2720 2721 // Third input register 2722 switch (Inst.getOpcode()) { 2723 case ARM::VST3d8: 2724 case ARM::VST3d16: 2725 case ARM::VST3d32: 2726 case ARM::VST3d8_UPD: 2727 case ARM::VST3d16_UPD: 2728 case ARM::VST3d32_UPD: 2729 case ARM::VST4d8: 2730 case ARM::VST4d16: 2731 case ARM::VST4d32: 2732 case ARM::VST4d8_UPD: 2733 case ARM::VST4d16_UPD: 2734 case ARM::VST4d32_UPD: 2735 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2736 return MCDisassembler::Fail; 2737 break; 2738 case ARM::VST3q8: 2739 case ARM::VST3q16: 2740 case ARM::VST3q32: 2741 case ARM::VST3q8_UPD: 2742 case ARM::VST3q16_UPD: 2743 case ARM::VST3q32_UPD: 2744 case ARM::VST4q8: 2745 case ARM::VST4q16: 2746 case ARM::VST4q32: 2747 case ARM::VST4q8_UPD: 2748 case ARM::VST4q16_UPD: 2749 case ARM::VST4q32_UPD: 2750 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2751 return MCDisassembler::Fail; 2752 break; 2753 default: 2754 break; 2755 } 2756 2757 // Fourth input register 2758 switch (Inst.getOpcode()) { 2759 case ARM::VST4d8: 2760 case ARM::VST4d16: 2761 case ARM::VST4d32: 2762 case ARM::VST4d8_UPD: 2763 case ARM::VST4d16_UPD: 2764 case ARM::VST4d32_UPD: 2765 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2766 return MCDisassembler::Fail; 2767 break; 2768 case ARM::VST4q8: 2769 case ARM::VST4q16: 2770 case ARM::VST4q32: 2771 case ARM::VST4q8_UPD: 2772 case ARM::VST4q16_UPD: 2773 case ARM::VST4q32_UPD: 2774 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2775 return MCDisassembler::Fail; 2776 break; 2777 default: 2778 break; 2779 } 2780 2781 return S; 2782 } 2783 2784 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2785 uint64_t Address, const void *Decoder) { 2786 DecodeStatus S = MCDisassembler::Success; 2787 2788 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2789 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2790 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2791 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2792 unsigned align = fieldFromInstruction(Insn, 4, 1); 2793 unsigned size = fieldFromInstruction(Insn, 6, 2); 2794 2795 if (size == 0 && align == 1) 2796 return MCDisassembler::Fail; 2797 align *= (1 << size); 2798 2799 switch (Inst.getOpcode()) { 2800 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2801 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2802 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2803 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2804 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2805 return MCDisassembler::Fail; 2806 break; 2807 default: 2808 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2809 return MCDisassembler::Fail; 2810 break; 2811 } 2812 if (Rm != 0xF) { 2813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2814 return MCDisassembler::Fail; 2815 } 2816 2817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2818 return MCDisassembler::Fail; 2819 Inst.addOperand(MCOperand::CreateImm(align)); 2820 2821 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2822 // variant encodes Rm == 0xf. Anything else is a register offset post- 2823 // increment and we need to add the register operand to the instruction. 2824 if (Rm != 0xD && Rm != 0xF && 2825 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2826 return MCDisassembler::Fail; 2827 2828 return S; 2829 } 2830 2831 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2832 uint64_t Address, const void *Decoder) { 2833 DecodeStatus S = MCDisassembler::Success; 2834 2835 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2836 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2837 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2838 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2839 unsigned align = fieldFromInstruction(Insn, 4, 1); 2840 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2841 align *= 2*size; 2842 2843 switch (Inst.getOpcode()) { 2844 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2845 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2846 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2847 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2848 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2849 return MCDisassembler::Fail; 2850 break; 2851 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2852 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2853 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2854 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2855 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2856 return MCDisassembler::Fail; 2857 break; 2858 default: 2859 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2860 return MCDisassembler::Fail; 2861 break; 2862 } 2863 2864 if (Rm != 0xF) 2865 Inst.addOperand(MCOperand::CreateImm(0)); 2866 2867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2868 return MCDisassembler::Fail; 2869 Inst.addOperand(MCOperand::CreateImm(align)); 2870 2871 if (Rm != 0xD && Rm != 0xF) { 2872 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2873 return MCDisassembler::Fail; 2874 } 2875 2876 return S; 2877 } 2878 2879 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2880 uint64_t Address, const void *Decoder) { 2881 DecodeStatus S = MCDisassembler::Success; 2882 2883 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2884 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2885 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2886 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2887 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2888 2889 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2890 return MCDisassembler::Fail; 2891 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2892 return MCDisassembler::Fail; 2893 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2894 return MCDisassembler::Fail; 2895 if (Rm != 0xF) { 2896 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2897 return MCDisassembler::Fail; 2898 } 2899 2900 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2901 return MCDisassembler::Fail; 2902 Inst.addOperand(MCOperand::CreateImm(0)); 2903 2904 if (Rm == 0xD) 2905 Inst.addOperand(MCOperand::CreateReg(0)); 2906 else if (Rm != 0xF) { 2907 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2908 return MCDisassembler::Fail; 2909 } 2910 2911 return S; 2912 } 2913 2914 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2915 uint64_t Address, const void *Decoder) { 2916 DecodeStatus S = MCDisassembler::Success; 2917 2918 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2919 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2920 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2921 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2922 unsigned size = fieldFromInstruction(Insn, 6, 2); 2923 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2924 unsigned align = fieldFromInstruction(Insn, 4, 1); 2925 2926 if (size == 0x3) { 2927 if (align == 0) 2928 return MCDisassembler::Fail; 2929 size = 4; 2930 align = 16; 2931 } else { 2932 if (size == 2) { 2933 size = 1 << size; 2934 align *= 8; 2935 } else { 2936 size = 1 << size; 2937 align *= 4*size; 2938 } 2939 } 2940 2941 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2942 return MCDisassembler::Fail; 2943 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2944 return MCDisassembler::Fail; 2945 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2946 return MCDisassembler::Fail; 2947 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2948 return MCDisassembler::Fail; 2949 if (Rm != 0xF) { 2950 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2951 return MCDisassembler::Fail; 2952 } 2953 2954 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2955 return MCDisassembler::Fail; 2956 Inst.addOperand(MCOperand::CreateImm(align)); 2957 2958 if (Rm == 0xD) 2959 Inst.addOperand(MCOperand::CreateReg(0)); 2960 else if (Rm != 0xF) { 2961 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2962 return MCDisassembler::Fail; 2963 } 2964 2965 return S; 2966 } 2967 2968 static DecodeStatus 2969 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2970 uint64_t Address, const void *Decoder) { 2971 DecodeStatus S = MCDisassembler::Success; 2972 2973 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2974 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2975 unsigned imm = fieldFromInstruction(Insn, 0, 4); 2976 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 2977 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 2978 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 2979 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 2980 unsigned Q = fieldFromInstruction(Insn, 6, 1); 2981 2982 if (Q) { 2983 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2984 return MCDisassembler::Fail; 2985 } else { 2986 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2987 return MCDisassembler::Fail; 2988 } 2989 2990 Inst.addOperand(MCOperand::CreateImm(imm)); 2991 2992 switch (Inst.getOpcode()) { 2993 case ARM::VORRiv4i16: 2994 case ARM::VORRiv2i32: 2995 case ARM::VBICiv4i16: 2996 case ARM::VBICiv2i32: 2997 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2998 return MCDisassembler::Fail; 2999 break; 3000 case ARM::VORRiv8i16: 3001 case ARM::VORRiv4i32: 3002 case ARM::VBICiv8i16: 3003 case ARM::VBICiv4i32: 3004 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3005 return MCDisassembler::Fail; 3006 break; 3007 default: 3008 break; 3009 } 3010 3011 return S; 3012 } 3013 3014 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3015 uint64_t Address, const void *Decoder) { 3016 DecodeStatus S = MCDisassembler::Success; 3017 3018 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3019 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3020 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3021 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3022 unsigned size = fieldFromInstruction(Insn, 18, 2); 3023 3024 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3025 return MCDisassembler::Fail; 3026 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3027 return MCDisassembler::Fail; 3028 Inst.addOperand(MCOperand::CreateImm(8 << size)); 3029 3030 return S; 3031 } 3032 3033 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3034 uint64_t Address, const void *Decoder) { 3035 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 3036 return MCDisassembler::Success; 3037 } 3038 3039 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3040 uint64_t Address, const void *Decoder) { 3041 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 3042 return MCDisassembler::Success; 3043 } 3044 3045 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3046 uint64_t Address, const void *Decoder) { 3047 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 3048 return MCDisassembler::Success; 3049 } 3050 3051 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3052 uint64_t Address, const void *Decoder) { 3053 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 3054 return MCDisassembler::Success; 3055 } 3056 3057 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3058 uint64_t Address, const void *Decoder) { 3059 DecodeStatus S = MCDisassembler::Success; 3060 3061 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3062 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3063 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3064 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3065 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3066 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3067 unsigned op = fieldFromInstruction(Insn, 6, 1); 3068 3069 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3070 return MCDisassembler::Fail; 3071 if (op) { 3072 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3073 return MCDisassembler::Fail; // Writeback 3074 } 3075 3076 switch (Inst.getOpcode()) { 3077 case ARM::VTBL2: 3078 case ARM::VTBX2: 3079 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3080 return MCDisassembler::Fail; 3081 break; 3082 default: 3083 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3084 return MCDisassembler::Fail; 3085 } 3086 3087 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3088 return MCDisassembler::Fail; 3089 3090 return S; 3091 } 3092 3093 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3094 uint64_t Address, const void *Decoder) { 3095 DecodeStatus S = MCDisassembler::Success; 3096 3097 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3098 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3099 3100 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3101 return MCDisassembler::Fail; 3102 3103 switch(Inst.getOpcode()) { 3104 default: 3105 return MCDisassembler::Fail; 3106 case ARM::tADR: 3107 break; // tADR does not explicitly represent the PC as an operand. 3108 case ARM::tADDrSPi: 3109 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3110 break; 3111 } 3112 3113 Inst.addOperand(MCOperand::CreateImm(imm)); 3114 return S; 3115 } 3116 3117 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3118 uint64_t Address, const void *Decoder) { 3119 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3120 true, 2, Inst, Decoder)) 3121 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3122 return MCDisassembler::Success; 3123 } 3124 3125 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3126 uint64_t Address, const void *Decoder) { 3127 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3128 true, 4, Inst, Decoder)) 3129 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3130 return MCDisassembler::Success; 3131 } 3132 3133 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3134 uint64_t Address, const void *Decoder) { 3135 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3136 true, 2, Inst, Decoder)) 3137 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3138 return MCDisassembler::Success; 3139 } 3140 3141 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3142 uint64_t Address, const void *Decoder) { 3143 DecodeStatus S = MCDisassembler::Success; 3144 3145 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3146 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3147 3148 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3149 return MCDisassembler::Fail; 3150 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3151 return MCDisassembler::Fail; 3152 3153 return S; 3154 } 3155 3156 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3157 uint64_t Address, const void *Decoder) { 3158 DecodeStatus S = MCDisassembler::Success; 3159 3160 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3161 unsigned imm = fieldFromInstruction(Val, 3, 5); 3162 3163 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3164 return MCDisassembler::Fail; 3165 Inst.addOperand(MCOperand::CreateImm(imm)); 3166 3167 return S; 3168 } 3169 3170 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3171 uint64_t Address, const void *Decoder) { 3172 unsigned imm = Val << 2; 3173 3174 Inst.addOperand(MCOperand::CreateImm(imm)); 3175 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3176 3177 return MCDisassembler::Success; 3178 } 3179 3180 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3181 uint64_t Address, const void *Decoder) { 3182 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3183 Inst.addOperand(MCOperand::CreateImm(Val)); 3184 3185 return MCDisassembler::Success; 3186 } 3187 3188 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3189 uint64_t Address, const void *Decoder) { 3190 DecodeStatus S = MCDisassembler::Success; 3191 3192 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3193 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3194 unsigned imm = fieldFromInstruction(Val, 0, 2); 3195 3196 // Thumb stores cannot use PC as dest register. 3197 switch (Inst.getOpcode()) { 3198 case ARM::t2STRHs: 3199 case ARM::t2STRBs: 3200 case ARM::t2STRs: 3201 if (Rn == 15) 3202 return MCDisassembler::Fail; 3203 default: 3204 break; 3205 } 3206 3207 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3208 return MCDisassembler::Fail; 3209 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3210 return MCDisassembler::Fail; 3211 Inst.addOperand(MCOperand::CreateImm(imm)); 3212 3213 return S; 3214 } 3215 3216 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3217 uint64_t Address, const void *Decoder) { 3218 DecodeStatus S = MCDisassembler::Success; 3219 3220 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3221 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3222 3223 if (Rn == 15) { 3224 switch (Inst.getOpcode()) { 3225 case ARM::t2LDRBs: 3226 Inst.setOpcode(ARM::t2LDRBpci); 3227 break; 3228 case ARM::t2LDRHs: 3229 Inst.setOpcode(ARM::t2LDRHpci); 3230 break; 3231 case ARM::t2LDRSHs: 3232 Inst.setOpcode(ARM::t2LDRSHpci); 3233 break; 3234 case ARM::t2LDRSBs: 3235 Inst.setOpcode(ARM::t2LDRSBpci); 3236 break; 3237 case ARM::t2LDRs: 3238 Inst.setOpcode(ARM::t2LDRpci); 3239 break; 3240 case ARM::t2PLDs: 3241 Inst.setOpcode(ARM::t2PLDpci); 3242 break; 3243 case ARM::t2PLIs: 3244 Inst.setOpcode(ARM::t2PLIpci); 3245 break; 3246 default: 3247 return MCDisassembler::Fail; 3248 } 3249 3250 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3251 } 3252 3253 if (Rt == 15) { 3254 switch (Inst.getOpcode()) { 3255 case ARM::t2LDRSHs: 3256 return MCDisassembler::Fail; 3257 case ARM::t2LDRHs: 3258 // FIXME: this instruction is only available with MP extensions, 3259 // this should be checked first but we don't have access to the 3260 // feature bits here. 3261 Inst.setOpcode(ARM::t2PLDWs); 3262 break; 3263 default: 3264 break; 3265 } 3266 } 3267 3268 switch (Inst.getOpcode()) { 3269 case ARM::t2PLDs: 3270 case ARM::t2PLDWs: 3271 case ARM::t2PLIs: 3272 break; 3273 default: 3274 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3275 return MCDisassembler::Fail; 3276 } 3277 3278 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3279 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3280 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3281 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3282 return MCDisassembler::Fail; 3283 3284 return S; 3285 } 3286 3287 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3288 uint64_t Address, const void* Decoder) { 3289 DecodeStatus S = MCDisassembler::Success; 3290 3291 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3292 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3293 unsigned U = fieldFromInstruction(Insn, 9, 1); 3294 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3295 imm |= (U << 8); 3296 imm |= (Rn << 9); 3297 3298 if (Rn == 15) { 3299 switch (Inst.getOpcode()) { 3300 case ARM::t2LDRi8: 3301 Inst.setOpcode(ARM::t2LDRpci); 3302 break; 3303 case ARM::t2LDRBi8: 3304 Inst.setOpcode(ARM::t2LDRBpci); 3305 break; 3306 case ARM::t2LDRSBi8: 3307 Inst.setOpcode(ARM::t2LDRSBpci); 3308 break; 3309 case ARM::t2LDRHi8: 3310 Inst.setOpcode(ARM::t2LDRHpci); 3311 break; 3312 case ARM::t2LDRSHi8: 3313 Inst.setOpcode(ARM::t2LDRSHpci); 3314 break; 3315 case ARM::t2PLDi8: 3316 Inst.setOpcode(ARM::t2PLDpci); 3317 break; 3318 case ARM::t2PLIi8: 3319 Inst.setOpcode(ARM::t2PLIpci); 3320 break; 3321 default: 3322 return MCDisassembler::Fail; 3323 } 3324 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3325 } 3326 3327 if (Rt == 15) { 3328 switch (Inst.getOpcode()) { 3329 case ARM::t2LDRSHi8: 3330 return MCDisassembler::Fail; 3331 default: 3332 break; 3333 } 3334 } 3335 3336 switch (Inst.getOpcode()) { 3337 case ARM::t2PLDi8: 3338 case ARM::t2PLIi8: 3339 break; 3340 default: 3341 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3342 return MCDisassembler::Fail; 3343 } 3344 3345 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3346 return MCDisassembler::Fail; 3347 return S; 3348 } 3349 3350 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3351 uint64_t Address, const void* Decoder) { 3352 DecodeStatus S = MCDisassembler::Success; 3353 3354 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3355 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3356 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3357 imm |= (Rn << 13); 3358 3359 if (Rn == 15) { 3360 switch (Inst.getOpcode()) { 3361 case ARM::t2LDRi12: 3362 Inst.setOpcode(ARM::t2LDRpci); 3363 break; 3364 case ARM::t2LDRHi12: 3365 Inst.setOpcode(ARM::t2LDRHpci); 3366 break; 3367 case ARM::t2LDRSHi12: 3368 Inst.setOpcode(ARM::t2LDRSHpci); 3369 break; 3370 case ARM::t2LDRBi12: 3371 Inst.setOpcode(ARM::t2LDRBpci); 3372 break; 3373 case ARM::t2LDRSBi12: 3374 Inst.setOpcode(ARM::t2LDRSBpci); 3375 break; 3376 case ARM::t2PLDi12: 3377 Inst.setOpcode(ARM::t2PLDpci); 3378 break; 3379 case ARM::t2PLIi12: 3380 Inst.setOpcode(ARM::t2PLIpci); 3381 break; 3382 default: 3383 return MCDisassembler::Fail; 3384 } 3385 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3386 } 3387 3388 if (Rt == 15) { 3389 switch (Inst.getOpcode()) { 3390 case ARM::t2LDRSHi12: 3391 return MCDisassembler::Fail; 3392 case ARM::t2LDRHi12: 3393 Inst.setOpcode(ARM::t2PLDi12); 3394 break; 3395 default: 3396 break; 3397 } 3398 } 3399 3400 switch (Inst.getOpcode()) { 3401 case ARM::t2PLDi12: 3402 case ARM::t2PLIi12: 3403 break; 3404 default: 3405 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3406 return MCDisassembler::Fail; 3407 } 3408 3409 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3410 return MCDisassembler::Fail; 3411 return S; 3412 } 3413 3414 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3415 uint64_t Address, const void* Decoder) { 3416 DecodeStatus S = MCDisassembler::Success; 3417 3418 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3419 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3420 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3421 imm |= (Rn << 9); 3422 3423 if (Rn == 15) { 3424 switch (Inst.getOpcode()) { 3425 case ARM::t2LDRT: 3426 Inst.setOpcode(ARM::t2LDRpci); 3427 break; 3428 case ARM::t2LDRBT: 3429 Inst.setOpcode(ARM::t2LDRBpci); 3430 break; 3431 case ARM::t2LDRHT: 3432 Inst.setOpcode(ARM::t2LDRHpci); 3433 break; 3434 case ARM::t2LDRSBT: 3435 Inst.setOpcode(ARM::t2LDRSBpci); 3436 break; 3437 case ARM::t2LDRSHT: 3438 Inst.setOpcode(ARM::t2LDRSHpci); 3439 break; 3440 default: 3441 return MCDisassembler::Fail; 3442 } 3443 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3444 } 3445 3446 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3447 return MCDisassembler::Fail; 3448 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3449 return MCDisassembler::Fail; 3450 return S; 3451 } 3452 3453 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3454 uint64_t Address, const void* Decoder) { 3455 DecodeStatus S = MCDisassembler::Success; 3456 3457 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3458 unsigned U = fieldFromInstruction(Insn, 23, 1); 3459 int imm = fieldFromInstruction(Insn, 0, 12); 3460 3461 if (Rt == 15) { 3462 switch (Inst.getOpcode()) { 3463 case ARM::t2LDRBpci: 3464 case ARM::t2LDRHpci: 3465 Inst.setOpcode(ARM::t2PLDpci); 3466 break; 3467 case ARM::t2LDRSBpci: 3468 Inst.setOpcode(ARM::t2PLIpci); 3469 break; 3470 case ARM::t2LDRSHpci: 3471 return MCDisassembler::Fail; 3472 default: 3473 break; 3474 } 3475 } 3476 3477 switch(Inst.getOpcode()) { 3478 case ARM::t2PLDpci: 3479 case ARM::t2PLIpci: 3480 break; 3481 default: 3482 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3483 return MCDisassembler::Fail; 3484 } 3485 3486 if (!U) { 3487 // Special case for #-0. 3488 if (imm == 0) 3489 imm = INT32_MIN; 3490 else 3491 imm = -imm; 3492 } 3493 Inst.addOperand(MCOperand::CreateImm(imm)); 3494 3495 return S; 3496 } 3497 3498 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3499 uint64_t Address, const void *Decoder) { 3500 if (Val == 0) 3501 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3502 else { 3503 int imm = Val & 0xFF; 3504 3505 if (!(Val & 0x100)) imm *= -1; 3506 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3507 } 3508 3509 return MCDisassembler::Success; 3510 } 3511 3512 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3513 uint64_t Address, const void *Decoder) { 3514 DecodeStatus S = MCDisassembler::Success; 3515 3516 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3517 unsigned imm = fieldFromInstruction(Val, 0, 9); 3518 3519 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3520 return MCDisassembler::Fail; 3521 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3522 return MCDisassembler::Fail; 3523 3524 return S; 3525 } 3526 3527 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3528 uint64_t Address, const void *Decoder) { 3529 DecodeStatus S = MCDisassembler::Success; 3530 3531 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3532 unsigned imm = fieldFromInstruction(Val, 0, 8); 3533 3534 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3535 return MCDisassembler::Fail; 3536 3537 Inst.addOperand(MCOperand::CreateImm(imm)); 3538 3539 return S; 3540 } 3541 3542 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3543 uint64_t Address, const void *Decoder) { 3544 int imm = Val & 0xFF; 3545 if (Val == 0) 3546 imm = INT32_MIN; 3547 else if (!(Val & 0x100)) 3548 imm *= -1; 3549 Inst.addOperand(MCOperand::CreateImm(imm)); 3550 3551 return MCDisassembler::Success; 3552 } 3553 3554 3555 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3556 uint64_t Address, const void *Decoder) { 3557 DecodeStatus S = MCDisassembler::Success; 3558 3559 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3560 unsigned imm = fieldFromInstruction(Val, 0, 9); 3561 3562 // Thumb stores cannot use PC as dest register. 3563 switch (Inst.getOpcode()) { 3564 case ARM::t2STRT: 3565 case ARM::t2STRBT: 3566 case ARM::t2STRHT: 3567 case ARM::t2STRi8: 3568 case ARM::t2STRHi8: 3569 case ARM::t2STRBi8: 3570 if (Rn == 15) 3571 return MCDisassembler::Fail; 3572 break; 3573 default: 3574 break; 3575 } 3576 3577 // Some instructions always use an additive offset. 3578 switch (Inst.getOpcode()) { 3579 case ARM::t2LDRT: 3580 case ARM::t2LDRBT: 3581 case ARM::t2LDRHT: 3582 case ARM::t2LDRSBT: 3583 case ARM::t2LDRSHT: 3584 case ARM::t2STRT: 3585 case ARM::t2STRBT: 3586 case ARM::t2STRHT: 3587 imm |= 0x100; 3588 break; 3589 default: 3590 break; 3591 } 3592 3593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3594 return MCDisassembler::Fail; 3595 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3596 return MCDisassembler::Fail; 3597 3598 return S; 3599 } 3600 3601 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3602 uint64_t Address, const void *Decoder) { 3603 DecodeStatus S = MCDisassembler::Success; 3604 3605 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3606 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3607 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3608 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3609 addr |= Rn << 9; 3610 unsigned load = fieldFromInstruction(Insn, 20, 1); 3611 3612 if (Rn == 15) { 3613 switch (Inst.getOpcode()) { 3614 case ARM::t2LDR_PRE: 3615 case ARM::t2LDR_POST: 3616 Inst.setOpcode(ARM::t2LDRpci); 3617 break; 3618 case ARM::t2LDRB_PRE: 3619 case ARM::t2LDRB_POST: 3620 Inst.setOpcode(ARM::t2LDRBpci); 3621 break; 3622 case ARM::t2LDRH_PRE: 3623 case ARM::t2LDRH_POST: 3624 Inst.setOpcode(ARM::t2LDRHpci); 3625 break; 3626 case ARM::t2LDRSB_PRE: 3627 case ARM::t2LDRSB_POST: 3628 if (Rt == 15) 3629 Inst.setOpcode(ARM::t2PLIpci); 3630 else 3631 Inst.setOpcode(ARM::t2LDRSBpci); 3632 break; 3633 case ARM::t2LDRSH_PRE: 3634 case ARM::t2LDRSH_POST: 3635 Inst.setOpcode(ARM::t2LDRSHpci); 3636 break; 3637 default: 3638 return MCDisassembler::Fail; 3639 } 3640 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3641 } 3642 3643 if (!load) { 3644 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3645 return MCDisassembler::Fail; 3646 } 3647 3648 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3649 return MCDisassembler::Fail; 3650 3651 if (load) { 3652 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3653 return MCDisassembler::Fail; 3654 } 3655 3656 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3657 return MCDisassembler::Fail; 3658 3659 return S; 3660 } 3661 3662 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3663 uint64_t Address, const void *Decoder) { 3664 DecodeStatus S = MCDisassembler::Success; 3665 3666 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3667 unsigned imm = fieldFromInstruction(Val, 0, 12); 3668 3669 // Thumb stores cannot use PC as dest register. 3670 switch (Inst.getOpcode()) { 3671 case ARM::t2STRi12: 3672 case ARM::t2STRBi12: 3673 case ARM::t2STRHi12: 3674 if (Rn == 15) 3675 return MCDisassembler::Fail; 3676 default: 3677 break; 3678 } 3679 3680 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3681 return MCDisassembler::Fail; 3682 Inst.addOperand(MCOperand::CreateImm(imm)); 3683 3684 return S; 3685 } 3686 3687 3688 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3689 uint64_t Address, const void *Decoder) { 3690 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3691 3692 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3693 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3694 Inst.addOperand(MCOperand::CreateImm(imm)); 3695 3696 return MCDisassembler::Success; 3697 } 3698 3699 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3700 uint64_t Address, const void *Decoder) { 3701 DecodeStatus S = MCDisassembler::Success; 3702 3703 if (Inst.getOpcode() == ARM::tADDrSP) { 3704 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3705 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3706 3707 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3708 return MCDisassembler::Fail; 3709 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3710 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3711 return MCDisassembler::Fail; 3712 } else if (Inst.getOpcode() == ARM::tADDspr) { 3713 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3714 3715 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3716 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3717 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3718 return MCDisassembler::Fail; 3719 } 3720 3721 return S; 3722 } 3723 3724 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3725 uint64_t Address, const void *Decoder) { 3726 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3727 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3728 3729 Inst.addOperand(MCOperand::CreateImm(imod)); 3730 Inst.addOperand(MCOperand::CreateImm(flags)); 3731 3732 return MCDisassembler::Success; 3733 } 3734 3735 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3736 uint64_t Address, const void *Decoder) { 3737 DecodeStatus S = MCDisassembler::Success; 3738 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3739 unsigned add = fieldFromInstruction(Insn, 4, 1); 3740 3741 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3742 return MCDisassembler::Fail; 3743 Inst.addOperand(MCOperand::CreateImm(add)); 3744 3745 return S; 3746 } 3747 3748 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3749 uint64_t Address, const void *Decoder) { 3750 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3751 // Note only one trailing zero not two. Also the J1 and J2 values are from 3752 // the encoded instruction. So here change to I1 and I2 values via: 3753 // I1 = NOT(J1 EOR S); 3754 // I2 = NOT(J2 EOR S); 3755 // and build the imm32 with two trailing zeros as documented: 3756 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3757 unsigned S = (Val >> 23) & 1; 3758 unsigned J1 = (Val >> 22) & 1; 3759 unsigned J2 = (Val >> 21) & 1; 3760 unsigned I1 = !(J1 ^ S); 3761 unsigned I2 = !(J2 ^ S); 3762 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3763 int imm32 = SignExtend32<25>(tmp << 1); 3764 3765 if (!tryAddingSymbolicOperand(Address, 3766 (Address & ~2u) + imm32 + 4, 3767 true, 4, Inst, Decoder)) 3768 Inst.addOperand(MCOperand::CreateImm(imm32)); 3769 return MCDisassembler::Success; 3770 } 3771 3772 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3773 uint64_t Address, const void *Decoder) { 3774 if (Val == 0xA || Val == 0xB) 3775 return MCDisassembler::Fail; 3776 3777 Inst.addOperand(MCOperand::CreateImm(Val)); 3778 return MCDisassembler::Success; 3779 } 3780 3781 static DecodeStatus 3782 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3783 uint64_t Address, const void *Decoder) { 3784 DecodeStatus S = MCDisassembler::Success; 3785 3786 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3787 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3788 3789 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3790 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3791 return MCDisassembler::Fail; 3792 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3793 return MCDisassembler::Fail; 3794 return S; 3795 } 3796 3797 static DecodeStatus 3798 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3799 uint64_t Address, const void *Decoder) { 3800 DecodeStatus S = MCDisassembler::Success; 3801 3802 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3803 if (pred == 0xE || pred == 0xF) { 3804 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3805 switch (opc) { 3806 default: 3807 return MCDisassembler::Fail; 3808 case 0xf3bf8f4: 3809 Inst.setOpcode(ARM::t2DSB); 3810 break; 3811 case 0xf3bf8f5: 3812 Inst.setOpcode(ARM::t2DMB); 3813 break; 3814 case 0xf3bf8f6: 3815 Inst.setOpcode(ARM::t2ISB); 3816 break; 3817 } 3818 3819 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3820 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3821 } 3822 3823 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3824 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3825 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3826 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3827 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3828 3829 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3830 return MCDisassembler::Fail; 3831 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3832 return MCDisassembler::Fail; 3833 3834 return S; 3835 } 3836 3837 // Decode a shifted immediate operand. These basically consist 3838 // of an 8-bit value, and a 4-bit directive that specifies either 3839 // a splat operation or a rotation. 3840 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3841 uint64_t Address, const void *Decoder) { 3842 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3843 if (ctrl == 0) { 3844 unsigned byte = fieldFromInstruction(Val, 8, 2); 3845 unsigned imm = fieldFromInstruction(Val, 0, 8); 3846 switch (byte) { 3847 case 0: 3848 Inst.addOperand(MCOperand::CreateImm(imm)); 3849 break; 3850 case 1: 3851 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3852 break; 3853 case 2: 3854 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3855 break; 3856 case 3: 3857 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3858 (imm << 8) | imm)); 3859 break; 3860 } 3861 } else { 3862 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3863 unsigned rot = fieldFromInstruction(Val, 7, 5); 3864 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3865 Inst.addOperand(MCOperand::CreateImm(imm)); 3866 } 3867 3868 return MCDisassembler::Success; 3869 } 3870 3871 static DecodeStatus 3872 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3873 uint64_t Address, const void *Decoder){ 3874 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3875 true, 2, Inst, Decoder)) 3876 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3877 return MCDisassembler::Success; 3878 } 3879 3880 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3881 uint64_t Address, const void *Decoder){ 3882 // Val is passed in as S:J1:J2:imm10:imm11 3883 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3884 // the encoded instruction. So here change to I1 and I2 values via: 3885 // I1 = NOT(J1 EOR S); 3886 // I2 = NOT(J2 EOR S); 3887 // and build the imm32 with one trailing zero as documented: 3888 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 3889 unsigned S = (Val >> 23) & 1; 3890 unsigned J1 = (Val >> 22) & 1; 3891 unsigned J2 = (Val >> 21) & 1; 3892 unsigned I1 = !(J1 ^ S); 3893 unsigned I2 = !(J2 ^ S); 3894 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3895 int imm32 = SignExtend32<25>(tmp << 1); 3896 3897 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 3898 true, 4, Inst, Decoder)) 3899 Inst.addOperand(MCOperand::CreateImm(imm32)); 3900 return MCDisassembler::Success; 3901 } 3902 3903 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3904 uint64_t Address, const void *Decoder) { 3905 if (Val & ~0xf) 3906 return MCDisassembler::Fail; 3907 3908 Inst.addOperand(MCOperand::CreateImm(Val)); 3909 return MCDisassembler::Success; 3910 } 3911 3912 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 3913 uint64_t Address, const void *Decoder) { 3914 if (Val & ~0xf) 3915 return MCDisassembler::Fail; 3916 3917 Inst.addOperand(MCOperand::CreateImm(Val)); 3918 return MCDisassembler::Success; 3919 } 3920 3921 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3922 uint64_t Address, const void *Decoder) { 3923 if (!Val) return MCDisassembler::Fail; 3924 Inst.addOperand(MCOperand::CreateImm(Val)); 3925 return MCDisassembler::Success; 3926 } 3927 3928 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3929 uint64_t Address, const void *Decoder) { 3930 DecodeStatus S = MCDisassembler::Success; 3931 3932 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3933 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3934 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3935 3936 if (Rn == 0xF) 3937 S = MCDisassembler::SoftFail; 3938 3939 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 3940 return MCDisassembler::Fail; 3941 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3942 return MCDisassembler::Fail; 3943 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3944 return MCDisassembler::Fail; 3945 3946 return S; 3947 } 3948 3949 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3950 uint64_t Address, const void *Decoder){ 3951 DecodeStatus S = MCDisassembler::Success; 3952 3953 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3954 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 3955 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3956 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3957 3958 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 3959 return MCDisassembler::Fail; 3960 3961 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 3962 S = MCDisassembler::SoftFail; 3963 3964 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 3965 return MCDisassembler::Fail; 3966 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3967 return MCDisassembler::Fail; 3968 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3969 return MCDisassembler::Fail; 3970 3971 return S; 3972 } 3973 3974 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3975 uint64_t Address, const void *Decoder) { 3976 DecodeStatus S = MCDisassembler::Success; 3977 3978 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3979 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3980 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3981 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3982 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3983 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3984 3985 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3986 3987 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3988 return MCDisassembler::Fail; 3989 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3990 return MCDisassembler::Fail; 3991 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3992 return MCDisassembler::Fail; 3993 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3994 return MCDisassembler::Fail; 3995 3996 return S; 3997 } 3998 3999 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4000 uint64_t Address, const void *Decoder) { 4001 DecodeStatus S = MCDisassembler::Success; 4002 4003 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4004 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4005 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4006 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4007 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4008 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4009 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4010 4011 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4012 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4013 4014 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4015 return MCDisassembler::Fail; 4016 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4017 return MCDisassembler::Fail; 4018 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4019 return MCDisassembler::Fail; 4020 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4021 return MCDisassembler::Fail; 4022 4023 return S; 4024 } 4025 4026 4027 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4028 uint64_t Address, const void *Decoder) { 4029 DecodeStatus S = MCDisassembler::Success; 4030 4031 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4032 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4033 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4034 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4035 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4036 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4037 4038 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4039 4040 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4041 return MCDisassembler::Fail; 4042 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4043 return MCDisassembler::Fail; 4044 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4045 return MCDisassembler::Fail; 4046 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4047 return MCDisassembler::Fail; 4048 4049 return S; 4050 } 4051 4052 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4053 uint64_t Address, const void *Decoder) { 4054 DecodeStatus S = MCDisassembler::Success; 4055 4056 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4057 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4058 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4059 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4060 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4061 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4062 4063 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4064 4065 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4066 return MCDisassembler::Fail; 4067 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4068 return MCDisassembler::Fail; 4069 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4070 return MCDisassembler::Fail; 4071 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4072 return MCDisassembler::Fail; 4073 4074 return S; 4075 } 4076 4077 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4078 uint64_t Address, const void *Decoder) { 4079 DecodeStatus S = MCDisassembler::Success; 4080 4081 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4082 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4083 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4084 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4085 unsigned size = fieldFromInstruction(Insn, 10, 2); 4086 4087 unsigned align = 0; 4088 unsigned index = 0; 4089 switch (size) { 4090 default: 4091 return MCDisassembler::Fail; 4092 case 0: 4093 if (fieldFromInstruction(Insn, 4, 1)) 4094 return MCDisassembler::Fail; // UNDEFINED 4095 index = fieldFromInstruction(Insn, 5, 3); 4096 break; 4097 case 1: 4098 if (fieldFromInstruction(Insn, 5, 1)) 4099 return MCDisassembler::Fail; // UNDEFINED 4100 index = fieldFromInstruction(Insn, 6, 2); 4101 if (fieldFromInstruction(Insn, 4, 1)) 4102 align = 2; 4103 break; 4104 case 2: 4105 if (fieldFromInstruction(Insn, 6, 1)) 4106 return MCDisassembler::Fail; // UNDEFINED 4107 index = fieldFromInstruction(Insn, 7, 1); 4108 4109 switch (fieldFromInstruction(Insn, 4, 2)) { 4110 case 0 : 4111 align = 0; break; 4112 case 3: 4113 align = 4; break; 4114 default: 4115 return MCDisassembler::Fail; 4116 } 4117 break; 4118 } 4119 4120 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4121 return MCDisassembler::Fail; 4122 if (Rm != 0xF) { // Writeback 4123 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4124 return MCDisassembler::Fail; 4125 } 4126 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4127 return MCDisassembler::Fail; 4128 Inst.addOperand(MCOperand::CreateImm(align)); 4129 if (Rm != 0xF) { 4130 if (Rm != 0xD) { 4131 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4132 return MCDisassembler::Fail; 4133 } else 4134 Inst.addOperand(MCOperand::CreateReg(0)); 4135 } 4136 4137 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4138 return MCDisassembler::Fail; 4139 Inst.addOperand(MCOperand::CreateImm(index)); 4140 4141 return S; 4142 } 4143 4144 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4145 uint64_t Address, const void *Decoder) { 4146 DecodeStatus S = MCDisassembler::Success; 4147 4148 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4149 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4150 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4151 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4152 unsigned size = fieldFromInstruction(Insn, 10, 2); 4153 4154 unsigned align = 0; 4155 unsigned index = 0; 4156 switch (size) { 4157 default: 4158 return MCDisassembler::Fail; 4159 case 0: 4160 if (fieldFromInstruction(Insn, 4, 1)) 4161 return MCDisassembler::Fail; // UNDEFINED 4162 index = fieldFromInstruction(Insn, 5, 3); 4163 break; 4164 case 1: 4165 if (fieldFromInstruction(Insn, 5, 1)) 4166 return MCDisassembler::Fail; // UNDEFINED 4167 index = fieldFromInstruction(Insn, 6, 2); 4168 if (fieldFromInstruction(Insn, 4, 1)) 4169 align = 2; 4170 break; 4171 case 2: 4172 if (fieldFromInstruction(Insn, 6, 1)) 4173 return MCDisassembler::Fail; // UNDEFINED 4174 index = fieldFromInstruction(Insn, 7, 1); 4175 4176 switch (fieldFromInstruction(Insn, 4, 2)) { 4177 case 0: 4178 align = 0; break; 4179 case 3: 4180 align = 4; break; 4181 default: 4182 return MCDisassembler::Fail; 4183 } 4184 break; 4185 } 4186 4187 if (Rm != 0xF) { // Writeback 4188 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4189 return MCDisassembler::Fail; 4190 } 4191 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4192 return MCDisassembler::Fail; 4193 Inst.addOperand(MCOperand::CreateImm(align)); 4194 if (Rm != 0xF) { 4195 if (Rm != 0xD) { 4196 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4197 return MCDisassembler::Fail; 4198 } else 4199 Inst.addOperand(MCOperand::CreateReg(0)); 4200 } 4201 4202 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4203 return MCDisassembler::Fail; 4204 Inst.addOperand(MCOperand::CreateImm(index)); 4205 4206 return S; 4207 } 4208 4209 4210 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4211 uint64_t Address, const void *Decoder) { 4212 DecodeStatus S = MCDisassembler::Success; 4213 4214 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4215 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4216 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4217 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4218 unsigned size = fieldFromInstruction(Insn, 10, 2); 4219 4220 unsigned align = 0; 4221 unsigned index = 0; 4222 unsigned inc = 1; 4223 switch (size) { 4224 default: 4225 return MCDisassembler::Fail; 4226 case 0: 4227 index = fieldFromInstruction(Insn, 5, 3); 4228 if (fieldFromInstruction(Insn, 4, 1)) 4229 align = 2; 4230 break; 4231 case 1: 4232 index = fieldFromInstruction(Insn, 6, 2); 4233 if (fieldFromInstruction(Insn, 4, 1)) 4234 align = 4; 4235 if (fieldFromInstruction(Insn, 5, 1)) 4236 inc = 2; 4237 break; 4238 case 2: 4239 if (fieldFromInstruction(Insn, 5, 1)) 4240 return MCDisassembler::Fail; // UNDEFINED 4241 index = fieldFromInstruction(Insn, 7, 1); 4242 if (fieldFromInstruction(Insn, 4, 1) != 0) 4243 align = 8; 4244 if (fieldFromInstruction(Insn, 6, 1)) 4245 inc = 2; 4246 break; 4247 } 4248 4249 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4250 return MCDisassembler::Fail; 4251 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4252 return MCDisassembler::Fail; 4253 if (Rm != 0xF) { // Writeback 4254 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4255 return MCDisassembler::Fail; 4256 } 4257 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4258 return MCDisassembler::Fail; 4259 Inst.addOperand(MCOperand::CreateImm(align)); 4260 if (Rm != 0xF) { 4261 if (Rm != 0xD) { 4262 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4263 return MCDisassembler::Fail; 4264 } else 4265 Inst.addOperand(MCOperand::CreateReg(0)); 4266 } 4267 4268 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4269 return MCDisassembler::Fail; 4270 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4271 return MCDisassembler::Fail; 4272 Inst.addOperand(MCOperand::CreateImm(index)); 4273 4274 return S; 4275 } 4276 4277 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4278 uint64_t Address, const void *Decoder) { 4279 DecodeStatus S = MCDisassembler::Success; 4280 4281 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4282 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4283 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4284 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4285 unsigned size = fieldFromInstruction(Insn, 10, 2); 4286 4287 unsigned align = 0; 4288 unsigned index = 0; 4289 unsigned inc = 1; 4290 switch (size) { 4291 default: 4292 return MCDisassembler::Fail; 4293 case 0: 4294 index = fieldFromInstruction(Insn, 5, 3); 4295 if (fieldFromInstruction(Insn, 4, 1)) 4296 align = 2; 4297 break; 4298 case 1: 4299 index = fieldFromInstruction(Insn, 6, 2); 4300 if (fieldFromInstruction(Insn, 4, 1)) 4301 align = 4; 4302 if (fieldFromInstruction(Insn, 5, 1)) 4303 inc = 2; 4304 break; 4305 case 2: 4306 if (fieldFromInstruction(Insn, 5, 1)) 4307 return MCDisassembler::Fail; // UNDEFINED 4308 index = fieldFromInstruction(Insn, 7, 1); 4309 if (fieldFromInstruction(Insn, 4, 1) != 0) 4310 align = 8; 4311 if (fieldFromInstruction(Insn, 6, 1)) 4312 inc = 2; 4313 break; 4314 } 4315 4316 if (Rm != 0xF) { // Writeback 4317 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4318 return MCDisassembler::Fail; 4319 } 4320 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4321 return MCDisassembler::Fail; 4322 Inst.addOperand(MCOperand::CreateImm(align)); 4323 if (Rm != 0xF) { 4324 if (Rm != 0xD) { 4325 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4326 return MCDisassembler::Fail; 4327 } else 4328 Inst.addOperand(MCOperand::CreateReg(0)); 4329 } 4330 4331 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4332 return MCDisassembler::Fail; 4333 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4334 return MCDisassembler::Fail; 4335 Inst.addOperand(MCOperand::CreateImm(index)); 4336 4337 return S; 4338 } 4339 4340 4341 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4342 uint64_t Address, const void *Decoder) { 4343 DecodeStatus S = MCDisassembler::Success; 4344 4345 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4346 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4347 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4348 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4349 unsigned size = fieldFromInstruction(Insn, 10, 2); 4350 4351 unsigned align = 0; 4352 unsigned index = 0; 4353 unsigned inc = 1; 4354 switch (size) { 4355 default: 4356 return MCDisassembler::Fail; 4357 case 0: 4358 if (fieldFromInstruction(Insn, 4, 1)) 4359 return MCDisassembler::Fail; // UNDEFINED 4360 index = fieldFromInstruction(Insn, 5, 3); 4361 break; 4362 case 1: 4363 if (fieldFromInstruction(Insn, 4, 1)) 4364 return MCDisassembler::Fail; // UNDEFINED 4365 index = fieldFromInstruction(Insn, 6, 2); 4366 if (fieldFromInstruction(Insn, 5, 1)) 4367 inc = 2; 4368 break; 4369 case 2: 4370 if (fieldFromInstruction(Insn, 4, 2)) 4371 return MCDisassembler::Fail; // UNDEFINED 4372 index = fieldFromInstruction(Insn, 7, 1); 4373 if (fieldFromInstruction(Insn, 6, 1)) 4374 inc = 2; 4375 break; 4376 } 4377 4378 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4379 return MCDisassembler::Fail; 4380 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4381 return MCDisassembler::Fail; 4382 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4383 return MCDisassembler::Fail; 4384 4385 if (Rm != 0xF) { // Writeback 4386 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4387 return MCDisassembler::Fail; 4388 } 4389 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4390 return MCDisassembler::Fail; 4391 Inst.addOperand(MCOperand::CreateImm(align)); 4392 if (Rm != 0xF) { 4393 if (Rm != 0xD) { 4394 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4395 return MCDisassembler::Fail; 4396 } else 4397 Inst.addOperand(MCOperand::CreateReg(0)); 4398 } 4399 4400 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4401 return MCDisassembler::Fail; 4402 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4403 return MCDisassembler::Fail; 4404 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4405 return MCDisassembler::Fail; 4406 Inst.addOperand(MCOperand::CreateImm(index)); 4407 4408 return S; 4409 } 4410 4411 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4412 uint64_t Address, const void *Decoder) { 4413 DecodeStatus S = MCDisassembler::Success; 4414 4415 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4416 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4417 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4418 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4419 unsigned size = fieldFromInstruction(Insn, 10, 2); 4420 4421 unsigned align = 0; 4422 unsigned index = 0; 4423 unsigned inc = 1; 4424 switch (size) { 4425 default: 4426 return MCDisassembler::Fail; 4427 case 0: 4428 if (fieldFromInstruction(Insn, 4, 1)) 4429 return MCDisassembler::Fail; // UNDEFINED 4430 index = fieldFromInstruction(Insn, 5, 3); 4431 break; 4432 case 1: 4433 if (fieldFromInstruction(Insn, 4, 1)) 4434 return MCDisassembler::Fail; // UNDEFINED 4435 index = fieldFromInstruction(Insn, 6, 2); 4436 if (fieldFromInstruction(Insn, 5, 1)) 4437 inc = 2; 4438 break; 4439 case 2: 4440 if (fieldFromInstruction(Insn, 4, 2)) 4441 return MCDisassembler::Fail; // UNDEFINED 4442 index = fieldFromInstruction(Insn, 7, 1); 4443 if (fieldFromInstruction(Insn, 6, 1)) 4444 inc = 2; 4445 break; 4446 } 4447 4448 if (Rm != 0xF) { // Writeback 4449 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4450 return MCDisassembler::Fail; 4451 } 4452 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4453 return MCDisassembler::Fail; 4454 Inst.addOperand(MCOperand::CreateImm(align)); 4455 if (Rm != 0xF) { 4456 if (Rm != 0xD) { 4457 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4458 return MCDisassembler::Fail; 4459 } else 4460 Inst.addOperand(MCOperand::CreateReg(0)); 4461 } 4462 4463 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4464 return MCDisassembler::Fail; 4465 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4466 return MCDisassembler::Fail; 4467 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4468 return MCDisassembler::Fail; 4469 Inst.addOperand(MCOperand::CreateImm(index)); 4470 4471 return S; 4472 } 4473 4474 4475 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4476 uint64_t Address, const void *Decoder) { 4477 DecodeStatus S = MCDisassembler::Success; 4478 4479 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4480 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4481 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4482 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4483 unsigned size = fieldFromInstruction(Insn, 10, 2); 4484 4485 unsigned align = 0; 4486 unsigned index = 0; 4487 unsigned inc = 1; 4488 switch (size) { 4489 default: 4490 return MCDisassembler::Fail; 4491 case 0: 4492 if (fieldFromInstruction(Insn, 4, 1)) 4493 align = 4; 4494 index = fieldFromInstruction(Insn, 5, 3); 4495 break; 4496 case 1: 4497 if (fieldFromInstruction(Insn, 4, 1)) 4498 align = 8; 4499 index = fieldFromInstruction(Insn, 6, 2); 4500 if (fieldFromInstruction(Insn, 5, 1)) 4501 inc = 2; 4502 break; 4503 case 2: 4504 switch (fieldFromInstruction(Insn, 4, 2)) { 4505 case 0: 4506 align = 0; break; 4507 case 3: 4508 return MCDisassembler::Fail; 4509 default: 4510 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4511 } 4512 4513 index = fieldFromInstruction(Insn, 7, 1); 4514 if (fieldFromInstruction(Insn, 6, 1)) 4515 inc = 2; 4516 break; 4517 } 4518 4519 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4520 return MCDisassembler::Fail; 4521 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4522 return MCDisassembler::Fail; 4523 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4524 return MCDisassembler::Fail; 4525 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4526 return MCDisassembler::Fail; 4527 4528 if (Rm != 0xF) { // Writeback 4529 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4530 return MCDisassembler::Fail; 4531 } 4532 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4533 return MCDisassembler::Fail; 4534 Inst.addOperand(MCOperand::CreateImm(align)); 4535 if (Rm != 0xF) { 4536 if (Rm != 0xD) { 4537 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4538 return MCDisassembler::Fail; 4539 } else 4540 Inst.addOperand(MCOperand::CreateReg(0)); 4541 } 4542 4543 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4544 return MCDisassembler::Fail; 4545 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4546 return MCDisassembler::Fail; 4547 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4548 return MCDisassembler::Fail; 4549 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4550 return MCDisassembler::Fail; 4551 Inst.addOperand(MCOperand::CreateImm(index)); 4552 4553 return S; 4554 } 4555 4556 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4557 uint64_t Address, const void *Decoder) { 4558 DecodeStatus S = MCDisassembler::Success; 4559 4560 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4561 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4562 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4563 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4564 unsigned size = fieldFromInstruction(Insn, 10, 2); 4565 4566 unsigned align = 0; 4567 unsigned index = 0; 4568 unsigned inc = 1; 4569 switch (size) { 4570 default: 4571 return MCDisassembler::Fail; 4572 case 0: 4573 if (fieldFromInstruction(Insn, 4, 1)) 4574 align = 4; 4575 index = fieldFromInstruction(Insn, 5, 3); 4576 break; 4577 case 1: 4578 if (fieldFromInstruction(Insn, 4, 1)) 4579 align = 8; 4580 index = fieldFromInstruction(Insn, 6, 2); 4581 if (fieldFromInstruction(Insn, 5, 1)) 4582 inc = 2; 4583 break; 4584 case 2: 4585 switch (fieldFromInstruction(Insn, 4, 2)) { 4586 case 0: 4587 align = 0; break; 4588 case 3: 4589 return MCDisassembler::Fail; 4590 default: 4591 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4592 } 4593 4594 index = fieldFromInstruction(Insn, 7, 1); 4595 if (fieldFromInstruction(Insn, 6, 1)) 4596 inc = 2; 4597 break; 4598 } 4599 4600 if (Rm != 0xF) { // Writeback 4601 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4602 return MCDisassembler::Fail; 4603 } 4604 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4605 return MCDisassembler::Fail; 4606 Inst.addOperand(MCOperand::CreateImm(align)); 4607 if (Rm != 0xF) { 4608 if (Rm != 0xD) { 4609 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4610 return MCDisassembler::Fail; 4611 } else 4612 Inst.addOperand(MCOperand::CreateReg(0)); 4613 } 4614 4615 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4616 return MCDisassembler::Fail; 4617 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4618 return MCDisassembler::Fail; 4619 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4620 return MCDisassembler::Fail; 4621 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4622 return MCDisassembler::Fail; 4623 Inst.addOperand(MCOperand::CreateImm(index)); 4624 4625 return S; 4626 } 4627 4628 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4629 uint64_t Address, const void *Decoder) { 4630 DecodeStatus S = MCDisassembler::Success; 4631 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4632 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4633 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4634 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4635 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4636 4637 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4638 S = MCDisassembler::SoftFail; 4639 4640 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4641 return MCDisassembler::Fail; 4642 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4643 return MCDisassembler::Fail; 4644 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4645 return MCDisassembler::Fail; 4646 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4647 return MCDisassembler::Fail; 4648 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4649 return MCDisassembler::Fail; 4650 4651 return S; 4652 } 4653 4654 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4655 uint64_t Address, const void *Decoder) { 4656 DecodeStatus S = MCDisassembler::Success; 4657 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4658 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4659 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4660 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4661 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4662 4663 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4664 S = MCDisassembler::SoftFail; 4665 4666 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4667 return MCDisassembler::Fail; 4668 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4669 return MCDisassembler::Fail; 4670 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4671 return MCDisassembler::Fail; 4672 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4673 return MCDisassembler::Fail; 4674 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4675 return MCDisassembler::Fail; 4676 4677 return S; 4678 } 4679 4680 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4681 uint64_t Address, const void *Decoder) { 4682 DecodeStatus S = MCDisassembler::Success; 4683 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4684 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4685 4686 if (pred == 0xF) { 4687 pred = 0xE; 4688 S = MCDisassembler::SoftFail; 4689 } 4690 4691 if (mask == 0x0) 4692 return MCDisassembler::Fail; 4693 4694 Inst.addOperand(MCOperand::CreateImm(pred)); 4695 Inst.addOperand(MCOperand::CreateImm(mask)); 4696 return S; 4697 } 4698 4699 static DecodeStatus 4700 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4701 uint64_t Address, const void *Decoder) { 4702 DecodeStatus S = MCDisassembler::Success; 4703 4704 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4705 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4706 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4707 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4708 unsigned W = fieldFromInstruction(Insn, 21, 1); 4709 unsigned U = fieldFromInstruction(Insn, 23, 1); 4710 unsigned P = fieldFromInstruction(Insn, 24, 1); 4711 bool writeback = (W == 1) | (P == 0); 4712 4713 addr |= (U << 8) | (Rn << 9); 4714 4715 if (writeback && (Rn == Rt || Rn == Rt2)) 4716 Check(S, MCDisassembler::SoftFail); 4717 if (Rt == Rt2) 4718 Check(S, MCDisassembler::SoftFail); 4719 4720 // Rt 4721 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4722 return MCDisassembler::Fail; 4723 // Rt2 4724 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4725 return MCDisassembler::Fail; 4726 // Writeback operand 4727 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4728 return MCDisassembler::Fail; 4729 // addr 4730 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4731 return MCDisassembler::Fail; 4732 4733 return S; 4734 } 4735 4736 static DecodeStatus 4737 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4738 uint64_t Address, const void *Decoder) { 4739 DecodeStatus S = MCDisassembler::Success; 4740 4741 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4742 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4743 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4744 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4745 unsigned W = fieldFromInstruction(Insn, 21, 1); 4746 unsigned U = fieldFromInstruction(Insn, 23, 1); 4747 unsigned P = fieldFromInstruction(Insn, 24, 1); 4748 bool writeback = (W == 1) | (P == 0); 4749 4750 addr |= (U << 8) | (Rn << 9); 4751 4752 if (writeback && (Rn == Rt || Rn == Rt2)) 4753 Check(S, MCDisassembler::SoftFail); 4754 4755 // Writeback operand 4756 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4757 return MCDisassembler::Fail; 4758 // Rt 4759 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4760 return MCDisassembler::Fail; 4761 // Rt2 4762 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4763 return MCDisassembler::Fail; 4764 // addr 4765 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4766 return MCDisassembler::Fail; 4767 4768 return S; 4769 } 4770 4771 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4772 uint64_t Address, const void *Decoder) { 4773 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4774 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4775 if (sign1 != sign2) return MCDisassembler::Fail; 4776 4777 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4778 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4779 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4780 Val |= sign1 << 12; 4781 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4782 4783 return MCDisassembler::Success; 4784 } 4785 4786 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4787 uint64_t Address, 4788 const void *Decoder) { 4789 DecodeStatus S = MCDisassembler::Success; 4790 4791 // Shift of "asr #32" is not allowed in Thumb2 mode. 4792 if (Val == 0x20) S = MCDisassembler::SoftFail; 4793 Inst.addOperand(MCOperand::CreateImm(Val)); 4794 return S; 4795 } 4796 4797 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4798 uint64_t Address, const void *Decoder) { 4799 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4800 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4801 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4802 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4803 4804 if (pred == 0xF) 4805 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4806 4807 DecodeStatus S = MCDisassembler::Success; 4808 4809 if (Rt == Rn || Rn == Rt2) 4810 S = MCDisassembler::SoftFail; 4811 4812 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4813 return MCDisassembler::Fail; 4814 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4815 return MCDisassembler::Fail; 4816 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4817 return MCDisassembler::Fail; 4818 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4819 return MCDisassembler::Fail; 4820 4821 return S; 4822 } 4823 4824 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4825 uint64_t Address, const void *Decoder) { 4826 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4827 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4828 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4829 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4830 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4831 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4832 unsigned op = fieldFromInstruction(Insn, 5, 1); 4833 4834 DecodeStatus S = MCDisassembler::Success; 4835 4836 // VMOVv2f32 is ambiguous with these decodings. 4837 if (!(imm & 0x38) && cmode == 0xF) { 4838 if (op == 1) return MCDisassembler::Fail; 4839 Inst.setOpcode(ARM::VMOVv2f32); 4840 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4841 } 4842 4843 if (!(imm & 0x20)) return MCDisassembler::Fail; 4844 4845 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4846 return MCDisassembler::Fail; 4847 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4848 return MCDisassembler::Fail; 4849 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4850 4851 return S; 4852 } 4853 4854 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4855 uint64_t Address, const void *Decoder) { 4856 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4857 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4858 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4859 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4860 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4861 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4862 unsigned op = fieldFromInstruction(Insn, 5, 1); 4863 4864 DecodeStatus S = MCDisassembler::Success; 4865 4866 // VMOVv4f32 is ambiguous with these decodings. 4867 if (!(imm & 0x38) && cmode == 0xF) { 4868 if (op == 1) return MCDisassembler::Fail; 4869 Inst.setOpcode(ARM::VMOVv4f32); 4870 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4871 } 4872 4873 if (!(imm & 0x20)) return MCDisassembler::Fail; 4874 4875 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4876 return MCDisassembler::Fail; 4877 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4878 return MCDisassembler::Fail; 4879 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4880 4881 return S; 4882 } 4883 4884 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 4885 const void *Decoder) 4886 { 4887 unsigned Imm = fieldFromInstruction(Insn, 0, 3); 4888 if (Imm > 4) return MCDisassembler::Fail; 4889 Inst.addOperand(MCOperand::CreateImm(Imm)); 4890 return MCDisassembler::Success; 4891 } 4892 4893 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4894 uint64_t Address, const void *Decoder) { 4895 DecodeStatus S = MCDisassembler::Success; 4896 4897 unsigned Rn = fieldFromInstruction(Val, 16, 4); 4898 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4899 unsigned Rm = fieldFromInstruction(Val, 0, 4); 4900 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 4901 unsigned Cond = fieldFromInstruction(Val, 28, 4); 4902 4903 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 4904 S = MCDisassembler::SoftFail; 4905 4906 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4907 return MCDisassembler::Fail; 4908 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4909 return MCDisassembler::Fail; 4910 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4911 return MCDisassembler::Fail; 4912 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4913 return MCDisassembler::Fail; 4914 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4915 return MCDisassembler::Fail; 4916 4917 return S; 4918 } 4919 4920 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4921 uint64_t Address, const void *Decoder) { 4922 4923 DecodeStatus S = MCDisassembler::Success; 4924 4925 unsigned CRm = fieldFromInstruction(Val, 0, 4); 4926 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 4927 unsigned cop = fieldFromInstruction(Val, 8, 4); 4928 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4929 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 4930 4931 if ((cop & ~0x1) == 0xa) 4932 return MCDisassembler::Fail; 4933 4934 if (Rt == Rt2) 4935 S = MCDisassembler::SoftFail; 4936 4937 Inst.addOperand(MCOperand::CreateImm(cop)); 4938 Inst.addOperand(MCOperand::CreateImm(opc1)); 4939 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4940 return MCDisassembler::Fail; 4941 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4942 return MCDisassembler::Fail; 4943 Inst.addOperand(MCOperand::CreateImm(CRm)); 4944 4945 return S; 4946 } 4947 4948